source: trunk/softs/tests_ccvcache_v4/test_dtlb_inval/test.S @ 312

Last change on this file since 312 was 232, checked in by alain, 12 years ago

Introducing the elementary tests for a TSAR mono-cluster
mono-processor platform with MMU using the vci_cc_vcache_v4
such as the "tsarv4_mono_mmu".
(assemby level tests written by Manuel Bouyer)
File size: 2.5 KB
Line 
1/*
2 * dtlb inval: a write to VC_DTLB_INVAL should invalidate the corresponding
3 * dtlb entry. On a ccvcache, VC_DTLB_INVAL should not be needed, and
4 * the first access after clearing pte2_a should fail
5 */
6#include <registers.h>
7#include <misc.h>
8#include <vcache.h>
9        .text
10        .globl  _start
11_start:
12        .set noreorder
13        la      k0, TTY_BASE
14        la      k1, EXIT_BASE
15
16        PRINT(startstr)
17
18        /* reset cop0 status (keep BEV) */
19        lui     a0, 0x0040;
20        mtc0    a0, COP0_STATUS
21
22        la      a0, pte1_a
23        srl     a0, a0, 13
24        mtc2    a0, VC_PTPR
25        nop
26
27        li      a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
28        mtc2    a0, VC_TLB_EN
29
30        PRINT(mmustr)
31        la      t0, testval + 0x00200000
32        lw      a0, 0(t0);
33        PRINTX
34        PUTCHAR(' ')
35        la      a0, pte2_a
36        sw      zero, 0(a0) /* invalidate PTE2 entry */
37        sync
38        la      t0, testval + 0x00200000
39        lw      a0, 0(t0); /* TLB entry not invalidated yet, we can do this */
40        PRINTX
41        PUTCHAR('\n')
42        la      t0, testval + 0x00200000
43        mtc2    t0, VC_DTLB_INVAL /* invalidate VA */
44        lw      a0, 0(t0); /* now this should fail */
45        PRINTX
46        PUTCHAR('\n')
47
48        /* we should not get there */
49        EXIT(1)
50
51        .globl excep
52excep:
53        .set noreorder
54        PRINT(statusstr)
55        mfc0    a0, COP0_STATUS
56        PRINTX
57
58        PRINT(causestr)
59        mfc0    a0, COP0_CAUSE
60        PRINTX
61
62        PRINT(pcstr)
63        mfc0    a0, COP0_EXPC
64        PRINTX
65
66        PRINT(badvastr)
67        mfc0    a0, COP_0_BADVADDR
68        PRINTX
69
70        PUTCHAR('\n')
71        /* we should get there */
72        EXIT(0)
73
74        .rodata:
75statusstr: .ascii "status \0"
76causestr: .ascii " cause \0"
77pcstr: .ascii " pc \0"
78badvastr: .ascii " badva \0"
79mmustr: .ascii "mmu started \0"
80startstr: .ascii "start\n\0"
81
82        .org EXCEP_ADDRESS - BOOT_ADDRESS
83        .globl evect
84evect:
85        j       excep
86        nop
87
88        .data
89        /* first 2 pages is data that will be switched my mmu switch */
90data_a:
91        .word MAGIC1
92testval:
93        .word MAGIC2
94        .globl pte2_a
95/*
96 * one PD with a level 2 PTP: we invalidate an entry in the PTP and
97 * check that the VA is no longer accessible
98 */
99pte2_a:
100        .align 12
101        .word PTE2_V | PTE2_C | PTE2_X
102        .word 0x0000 >> 12 /* check real value of data_a */
103        .org pte2_a + 4092
104        .word 0
105        .globl pte2_b
106        .globl pte1_a
107pte1_a:
108        .align 13
109        .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
110        .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
111        .org pte1_a + (BOOT_ADDRESS >> 21) * 4
112        .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
113        .org pte1_a + (TTY_BASE >> 21) * 4
114        .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
115        .org pte1_a + (EXIT_BASE >> 21) * 4
116        .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
117        .org pte1_a + 8192
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