1 | /* |
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2 | * cache inval test: check that VC_ICACHE_INVAL_PA does the job |
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3 | * on a cc_vcache, the cache invalidation/update should be done by hardware |
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4 | * and VC_ICACHE_INVAL_PA should not be needed. |
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5 | */ |
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6 | #include <registers.h> |
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7 | #include <misc.h> |
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8 | #include <vcache.h> |
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9 | |
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10 | #define TEST_ADDRESS 0x200000 |
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11 | |
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12 | .text |
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13 | .globl _start |
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14 | _start: |
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15 | .set noreorder |
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16 | la k0, TTY_BASE |
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17 | la k1, EXIT_BASE |
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18 | |
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19 | PRINT(startstr) |
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20 | |
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21 | /* reset cop0 status (keep BEV) */ |
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22 | lui a0, 0x0040; |
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23 | mtc0 a0, COP0_STATUS |
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24 | |
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25 | la a0, pte1_a |
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26 | srl a0, a0, 13 |
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27 | mtc2 a0, VC_PTPR |
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28 | nop |
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29 | |
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30 | li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE |
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31 | mtc2 a0, VC_TLB_EN |
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32 | |
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33 | PRINT(mmustr_a) |
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34 | #copy 'doload' to TEST_ADDRESS |
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35 | la a1, DMA_BASE |
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36 | la a0, doload |
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37 | sw a0, DMA_SRC(a1) |
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38 | la a0, TEST_ADDRESS |
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39 | sw a0, DMA_DST(a1) |
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40 | li a0, 8 |
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41 | sw a0, DMA_LEN(a1) /* start DMA */ |
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42 | loop1: |
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43 | lw a0, DMA_LEN(a1) |
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44 | bne a0, zero, loop1; |
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45 | nop |
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46 | sw zero, DMA_RESET(a1) |
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47 | |
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48 | la a0, TEST_ADDRESS |
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49 | jalr a0 |
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50 | nop |
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51 | PRINTX |
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52 | PUTCHAR('\n') |
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53 | #copy 'doload2' to TEST_ADDRESS |
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54 | la a1, DMA_BASE |
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55 | la a0, doload2 |
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56 | sw a0, DMA_SRC(a1) |
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57 | la a0, TEST_ADDRESS |
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58 | sw a0, DMA_DST(a1) |
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59 | li a0, 8 |
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60 | sw a0, DMA_LEN(a1) /* start DMA */ |
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61 | loop2: |
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62 | lw a0, DMA_LEN(a1) |
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63 | bne a0, zero, loop2; |
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64 | nop |
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65 | sw zero, DMA_RESET(a1) |
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66 | |
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67 | PRINT(mmustr_b) |
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68 | la a0, TEST_ADDRESS |
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69 | jalr a0 |
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70 | nop |
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71 | PRINTX |
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72 | PUTCHAR('\n') |
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73 | |
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74 | la a0, TEST_ADDRESS |
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75 | mtc2 a0, VC_DATA_LO |
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76 | mtc2 zero, VC_DATA_HI |
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77 | mtc2 zero, VC_ICACHE_INVAL_PA |
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78 | addi a0, a0, 4 |
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79 | mtc2 a0, VC_DATA_LO |
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80 | mtc2 zero, VC_DATA_HI |
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81 | mtc2 zero, VC_ICACHE_INVAL_PA |
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82 | nop |
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83 | |
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84 | PRINT(mmustr_c) |
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85 | la a0, TEST_ADDRESS |
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86 | jalr a0 |
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87 | nop |
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88 | PRINTX |
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89 | PUTCHAR('\n') |
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90 | /* we should get there */ |
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91 | EXIT(0) |
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92 | |
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93 | .globl doload |
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94 | doload: |
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95 | jr ra |
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96 | li a0, MAGIC1 |
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97 | /* we should not get there */ |
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98 | EXIT(1) |
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99 | nop |
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100 | |
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101 | .globl doload2 |
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102 | doload2: |
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103 | jr ra |
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104 | li a0, MAGIC2 |
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105 | /* we should not get there */ |
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106 | EXIT(2) |
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107 | nop |
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108 | |
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109 | .globl excep |
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110 | excep: |
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111 | .set noreorder |
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112 | PRINT(statusstr) |
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113 | mfc0 a0, COP0_STATUS |
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114 | PRINTX |
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115 | |
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116 | PRINT(causestr) |
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117 | mfc0 a0, COP0_CAUSE |
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118 | PRINTX |
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119 | |
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120 | PRINT(pcstr) |
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121 | mfc0 a0, COP0_EXPC |
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122 | PRINTX |
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123 | |
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124 | PRINT(badvastr) |
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125 | mfc0 a0, COP_0_BADVADDR |
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126 | PRINTX |
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127 | |
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128 | PUTCHAR('\n') |
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129 | /* we should not get there */ |
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130 | EXIT(3) |
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131 | |
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132 | .rodata: |
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133 | statusstr: .ascii "status \0" |
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134 | causestr: .ascii " cause \0" |
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135 | pcstr: .ascii " pc \0" |
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136 | badvastr: .ascii " badva \0" |
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137 | mmustr_a: .ascii "mmu started before DMA \0" |
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138 | mmustr_b: .ascii "mmu started after DMA \0" |
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139 | mmustr_c: .ascii "mmu started after FLUSH \0" |
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140 | startstr: .ascii "start\n\0" |
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141 | |
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142 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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143 | .globl evect |
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144 | evect: |
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145 | j excep |
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146 | nop |
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147 | |
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148 | .data |
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149 | .word MAGIC1 |
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150 | testval: |
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151 | .word MAGIC2 |
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152 | |
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153 | .globl pte1_a |
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154 | pte1_a: |
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155 | .align 13 |
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156 | .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ |
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157 | .org pte1_a + (TEST_ADDRESS >> 21) * 4 |
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158 | .word PTE1_V | PTE1_C | PTE1_X | (TEST_ADDRESS >> 21) /* map PA 0x200000 at VA 0x200000, read-only/exec */ |
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159 | .word 0x0 |
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160 | .org pte1_a + (BOOT_ADDRESS >> 21) * 4 |
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161 | .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ |
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162 | .org pte1_a + (TTY_BASE >> 21) * 4 |
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163 | .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ |
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164 | .org pte1_a + (EXIT_BASE >> 21) * 4 |
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165 | .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ |
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166 | .org pte1_a + (DMA_BASE >> 21) * 4 |
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167 | .word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */ |
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