Last change
on this file since 272 was
232,
checked in by alain, 12 years ago
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Introducing the elementary tests for a TSAR mono-cluster
mono-processor platform with MMU using the vci_cc_vcache_v4
such as the "tsarv4_mono_mmu".
(assemby level tests written by Manuel Bouyer)
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File size:
1.7 KB
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Line | |
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1 | /* |
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2 | * Check that we can take an interrupt from the xicu timer0 |
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3 | */ |
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4 | #include <registers.h> |
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5 | #include <misc.h> |
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6 | #include <xicu.h> |
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7 | |
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8 | .text |
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9 | .globl _start |
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10 | _start: |
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11 | .set noreorder |
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12 | la k0, TTY_BASE |
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13 | la k1, EXIT_BASE |
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14 | |
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15 | /* reset cause, make sure IV is off */ |
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16 | mtc0 zero, COP0_CAUSE |
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17 | |
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18 | PRINT(startstr) |
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19 | |
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20 | /* program xicu */ |
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21 | la t0, XICU_BASE |
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22 | /* clear pending interrupt */ |
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23 | lw a0, XICU_PTI_ACK(0)(t0) |
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24 | /* route PTI0 to irq 0 */ |
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25 | li a0, 1 << 0 |
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26 | sw a0, XICU_MSK_PTI_E(0)(t0) |
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27 | /* init s0 */ |
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28 | li s0, MAGIC2 |
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29 | /* |
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30 | * interrupt in 42 cycles. |
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31 | * Without cache this takes us to the delay slot of the jump. |
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32 | */ |
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33 | li a0, 42 |
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34 | sw a0, XICU_PTI_PER(0)(t0) |
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35 | /* clear pending interrupt */ |
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36 | lw a0, XICU_PTI_ACK(0)(t0) |
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37 | /* reset cop0 status (keep BEV), enable interrupt 0 */ |
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38 | lui a0, 0x0040; |
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39 | addiu a0, 0x0401; |
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40 | mtc0 a0, COP0_STATUS |
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41 | |
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42 | nop |
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43 | nop |
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44 | nop |
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45 | j end |
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46 | li s0, MAGIC1 |
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47 | nop |
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48 | /* we should not end there */ |
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49 | EXIT(1) |
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50 | |
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51 | end: |
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52 | PRINT(endstr) |
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53 | move a0, s0 |
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54 | PRINTX |
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55 | PUTCHAR('\n') |
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56 | EXIT(0) |
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57 | |
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58 | .globl excep |
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59 | excep: |
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60 | .set noreorder |
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61 | /* disable timer0 */ |
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62 | la t0, XICU_BASE |
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63 | sw zero, XICU_PTI_PER(0)(t0) |
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64 | PRINT(statusstr) |
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65 | mfc0 a0, COP0_STATUS |
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66 | PRINTX |
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67 | |
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68 | PRINT(causestr) |
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69 | mfc0 a0, COP0_CAUSE |
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70 | PRINTX |
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71 | |
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72 | PRINT(pcstr) |
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73 | mfc0 a0, COP0_EXPC |
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74 | PRINTX |
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75 | |
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76 | PRINT(badvastr) |
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77 | mfc0 a0, COP_0_BADVADDR |
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78 | PRINTX |
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79 | |
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80 | PRINT(xicustr) |
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81 | la t0, XICU_BASE |
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82 | lw a0, XICU_PRIO(0)(t0) |
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83 | PRINTX |
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84 | |
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85 | PUTCHAR('\n') |
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86 | /* clear interrupt */ |
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87 | mfc0 a0, COP0_CAUSE |
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88 | andi t0, a0, 0xff00 |
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89 | xor a0, a0, t0 |
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90 | mtc0 a0, COP0_CAUSE |
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91 | eret |
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92 | /* we should not end there */ |
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93 | EXIT(1) |
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94 | |
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95 | .rodata: |
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96 | statusstr: .ascii "status \0" |
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97 | causestr: .ascii " cause \0" |
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98 | pcstr: .ascii " pc \0" |
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99 | badvastr: .ascii " badva \0" |
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100 | xicustr: .ascii " xicu \0" |
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101 | startstr: .ascii "start\n\0" |
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102 | endstr: .ascii "end \0" |
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103 | |
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104 | .org EXCEP_ADDRESS - BOOT_ADDRESS |
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105 | .globl evect |
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106 | evect: |
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107 | j excep |
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108 | nop |
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109 | .data |
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110 | myvar: .word 0 |
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