[758] | 1 | #ifndef HARD_CONFIG_H |
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| 2 | #define HARD_CONFIG_H |
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| 3 | |
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| 4 | /* General platform parameters */ |
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| 5 | |
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| 6 | #define X_SIZE 1 |
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| 7 | #define Y_SIZE 1 |
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| 8 | #define X_WIDTH 4 |
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| 9 | #define Y_WIDTH 4 |
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[801] | 10 | #define P_WIDTH 1 |
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[758] | 11 | #define X_IO 0 |
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| 12 | #define Y_IO 0 |
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| 13 | #define NB_PROCS_MAX 2 |
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| 14 | #define IRQ_PER_PROCESSOR 4 |
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| 15 | #define RESET_ADDRESS 0xff000000 |
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| 16 | #define NB_TOTAL_PROCS 16 |
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| 17 | |
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| 18 | /* Peripherals */ |
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| 19 | |
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| 20 | #define NB_TTY_CHANNELS 1 |
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| 21 | #define NB_IOC_CHANNELS 1 |
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| 22 | #define NB_NIC_CHANNELS 0 |
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| 23 | #define NB_CMA_CHANNELS 0 |
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| 24 | #define NB_TIM_CHANNELS 0 |
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| 25 | #define NB_DMA_CHANNELS 0 |
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| 26 | |
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| 27 | #define USE_XCU 1 |
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| 28 | #define USE_IOB 0 |
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| 29 | #define USE_PIC 0 |
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| 30 | #define USE_FBF 1 |
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| 31 | |
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| 32 | #define USE_IOC_BDV 0 |
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[962] | 33 | #define USE_IOC_SDC 1 |
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[758] | 34 | #define USE_IOC_HBA 0 |
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[798] | 35 | #define USE_IOC_RDK 0 |
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[758] | 36 | |
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| 37 | #define FBUF_X_SIZE 640 |
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| 38 | #define FBUF_Y_SIZE 480 |
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| 39 | |
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| 40 | #define XCU_NB_INPUTS 16 |
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| 41 | |
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| 42 | /* base addresses and sizes for physical segments */ |
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| 43 | |
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| 44 | #define SEG_RAM_BASE 0x0 |
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| 45 | #define SEG_RAM_SIZE 0x08000000 /* 128 MB */ |
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| 46 | |
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[832] | 47 | #define SEG_CMA_BASE 0xffffffff |
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| 48 | #define SEG_CMA_SIZE 0x0 |
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[758] | 49 | |
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[832] | 50 | #define SEG_DMA_BASE 0xffffffff |
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| 51 | #define SEG_DMA_SIZE 0x0 |
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[758] | 52 | |
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[832] | 53 | #define SEG_FBF_BASE 0xf3000000 |
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[758] | 54 | #define SEG_FBF_SIZE 0x100000 |
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| 55 | |
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| 56 | #define SEG_ICU_BASE 0xffffffff |
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| 57 | #define SEG_ICU_SIZE 0x0 |
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| 58 | |
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[832] | 59 | #define SEG_IOB_BASE 0xffffffff |
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| 60 | #define SEG_IOB_SIZE 0x0 |
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[758] | 61 | |
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| 62 | #define SEG_IOC_BASE 0xf2000000 |
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| 63 | #define SEG_IOC_SIZE 0x1000 |
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| 64 | |
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| 65 | #define SEG_MMC_BASE 0xe0000000 |
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| 66 | #define SEG_MMC_SIZE 0x1000 |
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| 67 | |
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| 68 | #define SEG_MWR_BASE 0xffffffff |
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| 69 | #define SEG_MWR_SIZE 0x0 |
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| 70 | |
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| 71 | #define SEG_ROM_BASE 0xff000000 |
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[832] | 72 | #define SEG_ROM_SIZE 0x10000 |
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[758] | 73 | |
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| 74 | #define SEG_SIM_BASE 0xffffffff |
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| 75 | #define SEG_SIM_SIZE 0x0 |
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| 76 | |
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| 77 | #define SEG_NIC_BASE 0xffffffff |
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| 78 | #define SEG_NIC_SIZE 0x0 |
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| 79 | |
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| 80 | #define SEG_PIC_BASE 0xffffffff |
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| 81 | #define SEG_PIC_SIZE 0x0 |
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| 82 | |
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| 83 | #define SEG_TIM_BASE 0xffffffff |
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| 84 | #define SEG_TIM_SIZE 0x0 |
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| 85 | |
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| 86 | #define SEG_TTY_BASE 0xf4000000 |
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| 87 | #define SEG_TTY_SIZE 0x4000 |
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| 88 | |
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| 89 | #define SEG_XCU_BASE 0xf0000000 |
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| 90 | #define SEG_XCU_SIZE 0x1000 |
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| 91 | |
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| 92 | #define SEG_RDK_BASE 0xffffffff |
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| 93 | #define SEG_RDK_SIZE 0x0 |
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| 94 | |
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| 95 | #endif |
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