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Last change
on this file since 602 was
568,
checked in by cfuguet, 11 years ago
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Adding support for TSAR platforms using the vci_io_bridge component.
In this case (USE_IOB=1), when a block is read from the disk controller,
the buffer containing the read data must be invalidated in the Memory
Cache as the transfer is done between the disk controller and the RAM.
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File size:
461 bytes
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| Line | |
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| 1 | #define NB_PROCS 1 |
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| 2 | #define NB_CLUSTERS 1 |
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| 3 | |
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| 4 | #define IRQ_PER_PROC 1 |
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| 5 | |
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| 6 | #define USE_IOB 0 |
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| 7 | #define CACHE_COHERENCE 1 |
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| 8 | #define CACHE_LINE_SIZE 64//bytes |
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| 9 | |
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| 10 | #define BOOT_DEBUG 1 |
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| 11 | #define BOOT_DEBUG_IOC 0 |
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| 12 | |
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| 13 | #define IOC_BASE 0xFB000000 |
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| 14 | #define TTY_BASE 0xFC000000 |
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| 15 | #define ICU_BASE 0xFD000000 |
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| 16 | #define MCC_BASE 0xFFFFFFFF // not used |
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| 17 | |
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| 18 | /* Mandatory argument only for FPGA platforms */ |
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| 19 | |
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| 20 | #define SYSCLK_FREQ 25000000//Hz |
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