source: trunk/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts @ 292

Last change on this file since 292 was 292, checked in by cfuguet, 12 years ago

Changing directory structure of the TSAR boot loader.
A README.txt file has been included to explain the new structure
and the MAKEFILE parameters.

Erasing the heap segment for the boot elf loader. All the work space
is allocated in the stack.

The stack size is defined in the include/defs.h.

Important modification in the reset.S file. The non-boot
processors (processor id != 0) wait in a low comsumption energy
mode to be wake up by processor 0 using an IPI. Each processor
has a private mailbox in the local XICU. The value written in
the mailbox will be used as address to jump by the processors.

The waking up of non-boot processors is not done in this boot loader
so it must be done in the application loaded.

The boot_loader_elf function loads into memory an executable .elf file
which must be placed in the BOOT_LOADER_LBA block of the disk. This
constant can be defined in the include/defs.h file.

File size: 4.4 KB
Line 
1/dts-v1/;
2
3/ {
4    #address-cells = <0x1>;
5    #size-cells = <0x1>;
6
7    cpus {
8        #address-cells = <0x1>;
9        #size-cells = <0x0>;
10
11        Mips,32@0 {
12            device_type = "cpu";
13            icudev_type = "cpu:mips";
14            name = "Mips,32";
15            reg = <0x00000000>;
16        };
17
18        Mips,32@1 {
19            device_type = "cpu";
20            icudev_type = "cpu:mips";
21            name = "Mips,32";
22            reg = <0x00000001>;
23        };
24
25        Mips,32@2 {
26            device_type = "cpu";
27            icudev_type = "cpu:mips";
28            name = "Mips,32";
29            reg = <0x00000002>;
30        };
31
32        Mips,32@3 {
33            device_type = "cpu";
34            icudev_type = "cpu:mips";
35            name = "Mips,32";
36            reg = <0x00000003>;
37        };
38    };
39
40    memory@0x00000000 {
41        cached = <0x1>;
42        device_type = "memory";
43        reg = <0x00000000 0x08000000>;
44    };
45
46    memory@0xbfc00000 {
47        cached = <0x1>;
48        device_type = "rom";
49        reg = <0xbfc00000 0x00400000>;
50    };
51
52    tty@0xfc000000 {
53        device_type = "soclib:tty";
54        irq = <&{/xicu@0xfd000000} 0x0>;
55        reg = <0xfc000000 0x00000010>;
56        tty_count = <0x1>;
57    };
58    simhelper@0xf1000000 {
59        device_type = "soclib:simhelper";
60        reg = <0xf1000000 0x00000010>;
61    };
62
63    blockdevice@0xfb000000 {
64        device_type = "soclib:blockdevice";
65        irq = <&{/xicu@0xfd000000} 0x1>;
66        reg = <0xfb000000 0x00000020>;
67    };
68
69    fb@0xf0000000 {
70        device_type = "soclib:frame_buffer";
71        reg = <0xf0000000 0x400000>;
72        mode = <32>;
73        width = <640>;
74        height = <480>;
75    };
76
77    xicu@0xfd000000 {
78        device_type = "soclib:xicu:root";
79        input_lines = <0x2>;
80        ipis = <0x4>;
81        reg = <0xfd000000 0x00001000>;
82        timers = <0x4>;
83
84        out@0 {
85            device_type = "soclib:xicu:filter";
86            irq = <&{/cpus/Mips,32@0} 0x0>;
87            output_line = <0x0>;
88            parent = <&{/xicu@0xfd000000}>;
89        };
90
91        out@1 {
92            device_type = "soclib:xicu:filter";
93            irq = <&{/cpus/Mips,32@0} 0x1>;
94            output_line = <0x1>;
95            parent = <&{/xicu@0xfd000000}>;
96        };
97
98        out@2 {
99            device_type = "soclib:xicu:filter";
100            irq = <&{/cpus/Mips,32@0} 0x2>;
101            output_line = <0x2>;
102            parent = <&{/xicu@0xfd000000}>;
103        };
104
105        out@3 {
106            device_type = "soclib:xicu:filter";
107            irq = <&{/cpus/Mips,32@1} 0x0>;
108            output_line = <0x3>;
109            parent = <&{/xicu@0xfd000000}>;
110        };
111
112        out@4 {
113            device_type = "soclib:xicu:filter";
114            irq = <&{/cpus/Mips,32@1} 0x1>;
115            output_line = <0x4>;
116            parent = <&{/xicu@0xfd000000}>;
117        };
118
119        out@5 {
120            device_type = "soclib:xicu:filter";
121            irq = <&{/cpus/Mips,32@1} 0x2>;
122            output_line = <0x5>;
123            parent = <&{/xicu@0xfd000000}>;
124        };
125
126        out@6 {
127            device_type = "soclib:xicu:filter";
128            irq = <&{/cpus/Mips,32@2} 0x0>;
129            output_line = <0x6>;
130            parent = <&{/xicu@0xfd000000}>;
131        };
132
133        out@7 {
134            device_type = "soclib:xicu:filter";
135            irq = <&{/cpus/Mips,32@2} 0x1>;
136            output_line = <0x7>;
137            parent = <&{/xicu@0xfd000000}>;
138        };
139
140        out@8 {
141            device_type = "soclib:xicu:filter";
142            irq = <&{/cpus/Mips,32@2} 0x2>;
143            output_line = <0x8>;
144            parent = <&{/xicu@0xfd000000}>;
145        };
146
147        out@9 {
148            device_type = "soclib:xicu:filter";
149            irq = <&{/cpus/Mips,32@3} 0x0>;
150            output_line = <0x9>;
151            parent = <&{/xicu@0xfd000000}>;
152        };
153        out@10 {
154            device_type = "soclib:xicu:filter";
155            irq = <&{/cpus/Mips,32@3} 0x1>;
156            output_line = <0xa>;
157            parent = <&{/xicu@0xfd000000}>;
158        };
159
160        out@11 {
161            device_type = "soclib:xicu:filter";
162            irq = <&{/cpus/Mips,32@3} 0x2>;
163            output_line = <0xb>;
164            parent = <&{/xicu@0xfd000000}>;
165        };
166
167    };
168  topology {
169    #address-cells = <2>;
170    #size-cells = <0>;
171    cluster@0,0 {
172        reg = <0 0>;
173        devices = <&{/cpus/Mips,32@0} &{/cpus/Mips,32@1} &{/cpus/Mips,32@2} &{/cpus/Mips,32@3} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/simhelper@0xf1000000} &{/blockdevice@0xfb000000} &{/fb@0xf0000000} >;
174    };
175  };
176};
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