[758] | 1 | /** |
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| 2 | * \file reset_inval.c |
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| 3 | * \date December 14, 2014 |
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| 4 | * \author Cesar Fuguet |
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| 5 | */ |
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| 6 | |
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| 7 | #include <reset_inval.h> |
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| 8 | #include <io.h> |
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| 9 | #include <defs.h> |
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| 10 | |
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| 11 | #ifndef SEG_MMC_BASE |
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| 12 | # error "SEG_MMC_BASE constant must be defined in the hard_config.h file" |
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| 13 | #endif |
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| 14 | |
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| 15 | static int* const mcc_address = (int* const)SEG_MMC_BASE; |
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| 16 | |
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| 17 | enum memc_registers |
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| 18 | { |
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| 19 | MCC_LOCK = 0, |
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| 20 | MCC_ADDR_LO = 1, |
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| 21 | MCC_ADDR_HI = 2, |
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| 22 | MCC_LENGTH = 3, |
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| 23 | MCC_CMD = 4 |
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| 24 | }; |
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| 25 | |
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| 26 | enum memc_operations |
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| 27 | { |
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| 28 | MCC_CMD_NOP = 0, |
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| 29 | MCC_CMD_INVAL = 1, |
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| 30 | MCC_CMD_SYNC = 2 |
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| 31 | }; |
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| 32 | |
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| 33 | /** |
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| 34 | * \brief Invalidate all data cache lines corresponding to a memory buffer |
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| 35 | * (identified by an address and a size) in L2 cache. |
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| 36 | */ |
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| 37 | void reset_mcc_invalidate (void* const buffer, size_t size) |
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| 38 | { |
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| 39 | // get the hard lock assuring exclusive access to MEMC |
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| 40 | while (ioread32(&mcc_address[MCC_LOCK])); |
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| 41 | |
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| 42 | // write invalidate paremeters on the memory cache this preloader |
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| 43 | // use only the cluster 0 and then the HI bits are not used |
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| 44 | |
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| 45 | iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); |
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| 46 | iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); |
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| 47 | iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); |
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| 48 | iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); |
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| 49 | |
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| 50 | // release the lock protecting MEMC |
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| 51 | iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); |
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| 52 | } |
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| 53 | |
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| 54 | /** |
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| 55 | * \brief Invalidate all data cache lines corresponding to a memory buffer |
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| 56 | * (identified by an address and a size) in L1 cache and L2 cache. |
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| 57 | */ |
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| 58 | void reset_buf_invalidate (void* const buffer, size_t size, int inval_memc) |
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| 59 | { |
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| 60 | unsigned int i; |
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| 61 | |
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| 62 | /* |
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| 63 | * iterate on cache lines containing target buffer to invalidate them |
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| 64 | */ |
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| 65 | for (i = 0; i <= size; i += CACHE_LINE_SIZE) |
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| 66 | { |
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| 67 | asm volatile( |
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| 68 | " cache %0, %1" |
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| 69 | : /* no outputs */ |
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| 70 | : "i" (0x11), "R" (*((char*)buffer + i)) |
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| 71 | : "memory" |
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| 72 | ); |
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| 73 | } |
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| 74 | |
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| 75 | if (inval_memc) reset_mcc_invalidate(buffer, size); |
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| 76 | } |
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| 77 | |
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| 78 | /* |
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| 79 | * vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab |
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| 80 | */ |
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