source: trunk/softs/tsar_boot/drivers/reset_inval.c @ 847

Last change on this file since 847 was 758, checked in by cfuguet, 10 years ago

tsar_boot: improving configuration infrastructure

  • Using hard_config.h which respects the same sintax that the hard_config.h file of all TSAR platforms. This file can be then generated by the GIET-VM genmap tool or written manually.
  • All peripheral drivers have been moved to a drivers directory and they are compiled as a static library. This allows GCC to only include in the final .ELF the object files of used peripherals and not all of them.
  • Example hard_config.h and ldscripts have been introduced in the conf directory.
  • Improving comments in all files
File size: 2.0 KB
Line 
1/**
2 * \file   reset_inval.c
3 * \date   December 14, 2014
4 * \author Cesar Fuguet
5 */
6
7#include <reset_inval.h>
8#include <io.h>
9#include <defs.h>
10
11#ifndef SEG_MMC_BASE
12#   error "SEG_MMC_BASE constant must be defined in the hard_config.h file"
13#endif
14
15static int* const mcc_address = (int* const)SEG_MMC_BASE;
16
17enum memc_registers
18{
19    MCC_LOCK      = 0,
20    MCC_ADDR_LO   = 1,
21    MCC_ADDR_HI   = 2,
22    MCC_LENGTH    = 3,
23    MCC_CMD       = 4
24};
25
26enum memc_operations
27{
28    MCC_CMD_NOP   = 0,
29    MCC_CMD_INVAL = 1,
30    MCC_CMD_SYNC  = 2
31};
32
33/**
34 * \brief Invalidate all data cache lines corresponding to a memory buffer
35 *        (identified by an address and a size) in L2 cache.
36 */
37void reset_mcc_invalidate (void* const buffer, size_t size)
38{
39    // get the hard lock assuring exclusive access to MEMC
40    while (ioread32(&mcc_address[MCC_LOCK]));
41
42    // write invalidate paremeters on the memory cache this preloader
43    // use only the cluster 0 and then the HI bits are not used
44
45    iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer);
46    iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0);
47    iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size);
48    iowrite32(&mcc_address[MCC_CMD]    , (unsigned int) MCC_CMD_INVAL);
49
50    // release the lock protecting MEMC
51    iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0);
52}
53
54/**
55 * \brief Invalidate all data cache lines corresponding to a memory buffer
56 *        (identified by an address and a size) in L1 cache and L2 cache.
57 */
58void reset_buf_invalidate (void* const buffer, size_t size, int inval_memc)
59{
60    unsigned int i;
61
62    /*
63     * iterate on cache lines containing target buffer to invalidate them
64     */
65    for (i = 0; i <= size; i += CACHE_LINE_SIZE)
66    {
67        asm volatile(
68            " cache %0, %1"
69            : /* no outputs */
70            : "i" (0x11), "R" (*((char*)buffer + i))
71            : "memory"
72            );
73    }
74
75    if (inval_memc) reset_mcc_invalidate(buffer, size);
76}
77
78/*
79 * vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab
80 */
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