[992] | 1 | /** |
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| 2 | * \File : reset_ioc_sdc.c |
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| 3 | * \Date : 31/04/2015 |
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| 4 | * \Author : Alain Greiner |
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| 5 | * \Copyright (c) UPMC-LIP6 |
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| 6 | */ |
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| 7 | |
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| 8 | #include <reset_ioc_sdc.h> |
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| 9 | #include <reset_tty.h> |
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| 10 | #include <reset_inval.h> |
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| 11 | #include <reset_utils.h> |
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| 12 | #include <io.h> |
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| 13 | #include <defs.h> |
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| 14 | |
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| 15 | #define SDC_POLLING_TIMEOUT 1000000 // Number of retries when polling PXCI |
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| 16 | |
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| 17 | #define SDC_RSP_TIMEOUT 100 // Number of retries for a config RSP |
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| 18 | |
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| 19 | /////////////////////////////////////////////////////////////////////////////////// |
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| 20 | // AHCI related global variables |
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| 21 | /////////////////////////////////////////////////////////////////////////////////// |
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| 22 | |
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| 23 | // command descriptor (one single command) |
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| 24 | static ahci_cmd_desc_t ahci_cmd_desc __attribute__((aligned(64))); |
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| 25 | |
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| 26 | // command table (one single command) |
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| 27 | static ahci_cmd_table_t ahci_cmd_table __attribute__((aligned(64))); |
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| 28 | |
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| 29 | // IOC/AHCI device base address |
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| 30 | static int* const ioc_address = (int* const)SEG_IOC_BASE; |
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| 31 | |
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| 32 | /////////////////////////////////////////////////////////////////////////////////// |
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| 33 | // SD Card related global variables |
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| 34 | /////////////////////////////////////////////////////////////////////////////////// |
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| 35 | |
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| 36 | // SD card relative address |
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| 37 | unsigned int sdc_rca; |
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| 38 | |
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| 39 | // SD Card Hih Capacity Support when non zero |
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| 40 | unsigned int sdc_sdhc; |
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| 41 | |
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| 42 | /////////////////////////////////////////////////////////////////////////////// |
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| 43 | // This function sends a command to the SD card and returns the response. |
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| 44 | // - index : CMD index |
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| 45 | // - arg : CMD argument |
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| 46 | // - return Card response |
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| 47 | /////////////////////////////////////////////////////////////////////////////// |
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| 48 | static unsigned int reset_sdc_send_cmd ( unsigned int index, |
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| 49 | unsigned int arg ) |
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| 50 | { |
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| 51 | unsigned int sdc_rsp; |
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| 52 | register int iter = 0; |
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| 53 | |
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| 54 | // load argument |
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| 55 | iowrite32( &ioc_address[SDC_CMD_ARG] , arg ); |
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| 56 | |
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| 57 | // lauch command |
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| 58 | iowrite32( &ioc_address[SDC_CMD_ID] , index ); |
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| 59 | |
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| 60 | // get response |
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| 61 | do |
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| 62 | { |
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| 63 | sdc_rsp = ioread32( &ioc_address[SDC_RSP_STS] ); |
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| 64 | iter++; |
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| 65 | } |
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| 66 | while ( (sdc_rsp == 0xFFFFFFFF) && (iter < SDC_RSP_TIMEOUT) ); |
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| 67 | |
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| 68 | return sdc_rsp; |
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| 69 | } |
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| 70 | |
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| 71 | ///////////////////////////////////////////////////////////////////////////////// |
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| 72 | // Extern functions |
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| 73 | ///////////////////////////////////////////////////////////////////////////////// |
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| 74 | |
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| 75 | /////////////////////////////////////////////////////////////////////////////// |
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| 76 | // This function initialises both the SD Card and the AHCI registers and |
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| 77 | // memory structures used by the AHCI_SDC peripheral (one single command). |
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| 78 | /////////////////////////////////////////////////////////////////////////////// |
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| 79 | unsigned int reset_sdc_init() |
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| 80 | { |
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| 81 | //////////// SD Card initialisation ////////// |
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| 82 | |
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| 83 | unsigned int rsp; |
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| 84 | |
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| 85 | // define the SD card clock period |
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| 86 | iowrite32( &ioc_address[SDC_PERIOD] , 2 ); |
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| 87 | |
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| 88 | // send CMD0 command (soft reset / no argument) |
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| 89 | rsp = reset_sdc_send_cmd( SDC_CMD0 , 0 ); |
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| 90 | if ( rsp == 0xFFFFFFFF ) |
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| 91 | { |
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| 92 | reset_puts("\n[RESET ERROR] in reset_sdc_init() : no aknowledge to CMD0\n"); |
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| 93 | return 1; |
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| 94 | } |
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| 95 | |
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| 96 | #if RESET_DEBUG |
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| 97 | reset_puts("\n[DEBUG SDC] reset_sdc_init() : SDC_CMD0 done\n"); |
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| 98 | #endif |
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| 99 | |
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| 100 | // send CMD8 command |
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| 101 | rsp = reset_sdc_send_cmd( SDC_CMD8 , SDC_CMD8_ARGUMENT ); |
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| 102 | if ( rsp == 0xFFFFFFFF ) |
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| 103 | { |
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| 104 | reset_puts("\n[RESET ERROR] in reset_sdc_init() : no response to CMD8\n"); |
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| 105 | return 1; |
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| 106 | } |
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| 107 | else if ( rsp != SDC_CMD8_ARGUMENT ) |
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| 108 | { |
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| 109 | reset_puts("\n[RESET ERROR] in reset_sdc_init() : bad response to CMD8\n"); |
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| 110 | return 1; |
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| 111 | } |
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| 112 | |
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| 113 | #if RESET_DEBUG |
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| 114 | reset_puts("\n[DEBUG SDC] reset_sdc_init() : SDC_CMD8 done\n"); |
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| 115 | #endif |
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| 116 | |
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| 117 | // send CMD41 command to get SDHC |
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| 118 | rsp = reset_sdc_send_cmd( SDC_CMD41 , SDC_CMD41_ARGUMENT ); |
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| 119 | if ( rsp == 0xFFFFFFFF ) |
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| 120 | { |
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| 121 | reset_puts("\n[RESET ERROR] in reset_sdc_init() : no response to CMD41\n"); |
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| 122 | return 1; |
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| 123 | } |
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| 124 | sdc_sdhc = ( (rsp & SDC_CMD41_RSP_CCS) != 0 ); |
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| 125 | |
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| 126 | #if RESET_DEBUG |
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| 127 | reset_puts("\n[DEBUG SDC] reset_sdc_init() : SDC_CMD41 done / sdhc = "); |
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| 128 | reset_putd( sdc_sdhc ); |
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| 129 | reset_puts("\n"); |
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| 130 | #endif |
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| 131 | |
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| 132 | // send CMD3 to get RCA |
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| 133 | rsp = reset_sdc_send_cmd( SDC_CMD3 , 0 ); |
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| 134 | if ( rsp == 0xFFFFFFFF ) |
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| 135 | { |
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| 136 | reset_puts("\n[RESET ERROR] in reset_sdc_init() : no response to CMD3\n"); |
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| 137 | return 1; |
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| 138 | } |
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| 139 | sdc_rca = rsp; |
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| 140 | |
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| 141 | #if RESET_DEBUG |
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| 142 | reset_puts("\n[DEBUG SDC] reset_sdc_init() : SDC_CMD3 done / rca = "); |
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| 143 | reset_putd( sdc_rca ); |
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| 144 | reset_puts("\n"); |
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| 145 | #endif |
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| 146 | |
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| 147 | // send CMD7 |
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| 148 | rsp = reset_sdc_send_cmd( SDC_CMD7 , sdc_rca ); |
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| 149 | if ( rsp == 0xFFFFFFFF ) |
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| 150 | { |
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| 151 | reset_puts("\n[RESET ERROR] in reset_sdc_init() : no response to CMD7\n"); |
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| 152 | return 1; |
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| 153 | } |
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| 154 | |
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| 155 | #if RESET_DEBUG |
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| 156 | reset_puts("\n[DEBUG SDC] reset_sdc_init() : SDC_CMD7 done\n"); |
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| 157 | #endif |
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| 158 | |
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| 159 | //////////// AHCI interface initialisation /////// |
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| 160 | |
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| 161 | // initialise the command descriptor |
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| 162 | ahci_cmd_desc.ctba = (unsigned int)&ahci_cmd_table; |
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| 163 | ahci_cmd_desc.ctbau = 0; |
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| 164 | |
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| 165 | #if USE_IOB |
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| 166 | // update external memory for the commande descriptor |
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| 167 | reset_L2_sync( &ahci_cmd_desc , sizeof( ahci_cmd_desc_t ) ); |
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| 168 | #endif |
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| 169 | |
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| 170 | // initialise AHCI registers |
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| 171 | iowrite32( &ioc_address[AHCI_PXCLB] , (unsigned int)&ahci_cmd_desc ); |
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| 172 | iowrite32( &ioc_address[AHCI_PXCLBU] , 0 ); |
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| 173 | iowrite32( &ioc_address[AHCI_PXIE] , 0 ); |
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| 174 | iowrite32( &ioc_address[AHCI_PXIS] , 0 ); |
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| 175 | iowrite32( &ioc_address[AHCI_PXCI] , 0 ); |
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| 176 | iowrite32( &ioc_address[AHCI_PXCMD] , 1 ); |
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| 177 | |
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| 178 | #if RESET_DEBUG |
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| 179 | reset_puts("\n[DEBUG SDC] reset_sdc_init() : AHCI init done\n"); |
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| 180 | #endif |
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| 181 | |
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| 182 | return 0; |
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| 183 | |
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| 184 | } // end reset_sdc_init() |
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| 185 | |
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| 186 | |
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| 187 | /////////////////////////////////////////////////////////////////////////////// |
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| 188 | // This function register one command in both the command descriptor |
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| 189 | // and the command data, and updates the HBA_PXCI register. |
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| 190 | // The addresses are supposed to be identity mapping (vaddr == paddr). |
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| 191 | // return 0 if success, -1 if error |
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| 192 | /////////////////////////////////////////////////////////////////////////////// |
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| 193 | unsigned int reset_sdc_read( unsigned int lba, |
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| 194 | void* buffer, |
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| 195 | unsigned int count ) |
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| 196 | { |
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| 197 | unsigned int pxci; // AHCI_PXCI register value |
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| 198 | unsigned int pxis; // AHCI_PXIS register value |
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| 199 | |
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| 200 | #if RESET_DEBUG |
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| 201 | reset_puts("\n[DEBUG SDC] reset_sdc_read() : buffer = "); |
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| 202 | reset_putx( (unsigned int)buffer ); |
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| 203 | reset_puts(" / nblocks = "); |
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| 204 | reset_putd( count ); |
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| 205 | reset_puts(" / lba = "); |
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| 206 | reset_putd( lba ); |
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| 207 | reset_puts("\n"); |
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| 208 | #endif |
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| 209 | |
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| 210 | // check buffer alignment |
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| 211 | if( (unsigned int)buffer & 0x3F ) |
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| 212 | { |
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| 213 | reset_puts("\n[SDC ERROR] in reset_sdc_read() : buffer not 64 bytes aligned\n"); |
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| 214 | return 1; |
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| 215 | } |
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| 216 | |
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| 217 | // set command header: lba value |
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| 218 | ahci_cmd_table.header.lba0 = (char)lba; |
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| 219 | ahci_cmd_table.header.lba1 = (char)(lba>>8); |
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| 220 | ahci_cmd_table.header.lba2 = (char)(lba>>16); |
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| 221 | ahci_cmd_table.header.lba3 = (char)(lba>>24); |
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| 222 | ahci_cmd_table.header.lba4 = 0; |
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| 223 | ahci_cmd_table.header.lba5 = 0; |
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| 224 | |
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| 225 | // set command buffer: address and size) |
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| 226 | ahci_cmd_table.buffer.dba = (unsigned int)(buffer); |
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| 227 | ahci_cmd_table.buffer.dbau = 0; |
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| 228 | ahci_cmd_table.buffer.dbc = count*512; |
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| 229 | |
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| 230 | // set command descriptor: one single buffer / read access |
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| 231 | ahci_cmd_desc.prdtl[0] = 1; |
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| 232 | ahci_cmd_desc.prdtl[1] = 0; |
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| 233 | ahci_cmd_desc.flag[0] = 0; // read |
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| 234 | |
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| 235 | #if RESET_DEBUG |
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| 236 | reset_puts("\n[DEBUG SDC] reset_sdc_read() : command registered\n"); |
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| 237 | #endif |
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| 238 | |
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| 239 | #if USE_IOB |
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| 240 | // update external memory for command table |
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| 241 | reset_L2_sync( &ahci_cmd_table , 32 ); |
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| 242 | |
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| 243 | // update external memory for command descriptor |
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| 244 | reset_L2_sync( &ahci_cmd_desc , 16 ); |
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| 245 | #endif |
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| 246 | |
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| 247 | // start transfer |
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| 248 | iowrite32( &ioc_address[AHCI_PXCI] , 1 ); |
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| 249 | |
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| 250 | #if RESET_DEBUG |
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| 251 | reset_puts("\n[DEBUG SDC] reset_sdc_read() : AHCI_SDC activated at cycle "); |
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| 252 | reset_putd( proctime() ); |
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| 253 | reset_puts("\n"); |
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| 254 | #endif |
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| 255 | |
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| 256 | #if (RESET_HARD_CC == 0) || USE_IOB |
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| 257 | // inval buffer in L1 cache |
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| 258 | reset_L1_inval( buffer , count * 512 ); |
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| 259 | #endif |
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| 260 | |
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| 261 | #if USE_IOB |
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| 262 | // inval buffer in L2 cache |
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| 263 | reset_L2_inval( buffer , count * 512 ); |
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| 264 | #endif |
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| 265 | |
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| 266 | // poll PXCI until command completed by AHCI |
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| 267 | unsigned int iter = SDC_POLLING_TIMEOUT; |
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| 268 | do |
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| 269 | { |
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| 270 | pxci = ioread32( &ioc_address[AHCI_PXCI] ); |
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| 271 | iter--; |
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| 272 | if (iter == 0 ) |
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| 273 | { |
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| 274 | reset_puts("\n[SDC ERROR] in reset_sdc_read() : polling PXCI timeout\n"); |
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| 275 | return 1; |
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| 276 | } |
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| 277 | } |
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| 278 | while( pxci ); |
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| 279 | |
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| 280 | // get PXIS register |
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| 281 | pxis = ioread32( &ioc_address[AHCI_PXIS] ); |
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| 282 | |
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| 283 | // reset PXIS register |
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| 284 | iowrite32( &ioc_address[AHCI_PXIS] , 0 ); |
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| 285 | |
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| 286 | // check error status |
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| 287 | if ( pxis & 0x40000000 ) |
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| 288 | { |
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| 289 | reset_puts("\n[RESET ERROR] in reset_sdc_read() : status error\n"); |
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| 290 | return 1; |
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| 291 | } |
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| 292 | |
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| 293 | return 0; |
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| 294 | |
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| 295 | } // end reset_sdc_read() |
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| 296 | |
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| 297 | // Local Variables: |
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| 298 | // tab-width: 4 |
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| 299 | // c-basic-offset: 4 |
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| 300 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 301 | // indent-tabs-mode: nil |
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| 302 | // End: |
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| 303 | // vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 |
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