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Last change
on this file since 785 was
759,
checked in by cfuguet, 10 years ago
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tsar_boot: preloader ldscript is automatically generated
- Stack for processor 0 is allocated at the end of the
cluster(0,0) ram segment:
SEG_RAM_BASE + SEG_RAM_SIZE - RESET_STACK_SIZE
- code base is equal to the SEG_ROM_BASE constant defined
in the hard_config.h file.
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File size:
730 bytes
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| Rev | Line | |
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| [759] | 1 | /** |
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| 2 | * \file : preloader.ld.in |
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| 3 | * \author : Cesar Fuguet |
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| 4 | * \date : July 24, 2014 |
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| 5 | * |
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| 6 | * \brief : preloader ldscript template |
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| 7 | * \note : must be compiled with gcc to generate an instance |
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| 8 | */ |
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| 9 | |
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| 10 | #include <defs.h> |
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| 11 | |
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| 12 | /* Definition of the base address for code segment */ |
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| 13 | |
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| 14 | seg_code_base = SEG_ROM_BASE; |
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| 15 | seg_data_base = SEG_RAM_BASE + SEG_RAM_SIZE - RESET_STACK_SIZE - 0x4000; |
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| 16 | |
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| 17 | /* Grouping sections into segments */ |
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| 18 | |
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| 19 | ENTRY(reset) |
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| 20 | |
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| 21 | SECTIONS |
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| 22 | { |
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| 23 | . = seg_code_base; |
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| 24 | .text : |
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| 25 | { |
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| 26 | *(.reset) |
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| 27 | *(.rodata) |
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| 28 | *(.rodata.*) |
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| 29 | . = ALIGN(0x4); |
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| 30 | dtb_addr = .; |
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| 31 | INCLUDE "build/platform.ld"; |
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| 32 | } |
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| 33 | |
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| 34 | . = seg_data_base; |
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| 35 | .bss ALIGN(0x4) (NOLOAD) : |
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| 36 | { |
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| 37 | *(.data) |
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| 38 | *(.bss) |
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| 39 | } |
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| 40 | } |
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