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reset.S @ 582

Last change on this file since 582 was 567, checked in by alain, 11 years ago
Introducing CP2 registers mnemonics in mips32_registers.h Supporting 40 bits physical addresses, multi-clusters TSAR architectures: XICUs are accessed using the physical address extension mechanism.
File size: 6.8 KB

Rev	Line
[292]	1	/**
	2	* \file : reset.S
	3	* \date : 01/12/2012
	4	* \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner
	5	*
	6	* This is a boot code for a generic multi-clusters / multi-processors
	7	* TSAR architecture (up to 256 clusters / up to 4 processors per cluster).
	8	* There is one XICU, one TTY, one DMA and one stack segment per cluster.
	9	* segment base adresses = base + cluster_segment_increment*cluster_id
	10	*
	11	* - Each processor initializes the Status Register (SR) to disable interrupts.
	12	* - Each processor initializes the Count Register.
	13	* - Each processor initialises its private XICU Write Triggered Interruption
	14	* mask register.
	15	* - Only processor 0 initializes the stack pointer ($29).
	16	* - Only processor 0 (boot processor) executes the boot_load_elf function to
	17	* load in memory the boot loader stored in the block BOOT_LOADER_LBA of
	18	* the disk.
	19	* - All non-boot processors wait in a low power consumption mode that the
	20	* processor 0 wakes them using the IPI (Inter Processor Interruption)
	21	* functionality of the XICU device.
	22	*/
	23
	24	#include <defs.h>
	25	#include <mips32_registers.h>
	26
	27	.section .boot,"ax",@progbits
	28
	29	.extern seg_stack_base
	30
[348]	31	.extern dtb_addr
[292]	32	.extern boot_putc
	33	.extern boot_getc
	34	.extern boot_ioc_read
	35	.extern boot_elf_loader
[425]	36	.extern memcpy
[349]	37	.extern boot_puts
	38	.extern boot_putx
	39	.extern boot_putd
	40	.extern boot_ioc_init
[502]	41	.extern versionstr
[292]	42
	43	.globl boot /* Make reset an external symbol */
	44	.ent boot
	45
	46	.align 2
	47	.set noreorder
	48
	49	boot:
	50	b _boot /* 0xbfc0000 */
	51	nop /* 0xbfc0004 */
	52
	53	/* Addresses of the functions provided by this pre-loader */
	54
	55	.word BOOT_VERSION /* 0xbfc0008 */
	56	.word dtb_addr /* 0xbfc000c */
[349]	57	.word boot_putc /* 0xbfc0010 */
	58	.word boot_getc /* 0xbfc0014 */
	59	.word boot_ioc_read /* 0xbfc0018 */
	60	.word boot_elf_loader /* 0xbfc001C */
[425]	61	.word memcpy /* 0xbfc0020 */
[349]	62	.word boot_puts /* 0xbfc0024 */
	63	.word boot_putx /* 0xbfc0028 */
	64	.word boot_putd /* 0xbfc002C */
[292]	65
	66	_boot:
	67	/* Disable interruptions, keep STATUSbev enabled */
	68
	69	li k0, (1 << 22)
	70	mtc0 k0, CP0_STATUS
	71
	72	/* Computes proc_id, local_id, cluster_id, and cluster_increment */
	73
	74	mfc0 k0, CP0_EBASE
	75	andi t0, k0, 0x3FF /* t0 <= proc_id (at most 1024 processors) */
	76
	77	move t3, t0
	78
	79	la k0, NB_PROCS /* k0 <= number of processors per cluster */
	80	divu t3, k0
	81	mfhi t1 /* t1 <= local_id = proc_id % NB_PROCS */
	82	mflo t2 /* t2 <= cluster_id = proc_id / NB_PROCS */
	83
	84	la k0, NB_CLUSTERS
[567]	85	sll k1, t2, 8 /* k1 <= 256cluster_id /
	86	div k1, k0 /* LO <= cluster_id * 256 / NB_CLUSTERS */
	87	mflo k1 /* k1 <= physical address extension (8 MSB) */
[292]	88
	89	/* Initialization of the count register in the coprocessor 0 */
	90
	91	mtc0 zero, CP0_COUNT
	92
	93	/**
	94	* Compute the output index for the Write Triggered Interruption mask.
	95	* Each processor enable the WTI for its irq output
[567]	96	* Each processor may have IRQ_PER_PROC private irq outputs from the XICU
	97	* In each cluster, the ICU base address depends on the cluster_id
[292]	98	*/
[302]	99
[567]	100	la t3, ICU_BASE
[302]	101	move t4, t1 /* t4 <= local_id */
	102	li t5, IRQ_PER_PROC /* t5 <= IRQ_PER_PROC */
	103	multu t4, t5
	104	mflo t6 /* t6 <= IRQ_PER_PROC * local_id */
	105	sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */
	106
[314]	107	li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */
[302]	108	or t4, t4, t5 /* t4 <= FUNC \| INDEX \| 00 */
	109	or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */
[292]	110
[567]	111	/* Compute and set WTI mask using the physical address extension */
[292]	112
	113	li t4, 1
	114	sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */
	115
[567]	116	mtc2 k1, CP2_PADDR_EXT /* set PADDR extension */
	117	sw t4, 0(t3) /* XICU[MSK_WTI][INDEX] <= t4 */
	118	mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */
	119
[292]	120	/**
	121	* We have:
	122	* t0: global id
	123	* t1: local id
	124	* t2: cluster id
	125	* t3: xicu base address
[567]	126	* k1: Paddr extension depending on cluster_id
[292]	127	*
	128	* Only processor 0 in cluster 0 executes the boot loader
	129	*/
	130
	131	bne zero, t0, _reset_wait
	132	nop
	133
	134	/* Initializes stack pointer */
	135
[554]	136	la sp, stk
[292]	137
[502]	138	la a0, versionstr
	139	la k0, boot_puts
	140	jalr k0
	141	nop
	142
[292]	143	#ifndef SOCLIB_IOC
	144
	145	/* Initialize the block device */
	146
	147	la k0, boot_ioc_init
	148	jalr k0
	149	nop
	150
	151	#endif
	152
	153	/**
[302]	154	* Jump to the boot elf loader routine
[292]	155	* Passing as argument the block number in which it must be
[302]	156	* the executable elf file to load
[292]	157	*/
	158
	159	la k0, boot_elf_loader
	160	li a0, BOOT_LOADER_LBA
	161	jalr k0
	162	nop
	163
	164	/**
	165	* We jump to the entry point address defined in the
	166	* ELF file. This address is returned by boot_elf_loader function.
	167	* All function arguments are 0
	168	*/
	169
	170	move a0, zero
	171	move a1, zero
	172	move a2, zero
	173	move a3, zero
	174	jr v0
	175	nop
	176
	177	/**
	178	* Wait in low power consumption mode until the application wakes us.
	179	* The application wakes up the non-boot CPUs using a IPI with a non-0
	180	* value in the mailbox. This non-0 value is the address to jump to.
	181	*/
	182
	183	_reset_wait:
	184	/**
	185	* We have:
	186	* t0: global id
	187	* t1: local id
	188	* t2: cluster id
	189	* t3: xicu base address
[567]	190	* k1: Paddr extension depending on cluster_id
[292]	191	*/
	192
	193	sll t4, t1, 2 /* t4 <= local_id * 4 */
	194	addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */
	195
	196	wait
	197
[567]	198	/* read the address to jump with a physical read */
	199
	200	mtc2 k1, CP2_PADDR_EXT /* set PADDR extension */
	201	lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */
	202	mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */
	203
[292]	204	jr k0
	205	nop
	206
	207	/* Exception entry point */
	208	.org 0x0380
	209	_excep:
	210	mfc0 a0, CP0_STATUS /* first arg is status */
	211	mfc0 a1, CP0_CAUSE /* second arg is cause */
	212	mfc0 a2, CP0_EPC /* third argc is epc */
	213	nop
	214	j handle_except
	215	nop
	216
	217	.end boot
	218
	219	.set reorder
[302]	220
[554]	221	.section .data
	222	.space BOOT_STACK_SIZE
	223	stk:
	224	.space 1
	225
[302]	226	/*
	227	* vim: tabstop=4 : shiftwidth=4 : expandtab
	228	*/

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