[586] | 1 | /* |
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[292] | 2 | * \file : reset.S |
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| 3 | * \date : 01/12/2012 |
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| 4 | * \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner |
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| 5 | * |
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[586] | 6 | * This is a generic reset code for a generic multi-clusters / multi-processors |
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| 7 | * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). |
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[292] | 8 | * |
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[586] | 9 | * There is one XICU, one TTY, one DMA, and one memory bank per cluster. |
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| 10 | * |
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| 11 | * This preloader uses a stack segment allocated in cluster 0, defined |
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[660] | 12 | * by the seg_reset_stack_base parameters in ldscript, of size 0x10000 (64k) |
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[586] | 13 | * - Processor 0 uses a larger stack: 64 Kbytes. |
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[704] | 14 | * - Other processors use a smaller stack: 256 bytes. |
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| 15 | * => the seg_stack_size cannot be smaller than 0x50000 bytes (320 Kytes). |
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| 16 | * (64K + 1024 * 256 = 320 Kbytes) |
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[586] | 17 | * Those stacks can be used by both the preloader and the boot-loader code. |
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| 18 | * |
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| 19 | * The replicated XICU is used to awake the sleeping processors: |
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[606] | 20 | * xicu_paddr_base = ICU_PADDR_BASE + (cluster_xy << 32) |
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[586] | 21 | * |
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| 22 | * It is intended to be used with various operating systems or nano kernels, |
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| 23 | * including NetBSD, ALMOS, and GIET_VM. |
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| 24 | * |
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| 25 | * - Each processor initializes its Status Register (SR) to disable interrupts. |
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| 26 | * - Each processor initializes its Count Register. |
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| 27 | * - Each processor initialises its private XICU WTI mask register. |
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| 28 | * - Each processor initializes its Stack Pointer. |
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| 29 | * - Only processor 0 executes the reset_load_elf function to load into memory |
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| 30 | * the system specific boot-loader stored on disk at BOOT_LOADER_LBA |
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| 31 | * - All other processors wait in a low power consumption mode that the |
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| 32 | * processor 0 wakes them using an IPI (Inter Processor Interruption) |
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[292] | 33 | */ |
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| 34 | |
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| 35 | #include <defs.h> |
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| 36 | #include <mips32_registers.h> |
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| 37 | |
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[606] | 38 | /* These define should be consistent with values defined in map.xml file */ |
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[292] | 39 | |
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[586] | 40 | .extern seg_reset_stack_base |
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[292] | 41 | |
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[586] | 42 | .section .reset,"ax",@progbits |
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| 43 | |
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[348] | 44 | .extern dtb_addr |
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[586] | 45 | .extern reset_putc |
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| 46 | .extern reset_getc |
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| 47 | .extern reset_ioc_read |
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| 48 | .extern reset_elf_loader |
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[425] | 49 | .extern memcpy |
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[586] | 50 | .extern reset_puts |
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| 51 | .extern reset_putx |
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| 52 | .extern reset_putd |
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| 53 | .extern reset_ioc_init |
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[502] | 54 | .extern versionstr |
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[292] | 55 | |
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[586] | 56 | .globl reset /* Makes reset an external symbol */ |
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| 57 | .ent reset |
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[292] | 58 | |
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| 59 | .align 2 |
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| 60 | .set noreorder |
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| 61 | |
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[586] | 62 | reset: |
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| 63 | b _reset /* 0xbfc0000 */ |
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[292] | 64 | nop /* 0xbfc0004 */ |
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| 65 | |
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[586] | 66 | /* Addresses of the functions provided by this reset code */ |
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[292] | 67 | |
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[634] | 68 | preloader_vector: |
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[586] | 69 | .word RESET_VERSION /* 0xbfc0008 */ |
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[292] | 70 | .word dtb_addr /* 0xbfc000c */ |
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[586] | 71 | .word reset_putc /* 0xbfc0010 */ |
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| 72 | .word reset_getc /* 0xbfc0014 */ |
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| 73 | .word reset_ioc_read /* 0xbfc0018 */ |
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| 74 | .word reset_elf_loader /* 0xbfc001C */ |
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[425] | 75 | .word memcpy /* 0xbfc0020 */ |
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[586] | 76 | .word reset_puts /* 0xbfc0024 */ |
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| 77 | .word reset_putx /* 0xbfc0028 */ |
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| 78 | .word reset_putd /* 0xbfc002C */ |
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[292] | 79 | |
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[586] | 80 | _reset: |
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[292] | 81 | |
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[586] | 82 | /* All processors Disable interruptions, keep STATUSbev enabled */ |
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| 83 | |
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[292] | 84 | li k0, (1 << 22) |
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| 85 | mtc0 k0, CP0_STATUS |
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| 86 | |
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[606] | 87 | /* All processors compute proc_id, lpid, cluster_xy */ |
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[292] | 88 | |
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| 89 | mfc0 k0, CP0_EBASE |
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| 90 | andi t0, k0, 0x3FF /* t0 <= proc_id (at most 1024 processors) */ |
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| 91 | |
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| 92 | move t3, t0 |
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| 93 | |
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| 94 | la k0, NB_PROCS /* k0 <= number of processors per cluster */ |
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| 95 | divu t3, k0 |
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[606] | 96 | mfhi t1 /* t1 <= lpid = proc_id % NB_PROCS */ |
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| 97 | mflo t2 /* t2 <= cluster_xy = proc_id / NB_PROCS */ |
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[292] | 98 | |
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[586] | 99 | /* All processors initialise the count register in CP0 */ |
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[292] | 100 | |
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| 101 | mtc0 zero, CP0_COUNT |
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| 102 | |
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[586] | 103 | /* |
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| 104 | * All processors enable the WTI for XICU |
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| 105 | * Each processor may have IRQ_PER_PROC irq outputs from the XICU |
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[606] | 106 | * In each cluster, the XICU base address depends on the cluster_xy |
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[292] | 107 | */ |
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[302] | 108 | |
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[586] | 109 | la t3, ICU_PADDR_BASE /* t3 <= ICU base address */ |
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| 110 | move t4, t1 /* t4 <= local_id */ |
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| 111 | li t5, IRQ_PER_PROC /* t5 <= IRQ_PER_PROC */ |
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[302] | 112 | multu t4, t5 |
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[586] | 113 | mflo t6 /* t6 <= IRQ_PER_PROC * local_id */ |
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| 114 | sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */ |
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[302] | 115 | |
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[586] | 116 | li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */ |
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| 117 | or t4, t4, t5 /* t4 <= FUNC | INDEX | 00 */ |
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| 118 | or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */ |
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[292] | 119 | |
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[586] | 120 | /* All processors set WTI mask using the physical address extension */ |
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[292] | 121 | |
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| 122 | li t4, 1 |
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[586] | 123 | sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */ |
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[292] | 124 | |
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[606] | 125 | mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */ |
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[586] | 126 | sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */ |
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| 127 | mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */ |
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[567] | 128 | |
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[586] | 129 | /* All processors initializes stack pointer, depending on proc_id */ |
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| 130 | |
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| 131 | la k0, seg_reset_stack_base |
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[660] | 132 | li k1, 0x10000 /* k1 <= P0 stack size == 64 Kbytes */ |
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[586] | 133 | addu sp, k0, k1 /* P0 stack from base to (base + 64K) */ |
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| 134 | |
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| 135 | li k1, 0x200 /* k1 <= Pi stack size == 512 bytes */ |
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| 136 | multu k1, t0 |
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| 137 | mflo k0 /* k0 <= 256 * proc_id */ |
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| 138 | addu sp, sp, k1 |
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| 139 | addu sp, sp, k0 /* Pi stacks from base + 64K + proc_id*256 */ |
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| 140 | |
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| 141 | /* |
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| 142 | * Only processor 0 in cluster 0 loads and executes the boot-loader |
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[292] | 143 | * We have: |
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[586] | 144 | * t0: global proc_id |
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| 145 | * t1: local proc_id |
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[606] | 146 | * t2: cluster_xy |
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[586] | 147 | * t3: xicu physical base address in cluster 0 |
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[292] | 148 | */ |
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| 149 | |
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| 150 | bne zero, t0, _reset_wait |
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| 151 | nop |
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| 152 | |
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[586] | 153 | /* Processor 0 displays version for this reset code */ |
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[292] | 154 | |
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[587] | 155 | la a0, versionstr |
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| 156 | la k0, reset_puts |
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| 157 | jalr k0 |
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| 158 | nop |
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[292] | 159 | |
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[502] | 160 | |
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[653] | 161 | #if USE_SPI |
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[292] | 162 | |
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[653] | 163 | /* Processor 0 Initialize the SPI controller */ |
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[292] | 164 | |
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[586] | 165 | la k0, reset_ioc_init |
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[292] | 166 | jalr k0 |
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| 167 | nop |
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| 168 | |
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| 169 | #endif |
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| 170 | |
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[586] | 171 | /* |
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| 172 | * Processor 0 jumps to the reset_elf_loader routine |
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| 173 | * Passing as argument the block number in which is loaded the .elf file |
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[292] | 174 | */ |
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| 175 | |
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[586] | 176 | la k0, reset_elf_loader |
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[292] | 177 | li a0, BOOT_LOADER_LBA |
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| 178 | jalr k0 |
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| 179 | nop |
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| 180 | |
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[586] | 181 | /* |
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| 182 | * Processor O jumps to the entry address defined in the .elf file, |
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| 183 | * and returned by reset_elf_loader function. |
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[634] | 184 | * First argument is pointer to the preloader function vectors |
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| 185 | * other function arguments are 0 |
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[292] | 186 | */ |
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| 187 | |
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[634] | 188 | la a0, preloader_vector |
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[292] | 189 | move a1, zero |
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| 190 | move a2, zero |
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| 191 | move a3, zero |
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| 192 | jr v0 |
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| 193 | nop |
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| 194 | |
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[586] | 195 | /* |
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| 196 | * All processor (but processor 0) wait in low power mode |
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| 197 | * until processor 0 wakes them using an IPI. |
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[292] | 198 | * We have: |
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| 199 | * t0: global id |
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| 200 | * t1: local id |
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| 201 | * t2: cluster id |
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[586] | 202 | * t3: xicu physical base address in cluster 0 |
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[292] | 203 | */ |
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| 204 | |
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[586] | 205 | _reset_wait: |
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[292] | 206 | |
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[586] | 207 | sll t4, t1, 2 /* t4 <= local_id * 4 */ |
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| 208 | addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */ |
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| 209 | |
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[292] | 210 | wait |
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| 211 | |
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[586] | 212 | /* |
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| 213 | * All other processors, when exiting wait mode, |
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| 214 | * read from XICU the address to jump. |
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| 215 | * This address is the boot-loader entry address that has been |
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| 216 | * written in the mailbox by the IPI sent by processor 0 |
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| 217 | */ |
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[567] | 218 | |
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[606] | 219 | mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */ |
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[567] | 220 | lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */ |
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| 221 | mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */ |
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| 222 | |
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[292] | 223 | jr k0 |
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| 224 | nop |
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| 225 | |
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| 226 | /* Exception entry point */ |
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[586] | 227 | |
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[292] | 228 | .org 0x0380 |
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| 229 | _excep: |
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[586] | 230 | mfc0 a0, CP0_STATUS /* first arg is status */ |
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| 231 | mfc0 a1, CP0_CAUSE /* second arg is cause */ |
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| 232 | mfc0 a2, CP0_EPC /* third argc is epc */ |
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[694] | 233 | mfc2 a3, CP2_DBVAR /* fourth argc is dbvar */ |
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[292] | 234 | nop |
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| 235 | j handle_except |
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| 236 | nop |
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| 237 | |
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[586] | 238 | .end reset |
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[292] | 239 | |
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| 240 | .set reorder |
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[302] | 241 | |
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| 242 | /* |
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| 243 | * vim: tabstop=4 : shiftwidth=4 : expandtab |
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| 244 | */ |
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