source: trunk/softs/tsar_boot/src/reset.S @ 991

Last change on this file since 991 was 949, checked in by cfuguet, 10 years ago

preloader: when loading LINUX, copy the DTB in low memory addresses

File size: 7.3 KB
RevLine 
[586]1/*
[292]2 * \file  : reset.S
3 * \date  : 01/12/2012
4 * \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner
5 *
[586]6 * This is a generic reset code for a generic multi-clusters / multi-processors
[755]7 * TSAR architecture (up to 256 clusters / up to 4 processors per cluster).
[292]8 *
[586]9 * There is one XICU, one TTY, one DMA, and one memory bank per cluster.
10 *
[755]11 * This preloader uses a stack segment allocated in cluster 0 for processor 0.
12 * The stack allocation is not performed for other processors as they do not
13 * need it during the preloader execution. Therefore, this allocation should be
14 * done by the loaded Operating System.
15 *
[586]16 * The replicated XICU is used to awake the sleeping processors:
[606]17 *      xicu_paddr_base = ICU_PADDR_BASE + (cluster_xy << 32)
[586]18 *
19 * It is intended to be used with various operating systems or nano kernels,
[755]20 * including NetBSD, Linux, ALMOS, and GIET_VM.
[586]21 *
22 * - Each processor initializes its Status Register (SR) to disable interrupts.
23 * - Each processor initializes its Count Register.
24 * - Each processor initialises its private XICU WTI mask register.
[755]25 * - Only processor 0 executes the reset_load_elf function to load into memory
[758]26 *   the system specific boot-loader stored on disk at RESET_LOADER_LBA
[586]27 * - All other processors wait in a low power consumption mode that the
28 *   processor 0 wakes them using an IPI (Inter Processor Interruption)
[292]29 */
30
31    #include <defs.h>
32    #include <mips32_registers.h>
33
[606]34    /* These define should be consistent with values defined in map.xml file  */
[292]35
[586]36    .section .reset,"ax",@progbits
37
38    .extern reset_putc
39    .extern reset_getc
40    .extern reset_ioc_read
41    .extern reset_elf_loader
[425]42    .extern memcpy
[586]43    .extern reset_puts
44    .extern reset_putx
45    .extern reset_putd
46    .extern reset_ioc_init
[502]47    .extern versionstr
[949]48    .extern dtb_start
49    .extern dtb_addr
[292]50
[586]51    .globl  reset                    /* Makes reset an external symbol */
52    .ent    reset
[292]53
54    .align  2
55    .set noreorder
56
[586]57reset:
[755]58    b       _reset                   /* 0xbfc0000 */
59    nop                              /* 0xbfc0004 */
[292]60
[586]61    /*  Addresses of the functions provided by this reset code */
[292]62
[634]63preloader_vector:
[755]64    .word   RESET_VERSION            /* 0xbfc0008 */
[949]65    .word   dtb_start                /* 0xbfc000c */
[755]66    .word   reset_putc               /* 0xbfc0010 */
67    .word   reset_getc               /* 0xbfc0014 */
68    .word   reset_ioc_read           /* 0xbfc0018 */
69    .word   reset_elf_loader         /* 0xbfc001C */
70    .word   memcpy                   /* 0xbfc0020 */
71    .word   reset_puts               /* 0xbfc0024 */
72    .word   reset_putx               /* 0xbfc0028 */
73    .word   reset_putd               /* 0xbfc002C */
[292]74
[586]75_reset:
[292]76
[586]77    /* All processors Disable interruptions, keep STATUSbev enabled */
78
[292]79    li      k0,     (1 << 22)
80    mtc0    k0,     CP0_STATUS
81
[801]82    /*
83     * All processors compute gpid, lpid, cluster_xy
[833]84     * gpid = ebase[11:0] = X_WIDTH : Y_WIDTH : P_WIDTH
[801]85     *                        x         y       lpid
86     * X, Y and LPID fields are left-aligned
87     */
[292]88
89    mfc0    k0,     CP0_EBASE
[833]90    andi    t0,     k0,     0xFFF            /* t0 <= gpid (<= 4096 procs)  */
[801]91    andi    t1,     t0,     ((1<<P_WIDTH)-1) /* t1 <= lpid                  */
92    srl     t2,     t0,     P_WIDTH          /* t2 <= cluster_xy            */
[292]93
[586]94    /* All processors initialise the count register in CP0 */
[292]95
96    mtc0    zero,   CP0_COUNT
97
[586]98    /*
[755]99     * All processors enable the WTI for XICU
[586]100     * Each processor may have IRQ_PER_PROC irq outputs from the XICU
[755]101     * In each cluster, the XICU base address depends on the cluster_xy
[292]102     */
[302]103
[758]104    la      t3,     SEG_XCU_BASE      /* t3 <= ICU base address             */
105    move    t4,     t1                /* t4 <= local_id                     */
106    li      t5,     IRQ_PER_PROCESSOR /* t5 <= IRQ_PER_PROCESSOR            */
[755]107    multu   t4,     t5
108    mflo    t6                       /* t6 <= IRQ_PER_PROC * local_id       */
109    sll     t4,     t6,     2        /* t4 <= OUT_INDEX = t6 * 4            */
[302]110
[755]111    li      t5,     (0xC << 7)       /* t5 <= FUNC      = XICU_MSK_WTI      */
112    or      t4,     t4,     t5       /* t4 <= FUNC | INDEX | 00             */
113    or      t5,     t3,     t4       /* t5 <= &XICU[MSK_WTI][OUT_INDEX]     */
[292]114
[755]115    /* All processors set WTI mask using the physical address extension */
116
[292]117    li      t4,     1
[755]118    sllv    t4,     t4,     t1       /* Set XICU[MSK_WTI][INDEX][local_id]  */
[292]119
[755]120    mtc2    t2,     CP2_PADDR_EXT    /* set PADDR extension                 */
121    sw      t4,     0(t5)            /* XICU[MSK_WTI][INDEX] <= t4          */
122    mtc2    zero,   CP2_PADDR_EXT    /* reset PADDR extension               */
[567]123
[586]124    /*
[755]125     * Only processor 0 in cluster 0 loads and executes the boot-loader
[292]126     * We have:
[755]127     * t0: global pid
128     * t1: local pid
[606]129     * t2: cluster_xy
[586]130     * t3: xicu physical base address in cluster 0
[292]131     */
132
133    bne     zero,   t0,     _reset_wait
134    nop
135
[755]136    /* Processor 0 initializes stack pointer */
137
138    la      k0,     _stack
139    li      k1,     RESET_STACK_SIZE /* k1 <= P0 stack size                 */
140    addu    sp,     k0,     k1       /* P0 stack from base to (base + size) */
141
[586]142    /* Processor 0 displays version for this reset code */
[292]143
[587]144    la      a0,     versionstr
[758]145    jal     reset_puts
[587]146    nop
[292]147
[758]148    /* Processor 0 initializes the block device */
[502]149
[758]150    jal     reset_ioc_init
[292]151    nop
152
[586]153    /*
[755]154     * Processor 0 jumps to the reset_elf_loader routine passing as argument
155     * the block number in which is loaded the .elf file
[292]156     */
157
[758]158    li      a0,     RESET_LOADER_LBA
159    jal     reset_elf_loader
[292]160    nop
161
[755]162    /*
163     * Processor O jumps to the entry address defined in the .elf file, and
164     * returned by reset_elf_loader function.
165     * First argument is pointer to the preloader function vectors other
166     * function arguments are 0
[292]167     */
168
[755]169    la      a0,     preloader_vector
[949]170    lw      a1,     dtb_addr
[292]171    move    a2,     zero
172    move    a3,     zero
173    jr      v0
174    nop
175
[586]176    /*
[755]177     * All processor (but processor 0) wait in low power mode until processor 0
178     * wakes them using an IPI.
[292]179     * We have:
180     * t0: global id
181     * t1: local id
182     * t2: cluster id
[586]183     * t3: xicu physical base address in cluster 0
[292]184     */
185
[586]186_reset_wait:
[292]187
[755]188    sll     t4,     t1,     2        /* t4 <= local_id * 4                  */
189    addu    t5,     t4,     t3       /* t5 <= &XICU[WTI_REG][local_id]      */
[586]190
[292]191    wait
192
[755]193    /*
194     * All other processors, when exiting wait mode, read from XICU the address
195     * to jump.
196     * This address is the boot-loader entry address that has been written in
197     * the mailbox by the IPI sent by processor 0
[586]198     */
[567]199
[755]200    mtc2    t2,     CP2_PADDR_EXT    /* set PADDR extension                 */
201    lw      k0,     0(t5)            /* k0 <= XICU[WTI_REG][local_id]       */
202    mtc2    zero,   CP2_PADDR_EXT    /* reset PADDR extension               */
[567]203
[292]204    jr      k0
205    nop
206
207/* Exception entry point */
[586]208
[292]209.org 0x0380
210_excep:
[755]211    mfc0    a0,     CP0_STATUS       /* first arg is status                 */
212    mfc0    a1,     CP0_CAUSE        /* second arg is cause                 */
213    mfc0    a2,     CP0_EPC          /* third argc is epc                   */
214    mfc2    a3,     CP2_DBVAR        /* fourth argc is dbvar                */
[292]215    nop
216    j       handle_except
217    nop
218
[586]219    .end reset
[292]220
221    .set reorder
[302]222
[755]223    .section .data
224
225_stack:
226
227    .space RESET_STACK_SIZE
228
[302]229/*
230 * vim: tabstop=4 : shiftwidth=4 : expandtab
231 */
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