1 | /* |
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2 | * \file : reset.S |
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3 | * \date : 01/12/2012 |
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4 | * \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner |
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5 | * |
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6 | * This is a generic reset code for a generic multi-clusters / multi-processors |
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7 | * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). |
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8 | * |
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9 | * There is one XICU, one TTY, one DMA, and one memory bank per cluster. |
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10 | * |
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11 | * This preloader uses a stack segment allocated in cluster 0 for processor 0. |
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12 | * The stack allocation is not performed for other processors as they do not |
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13 | * need it during the preloader execution. Therefore, this allocation should be |
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14 | * done by the loaded Operating System. |
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15 | * |
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16 | * The replicated XICU is used to awake the sleeping processors: |
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17 | * xicu_paddr_base = ICU_PADDR_BASE + (cluster_xy << 32) |
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18 | * |
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19 | * It is intended to be used with various operating systems or nano kernels, |
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20 | * including NetBSD, Linux, ALMOS, and GIET_VM. |
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21 | * |
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22 | * - Each processor initializes its Status Register (SR) to disable interrupts. |
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23 | * - Each processor initializes its Count Register. |
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24 | * - Each processor initialises its private XICU WTI mask register. |
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25 | * - Only processor 0 executes the reset_load_elf function to load into memory |
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26 | * the system specific boot-loader stored on disk at RESET_LOADER_LBA |
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27 | * - All other processors wait in a low power consumption mode that the |
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28 | * processor 0 wakes them using an IPI (Inter Processor Interruption) |
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29 | */ |
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30 | |
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31 | #include <defs.h> |
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32 | #include <mips32_registers.h> |
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33 | |
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34 | /* These define should be consistent with values defined in map.xml file */ |
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35 | |
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36 | .section .reset,"ax",@progbits |
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37 | |
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38 | .extern dtb_addr |
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39 | .extern reset_putc |
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40 | .extern reset_getc |
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41 | .extern reset_ioc_read |
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42 | .extern reset_elf_loader |
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43 | .extern memcpy |
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44 | .extern reset_puts |
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45 | .extern reset_putx |
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46 | .extern reset_putd |
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47 | .extern reset_ioc_init |
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48 | .extern versionstr |
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49 | |
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50 | .globl reset /* Makes reset an external symbol */ |
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51 | .ent reset |
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52 | |
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53 | .align 2 |
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54 | .set noreorder |
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55 | |
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56 | reset: |
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57 | b _reset /* 0xbfc0000 */ |
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58 | nop /* 0xbfc0004 */ |
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59 | |
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60 | /* Addresses of the functions provided by this reset code */ |
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61 | |
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62 | preloader_vector: |
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63 | .word RESET_VERSION /* 0xbfc0008 */ |
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64 | .word dtb_addr /* 0xbfc000c */ |
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65 | .word reset_putc /* 0xbfc0010 */ |
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66 | .word reset_getc /* 0xbfc0014 */ |
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67 | .word reset_ioc_read /* 0xbfc0018 */ |
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68 | .word reset_elf_loader /* 0xbfc001C */ |
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69 | .word memcpy /* 0xbfc0020 */ |
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70 | .word reset_puts /* 0xbfc0024 */ |
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71 | .word reset_putx /* 0xbfc0028 */ |
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72 | .word reset_putd /* 0xbfc002C */ |
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73 | |
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74 | _reset: |
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75 | |
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76 | /* All processors Disable interruptions, keep STATUSbev enabled */ |
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77 | |
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78 | li k0, (1 << 22) |
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79 | mtc0 k0, CP0_STATUS |
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80 | |
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81 | /* |
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82 | * All processors compute gpid, lpid, cluster_xy |
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83 | * gpid = ebase[9:0] = X_WIDTH : Y_WIDTH : P_WIDTH |
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84 | * x y lpid |
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85 | * X, Y and LPID fields are left-aligned |
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86 | */ |
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87 | |
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88 | mfc0 k0, CP0_EBASE |
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89 | andi t0, k0, 0x3FF /* t0 <= gpid (<= 1024 procs) */ |
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90 | andi t1, t0, ((1<<P_WIDTH)-1) /* t1 <= lpid */ |
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91 | srl t2, t0, P_WIDTH /* t2 <= cluster_xy */ |
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92 | |
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93 | /* All processors initialise the count register in CP0 */ |
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94 | |
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95 | mtc0 zero, CP0_COUNT |
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96 | |
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97 | /* |
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98 | * All processors enable the WTI for XICU |
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99 | * Each processor may have IRQ_PER_PROC irq outputs from the XICU |
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100 | * In each cluster, the XICU base address depends on the cluster_xy |
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101 | */ |
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102 | |
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103 | la t3, SEG_XCU_BASE /* t3 <= ICU base address */ |
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104 | move t4, t1 /* t4 <= local_id */ |
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105 | li t5, IRQ_PER_PROCESSOR /* t5 <= IRQ_PER_PROCESSOR */ |
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106 | multu t4, t5 |
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107 | mflo t6 /* t6 <= IRQ_PER_PROC * local_id */ |
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108 | sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */ |
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109 | |
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110 | li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */ |
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111 | or t4, t4, t5 /* t4 <= FUNC | INDEX | 00 */ |
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112 | or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */ |
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113 | |
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114 | /* All processors set WTI mask using the physical address extension */ |
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115 | |
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116 | li t4, 1 |
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117 | sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */ |
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118 | |
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119 | mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */ |
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120 | sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */ |
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121 | mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */ |
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122 | |
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123 | /* |
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124 | * Only processor 0 in cluster 0 loads and executes the boot-loader |
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125 | * We have: |
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126 | * t0: global pid |
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127 | * t1: local pid |
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128 | * t2: cluster_xy |
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129 | * t3: xicu physical base address in cluster 0 |
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130 | */ |
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131 | |
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132 | bne zero, t0, _reset_wait |
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133 | nop |
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134 | |
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135 | /* Processor 0 initializes stack pointer */ |
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136 | |
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137 | la k0, _stack |
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138 | li k1, RESET_STACK_SIZE /* k1 <= P0 stack size */ |
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139 | addu sp, k0, k1 /* P0 stack from base to (base + size) */ |
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140 | |
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141 | /* Processor 0 displays version for this reset code */ |
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142 | |
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143 | la a0, versionstr |
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144 | jal reset_puts |
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145 | nop |
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146 | |
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147 | /* Processor 0 initializes the block device */ |
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148 | |
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149 | jal reset_ioc_init |
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150 | nop |
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151 | |
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152 | /* |
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153 | * Processor 0 jumps to the reset_elf_loader routine passing as argument |
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154 | * the block number in which is loaded the .elf file |
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155 | */ |
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156 | |
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157 | li a0, RESET_LOADER_LBA |
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158 | jal reset_elf_loader |
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159 | nop |
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160 | |
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161 | /* |
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162 | * Processor O jumps to the entry address defined in the .elf file, and |
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163 | * returned by reset_elf_loader function. |
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164 | * First argument is pointer to the preloader function vectors other |
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165 | * function arguments are 0 |
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166 | */ |
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167 | |
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168 | la a0, preloader_vector |
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169 | move a1, zero |
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170 | move a2, zero |
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171 | move a3, zero |
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172 | jr v0 |
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173 | nop |
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174 | |
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175 | /* |
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176 | * All processor (but processor 0) wait in low power mode until processor 0 |
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177 | * wakes them using an IPI. |
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178 | * We have: |
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179 | * t0: global id |
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180 | * t1: local id |
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181 | * t2: cluster id |
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182 | * t3: xicu physical base address in cluster 0 |
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183 | */ |
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184 | |
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185 | _reset_wait: |
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186 | |
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187 | sll t4, t1, 2 /* t4 <= local_id * 4 */ |
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188 | addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */ |
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189 | |
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190 | wait |
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191 | |
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192 | /* |
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193 | * All other processors, when exiting wait mode, read from XICU the address |
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194 | * to jump. |
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195 | * This address is the boot-loader entry address that has been written in |
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196 | * the mailbox by the IPI sent by processor 0 |
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197 | */ |
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198 | |
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199 | mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */ |
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200 | lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */ |
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201 | mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */ |
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202 | |
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203 | jr k0 |
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204 | nop |
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205 | |
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206 | /* Exception entry point */ |
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207 | |
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208 | .org 0x0380 |
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209 | _excep: |
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210 | mfc0 a0, CP0_STATUS /* first arg is status */ |
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211 | mfc0 a1, CP0_CAUSE /* second arg is cause */ |
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212 | mfc0 a2, CP0_EPC /* third argc is epc */ |
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213 | mfc2 a3, CP2_DBVAR /* fourth argc is dbvar */ |
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214 | nop |
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215 | j handle_except |
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216 | nop |
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217 | |
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218 | .end reset |
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219 | |
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220 | .set reorder |
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221 | |
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222 | .section .data |
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223 | |
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224 | _stack: |
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225 | |
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226 | .space RESET_STACK_SIZE |
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227 | |
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228 | /* |
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229 | * vim: tabstop=4 : shiftwidth=4 : expandtab |
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230 | */ |
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