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reset.S

Last change on this file was 1049, checked in by alain, 8 years ago
Cosmetic change in the hard_config.h file : XCU -> ICU , TTY -> TXT
File size: 9.7 KB

Line
1	/*
2	* \file : reset.S
3	* \date : 01/12/2012
4	* \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner
5	*
6	* This is a generic reset code for a generic multi-clusters / multi-processors
7	* TSAR architecture (up to 256 clusters / up to 4 processors per cluster).
8	*
9	* There is one XICU, one TTY, one DMA, and one memory bank per cluster.
10	*
11	* This preloader uses a stack segment allocated in cluster 0 for processor 0.
12	* The stack allocation is not performed for other processors as they do not
13	* need it during the preloader execution. Therefore, this allocation should be
14	* done by the loaded Operating System.
15	*
16	* The replicated XICU is used to awake the sleeping processors:
17	* xicu_paddr_base = ICU_PADDR_BASE + (cluster_xy << 32)
18	*
19	* It is intended to be used with various operating systems or nano kernels,
20	* including NetBSD, Linux, ALMOS, and GIET_VM.
21	*
22	* - Each processor initializes its Status Register (SR) to disable interrupts.
23	* - Each processor initializes its Count Register.
24	* - Each processor initialises its private XICU WTI mask register.
25	* - Only processor 0 executes the reset_load_elf function to load into memory
26	* the system specific boot-loader stored on disk at RESET_LOADER_LBA
27	* - All other processors wait in a low power consumption mode that the
28	* processor 0 wakes them using an IPI (Inter Processor Interruption)
29	*/
30
31	#include <defs.h>
32	#include <mips32_registers.h>
33
34	/* These define should be consistent with values defined in map.xml file */
35
36	.section .reset,"ax",@progbits
37
38	.extern reset_putc
39	.extern reset_getc
40	.extern reset_ioc_read
41	.extern reset_elf_loader
42	.extern memcpy
43	.extern reset_puts
44	.extern reset_putx
45	.extern reset_putd
46	.extern reset_ioc_init
47	.extern versionstr
48	.extern dtb_start
49	.extern dtb_addr
50
51	.globl reset /* Makes reset an external symbol */
52	.ent reset
53
54	.align 2
55	.set noreorder
56
57	reset:
58	b _reset /* 0xbfc0000 */
59	nop /* 0xbfc0004 */
60
61	/* Addresses of the functions provided by this reset code */
62
63	preloader_vector:
64	.word RESET_VERSION /* 0xbfc0008 */
65	.word dtb_start /* 0xbfc000c */
66	.word reset_putc /* 0xbfc0010 */
67	.word reset_getc /* 0xbfc0014 */
68	.word reset_ioc_read /* 0xbfc0018 */
69	.word reset_elf_loader /* 0xbfc001C */
70	.word memcpy /* 0xbfc0020 */
71	.word reset_puts /* 0xbfc0024 */
72	.word reset_putx /* 0xbfc0028 */
73	.word reset_putd /* 0xbfc002C */
74
75	_reset:
76
77	/* All processors Disable interruptions, keep STATUSbev enabled */
78
79	li k0, (1 << 22)
80	mtc0 k0, CP0_STATUS
81
82	/*
83	* All processors compute gpid, lpid, cluster_xy
84	* gpid = ebase[11:0] = X_WIDTH : Y_WIDTH : P_WIDTH
85	* x y lpid
86	* X, Y and LPID fields are left-aligned
87	*/
88
89	mfc0 k0, CP0_EBASE
90	andi t0, k0, 0xFFF /* t0 <= gpid (<= 4096 procs) */
91	andi t1, t0, ((1<<P_WIDTH)-1) /* t1 <= lpid */
92	srl t2, t0, P_WIDTH /* t2 <= cluster_xy */
93
94	/* All processors initialize the count register in CP0 */
95
96	mtc0 zero, CP0_COUNT
97
98	#if USE_32BIT
99
100	/* VERSION 1 : 32 bits */
101
102	/*
103	* If the addresses are 32-bit wide, we need to compute the address
104	* if the XICU for each cluster
105	* All processors enable the WTI for XICU
106	* Each processor may have IRQ_PER_PROC irq outputs from the XICU
107	* In each cluster, the XICU base address depends on the cluster_xy
108	*/
109	la t3, SEG_ICU_BASE /* t3 <= ICU base address */
110	li t4, 1 /* t4 <= 1 */
111	sll t4, t4, X_WIDTH /* t4 <= 1 << X_WIDTH */
112	li t5, 1 /* t5 <= 1 */
113	sll t5, t5, Y_WIDTH /* t5 <= 1 << Y_WIDTH */
114	multu t4, t5 /* X_WIDTH * Y_WIDTH */
115	mflo t4 /* t4 <= X_WIDTH * Y_WIDTH */
116	lui t5, 0x8000 /* t5 <= 0x80000000 */
117	divu t5, t4 /* (Address increment per cluster) / 2*/
118	mflo t4 /* t4 <= Increment / 2 */
119	sll t4, t4, 1 /* t4 <= Address increment per clus. */
120	mult t4, t2 /* Cluster increment * Cluster num. */
121	mflo t4 /* Cluster base address */
122	addu t3, t3, t4 /* t3 <= XICU base address in clus. */
123
124	move t4, t1 /* t4 <= local_id */
125	li t5, IRQ_PER_PROCESSOR /* t5 <= IRQ_PER_PROCESSOR */
126	multu t4, t5
127	mflo t6 /* t6 <= IRQ_PER_PROC * local_id */
128	sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */
129
130	li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */
131	or t4, t4, t5 /* t4 <= FUNC \| INDEX \| 00 */
132	or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */
133
134	/* All processors set WTI mask */
135
136	li t4, 1
137	sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */
138	sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */
139
140	#else
141
142	/* VERSION 2 : 40 bits */
143
144	/*
145	* All processors enable the WTI for XICU
146	* Each processor may have IRQ_PER_PROC irq outputs from the XICU
147	* In each cluster, the XICU base address depends on the cluster_xy
148	*/
149	la t3, SEG_ICU_BASE /* t3 <= ICU base address */
150	move t4, t1 /* t4 <= local_id */
151	li t5, IRQ_PER_PROCESSOR /* t5 <= IRQ_PER_PROCESSOR */
152	multu t4, t5
153	mflo t6 /* t6 <= IRQ_PER_PROC * local_id */
154	sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */
155
156	li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */
157	or t4, t4, t5 /* t4 <= FUNC \| INDEX \| 00 */
158	or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */
159
160	/* All processors set WTI mask using the physical address extension */
161
162	li t4, 1
163	sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */
164
165	mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */
166	sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */
167	mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */
168
169	#endif
170
171	/*
172	* Only the bootstrap processor loads and executes the boot-loader
173	* We have:
174	* t0: global pid
175	* t1: local pid
176	* t2: cluster_xy
177	* t3: xicu physical base address in bootstrap cluster
178	*/
179
180	li t4, BS_PROC
181	bne t4, t0, _reset_wait
182	nop
183
184	/* Bootstrap Processor initializes stack pointer */
185
186	la k0, _stack
187	li k1, RESET_STACK_SIZE /* k1 <= P0 stack size */
188	addu sp, k0, k1 /* P0 stack from base to (base + size) */
189
190	/* Bootstrap Processor displays version for this reset code */
191
192	la a0, versionstr
193	jal reset_puts
194	nop
195
196	/* Bootstrap Processor initializes the block device */
197
198	jal reset_ioc_init
199	nop
200
201	/*
202	* Bootstrap Processor jumps to the reset_elf_loader routine passing as argument
203	* the block number in which is loaded the .elf file
204	*/
205
206	li a0, RESET_LOADER_LBA
207	jal reset_elf_loader
208	nop
209
210	/*
211	* Bootstrap Processor jumps to the entry address defined in the .elf file, and
212	* returned by reset_elf_loader function.
213	* First argument is pointer to the preloader function vectors other
214	* function arguments are 0
215	*/
216
217	la a0, preloader_vector
218	lw a1, dtb_addr
219	move a2, zero
220	move a3, zero
221	jr v0
222	nop
223
224	/*
225	* All processor (but processor 0) wait in low power mode until processor 0
226	* wakes them using an IPI.
227	* We have:
228	* t0: global id
229	* t1: local id
230	* t2: cluster id
231	* t3: xicu physical base address in cluster 0
232	*/
233
234	_reset_wait:
235
236	sll t4, t1, 2 /* t4 <= local_id * 4 */
237	addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */
238
239	wait
240
241	/*
242	* All other processors, when exiting wait mode, read from XICU the address
243	* to jump.
244	* This address is the boot-loader entry address that has been written in
245	* the mailbox by the IPI sent by processor 0
246	*/
247
248	mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */
249	lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */
250	mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */
251
252	jr k0
253	nop
254
255	/* Exception entry point */
256
257	.org 0x0380
258	_excep:
259	mfc0 a0, CP0_STATUS /* first arg is status */
260	mfc0 a1, CP0_CAUSE /* second arg is cause */
261	mfc0 a2, CP0_EPC /* third argc is epc */
262	mfc2 a3, CP2_DBVAR /* fourth argc is dbvar */
263	nop
264	j handle_except
265	nop
266
267	.end reset
268
269	.set reorder
270
271	.section .data
272
273	_stack:
274
275	.space RESET_STACK_SIZE
276
277	/*
278	* vim: tabstop=4 : shiftwidth=4 : expandtab
279	*/

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