Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
 <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
 <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
 <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
 <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
 <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
 <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>

Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
 <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
 <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
 <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>

Loading at 0xbfc00000 size 262144: .text .reginfo 
Loading at 0 size 33554432: .data 
****************** cycle 1 ************************************************
PROC proc
  <InsReq  invalid mode MODE_HYPER @ 0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 2 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 3 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 4 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc00000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 5 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 6 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 7 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 8 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 9 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 10 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 11 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 12 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 13 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 14 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 15 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 16 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 17 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 18 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840155 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 19 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 20 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 21 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 22 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 23 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 24 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 25 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 26 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 27 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 28 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
****************** cycle 29 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 30 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 31 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
  <InsRsp    valid no error ins 0x3c1ad020>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 32 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00004>
  <InsRsp    valid no error ins 0x3c1be000>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 33 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00008>
  <InsRsp    valid no error ins 0x3c1d003f>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 34 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0000c>
  <InsRsp    valid no error ins 0x37bdfff0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 35 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00010>
  <InsRsp    valid no error ins 0x3c04bfc0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 36 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00014>
  <InsRsp    valid no error ins 0x24840155>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 37 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00018>
  <InsRsp    valid no error ins 0xff000e4>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 38 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0001c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 39 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 40 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc00380  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 41 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 42 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 43 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 44 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 45 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 46 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 47 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 48 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 49 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 50 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 51 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 52 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 53 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 54 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 55 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 56 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 57 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 58 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 59 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 60 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 61 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 62 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 63 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 64 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
****************** cycle 65 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 66 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 67 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
  <InsRsp    valid no error ins 0x804021>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 68 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 69 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 70 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0x5 / valid = 0 / line = 0x000000005
****************** cycle 71 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc00140  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 72 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 73 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 74 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 75 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 76 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 77 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 78 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
****************** cycle 79 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
****************** cycle 80 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
****************** cycle 81 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x75616320 / way = 0 / set = 0x5 / word = 0
****************** cycle 82 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x206573 / way = 0 / set = 0x5 / word = 0x1
****************** cycle 83 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x20637020 / way = 0 / set = 0x5 / word = 0x2
****************** cycle 84 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x61622000 / way = 0 / set = 0x5 / word = 0x3
****************** cycle 85 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x20617664 / way = 0 / set = 0x5 / word = 0x4
****************** cycle 86 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x61747300 / way = 0 / set = 0x5 / word = 0x5
****************** cycle 87 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0xa7472 / way = 0 / set = 0x5 / word = 0x6
****************** cycle 88 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x6d727375 / way = 0 / set = 0x5 / word = 0x7
****************** cycle 89 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0xa65646f / way = 0 / set = 0x5 / word = 0x8
****************** cycle 90 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0x9
****************** cycle 91 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xa
****************** cycle 92 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xb
****************** cycle 93 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xc
****************** cycle 94 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xd
****************** cycle 95 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xe
****************** cycle 96 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xf
****************** cycle 97 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 98 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp   valid no error rdata 0x61747300>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 99 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 100 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 101 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 102 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
  <InsRsp    valid no error ins 0x25080001>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 103 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
  <InsRsp    valid no error ins 0xbf000e5>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 104 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000073  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 105 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 106 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 107 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
  <DataRsp   valid no error rdata 0x61747300>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 108 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 109 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 110 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 111 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
  <InsRsp    valid no error ins 0x25080001>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 112 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
  <InsRsp    valid no error ins 0xbf000e5>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 113 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 114 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 115 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 116 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
  <DataRsp   valid no error rdata 0x61747300>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 117 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 118 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 119 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 120 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
  <InsRsp    valid no error ins 0x25080001>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 121 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
  <InsRsp    valid no error ins 0xbf000e5>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 122 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 123 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 124 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 125 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 126 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
  <DataRsp   valid no error rdata 0xa7472>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000061  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 127 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 128 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 129 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 130 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
  <InsRsp    valid no error ins 0x25080001>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 131 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
  <InsRsp    valid no error ins 0xbf000e5>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 132 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 133 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 134 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 135 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 136 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 137 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp   valid no error rdata 0xa7472>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000072  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 138 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 139 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 140 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 141 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
  <InsRsp    valid no error ins 0x25080001>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 142 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
  <InsRsp    valid no error ins 0xbf000e5>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 143 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 144 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 145 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 146 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 147 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 148 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp   valid no error rdata 0xa7472>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 149 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 150 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 151 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 152 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
  <InsRsp    valid no error ins 0x25080001>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 153 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
  <InsRsp    valid no error ins 0xbf000e5>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 154 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 155 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
  <InsRsp    valid no error ins 0x81090000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 156 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 157 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 158 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 159 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp   valid no error rdata 0xa7472>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 160 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
  <InsRsp    valid no error ins 0x11200005>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 161 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 162 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b0>
  <InsRsp    valid no error ins 0x3e00008>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 163 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 164 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00020>
  <InsRsp    valid no error ins 0x3c042040>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 165 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00024>
  <InsRsp    valid no error ins 0x40846000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 166 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00028>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 167 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0002c>
  <InsRsp    valid no error ins 0x24840008>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 168 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00030>
  <InsRsp    valid no error ins 0xc4820000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 169 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 170 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000
****************** cycle 171 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 172 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 173 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 174 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0
  <MEMC.TGT_CMD_IDLE> Receive command from srcid 0x0000 / for address 0x000000000
****************** cycle 175 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
  <MEMC.TGT_CMD_READ> Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040
****************** cycle 176 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.READ_IDLE> Read request: srcid = 0 / address = 0 / nwords = 16
****************** cycle 177 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.READ_DIR_LOCK> Accessing directory:  address = 0 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 178 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
****************** cycle 179 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.READ_TRT_SET> Write in Transaction Table:  address = 0 / srcid = 0
****************** cycle 180 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.READ_TRT_REQ> Request GET transaction for address 0
****************** cycle 181 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 182 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram
****************** cycle 183 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction
****************** cycle 184 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
****************** cycle 185 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0xdead
****************** cycle 186 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xbeef
****************** cycle 187 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0x41200000
****************** cycle 188 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0
****************** cycle 189 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0
****************** cycle 190 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0
****************** cycle 191 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0
****************** cycle 192 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0
****************** cycle 193 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0
****************** cycle 194 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0
****************** cycle 195 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0
****************** cycle 196 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0
****************** cycle 197 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0
****************** cycle 198 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0
****************** cycle 199 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0
****************** cycle 200 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0
****************** cycle 201 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
****************** cycle 202 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
****************** cycle 203 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory
****************** cycle 204 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
****************** cycle 205 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
  <MEMC.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 0 / inval_required = 0
****************** cycle 206 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
****************** cycle 207 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT
****************** cycle 208 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
  <MEMC.XRAM_RSP_DIR_UPDT> Directory update:  way = 0 / set = 0 / count = 1 / is_cnt = 0
****************** cycle 209 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16
****************** cycle 210 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 211 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0
****************** cycle 212 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1
****************** cycle 213 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2
****************** cycle 214 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3
****************** cycle 215 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4
****************** cycle 216 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5
****************** cycle 217 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6
****************** cycle 218 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7
****************** cycle 219 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8
****************** cycle 220 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9
****************** cycle 221 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa
****************** cycle 222 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb
****************** cycle 223 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc
****************** cycle 224 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd
****************** cycle 225 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe
****************** cycle 226 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9
  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf
****************** cycle 227 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa
****************** cycle 228 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb
****************** cycle 229 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc
****************** cycle 230 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd
****************** cycle 231 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe
****************** cycle 232 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf
****************** cycle 233 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 234 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
  <InsRsp    valid no error ins 0x3c040000>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp   valid no error rdata 0x41200000>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 235 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00038>
  <InsRsp    valid no error ins 0x2484000c>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 236 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
  <InsRsp    valid no error ins 0xc4800000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC.DCACHE_IDLE> HIT in dcache
****************** cycle 237 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp   valid no error rdata 0>
  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 238 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc00040  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 239 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 240 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 241 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 242 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 243 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 244 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 245 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 246 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 247 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046020003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 248 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 249 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 250 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 251 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00014 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 252 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 253 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000402021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 254 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 255 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 256 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 257 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 258 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000602021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 259 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 260 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 261 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 262 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
****************** cycle 263 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 264 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 265 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
  <InsRsp    valid no error ins 0xbf00016>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 266 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00044>
  <InsRsp    valid no error ins 0x46020003>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 267 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00058>
  <InsRsp    valid no error ins 0x402021>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 268 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0005c>
  <InsRsp    valid no error ins 0xff000ee>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 269 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00060>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 270 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
  <InsRsp    valid no error ins 0x804021>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 271 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
  <InsRsp    valid no error ins 0x24090030>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 272 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 273 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc003c0  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 274 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 275 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 276 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 277 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 278 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 279 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 280 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 281 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 282 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 283 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 284 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 285 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 286 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 287 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 288 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 289 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 290 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 291 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 292 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 293 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 294 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 295 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 296 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 297 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
****************** cycle 298 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 299 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 300 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 301 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
  <InsRsp    valid no error ins 0x24090078>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 302 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 303 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 304 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 305 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 306 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 307 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 308 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 309 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 310 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 311 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 312 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 313 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 314 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 315 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 316 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc00400  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 317 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 318 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 319 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 320 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 321 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 322 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 323 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 324 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 325 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 326 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 327 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 328 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 329 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 330 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc00009c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 331 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 332 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 333 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 334 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 335 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 336 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 337 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 338 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 339 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 340 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 341 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
****************** cycle 342 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 343 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 344 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 345 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 346 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 347 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 348 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 349 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 350 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 351 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 352 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 353 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 354 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 355 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 356 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 357 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 358 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 359 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 360 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 361 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 362 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 363 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 364 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 365 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 366 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 367 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 368 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 369 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 370 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 371 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 372 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 373 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 374 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 375 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 376 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 377 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 378 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 379 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 380 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 381 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 382 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 383 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 384 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 385 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 386 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 387 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 388 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 389 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 390 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 391 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 392 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 393 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 394 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 395 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 396 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 397 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 398 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 399 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 400 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 401 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 402 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 403 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 404 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 405 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 406 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 407 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 408 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 409 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 410 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 411 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 412 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 413 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 414 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 415 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 416 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 417 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 418 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 419 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 420 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 421 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 422 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 423 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 424 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 425 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 426 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 427 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 428 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 429 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 430 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 431 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 432 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 433 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 434 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 435 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 436 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 437 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
  <InsRsp    valid no error ins 0x3e00008>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 438 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 439 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00064>
  <InsRsp    valid no error ins 0x24040020>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 440 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
  <InsRsp    valid no error ins 0xa3440000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 441 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
  <InsRsp    valid no error ins 0x602021>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 442 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00070>
  <InsRsp    valid no error ins 0xff000ee>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 443 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00074>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 444 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
  <InsRsp    valid no error ins 0x804021>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 445 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
  <InsRsp    valid no error ins 0x24090030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 446 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 447 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
  <InsRsp    valid no error ins 0x24090078>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000020  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 448 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
  <InsRsp    valid no error ins 0xa3490000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 449 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 450 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 451 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 452 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 453 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 454 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 455 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 456 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 457 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
  <InsRsp    valid no error ins 0x24090008>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 458 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 459 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 460 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 461 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 462 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 463 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 464 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 465 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 466 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 467 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 468 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 469 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 470 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 471 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 472 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 473 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 474 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 475 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 476 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 477 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 478 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 479 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 480 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 481 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 482 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 483 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 484 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 485 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 486 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 487 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 488 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 489 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 490 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 491 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 492 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 493 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 494 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 495 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 496 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 497 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 498 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 499 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 500 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 501 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 502 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 503 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 504 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 505 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 506 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 507 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 508 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 509 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 510 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 511 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 512 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 513 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 514 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 515 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 516 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 517 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 518 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 519 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 520 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 521 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 522 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 523 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 524 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 525 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 526 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 527 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 528 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 529 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 530 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 531 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 532 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 533 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 534 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 535 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 536 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 537 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 538 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 539 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 540 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 541 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 542 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 543 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 544 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 545 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 546 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 547 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 548 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 549 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
  <InsRsp    valid no error ins 0x3c0af000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 550 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
  <InsRsp    valid no error ins 0x10a5024>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 551 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
  <InsRsp    valid no error ins 0xa5702>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 552 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
  <InsRsp    valid no error ins 0x294b000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 553 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
  <InsRsp    valid no error ins 0x11600004>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 554 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 555 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
  <InsRsp    valid no error ins 0x214a0030>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 556 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
  <InsRsp    valid no error ins 0xbf000fe>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 557 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 558 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
  <InsRsp    valid no error ins 0xa34a0000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 559 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
  <InsRsp    valid no error ins 0x2129ffff>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 560 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
  <InsRsp    valid no error ins 0x1d20fff3>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 561 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
  <InsRsp    valid no error ins 0x84100>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 562 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
  <InsRsp    valid no error ins 0x3e00008>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 563 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 564 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00078>
  <InsRsp    valid no error ins 0x2404000a>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 565 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0007c>
  <InsRsp    valid no error ins 0xa3440000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 566 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp   valid no error rdata 0>
  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 567 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : RD  @ = 0x0bfc00080  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
****************** cycle 568 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 569 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 570 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 571 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 572 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 573 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 574 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 575 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 576 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 577 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
****************** cycle 578 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 579 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 580 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 581 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840138 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 582 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 583 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 584 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 585 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 586 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 587 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 588 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840140 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 589 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 590 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
****************** cycle 591 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
****************** cycle 592 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
****************** cycle 593 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
****************** cycle 594 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
  <InsRsp    valid no error ins 0x24040000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 595 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00084>
  <InsRsp    valid no error ins 0xaf640000>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 596 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
  <InsRsp    valid no error ins 0xbf00022>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 597 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 598 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
  <InsRsp    valid no error ins 0xbf00022>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
proc_ini_d CMD VCI : WR  @ = 0x0e0000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
****************** cycle 599 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 600 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
  <InsRsp    valid no error ins 0xbf00022>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
****************** cycle 601 ************************************************
PROC proc
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
  Data TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
  Instruction TLB
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
MEMC memc
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
vci_exit terminate simulation, status 0x000000000
