//////////////////////////////////////////////////////////////////////////////
// File: tsarv4_cluster_ring.h  
// Author: Alain Greiner 
// Copyright: UPMC/LIP6
// Date : march 2011
// This program is released under the GNU public license
//////////////////////////////////////////////////////////////////////////////
// This file define a TSAR cluster architecture without virtual memory,
// - It uses virtual_dspin as distributed global interconnect 
// - It uses vci_local_ring_fast as local interconnect 
// - It uses the vci_cc_xcache_wrapper_v4
// - It uses the vci_mem_cache_v4
// - It contains a private RAM a variable latency to emulate the L3 cache
// - It can contains 1, 2 or 4 processors
// - Each processor has a private local TTY terminal (vci_multi_tty)
// - Each processor has a private dma channel (vci_multi_dma)
// - It uses the vci_xicu interrupt controller
// - The nprocs tty irq are connected to IRQ_IN[0]...IRQ_IN[3]
// - The nprocs dma irq are connected to IRQ_IN[4]...IRQ_IN[7]
// - The peripherals BDEV, FBUF, and the boot BROM are in the cluster 
//   containing address 0xBFC00000, and the bdev_irq is connected to IRQ_IN[8]
////////////////////////////////////////////////////////////////////////////////// 

#ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_RING_H
#define SOCLIB_CABA_TSAR_CLUSTER_V4_RING_H

#include <systemc>
#include <sys/time.h>
#include <iostream>
#include <sstream>
#include <cstdlib>
#include <cstdarg>

#include "gdbserver.h"
#include "mapping_table.h"
#include "mips32.h"
#include "vci_mem_cache_v4.h"
#include "vci_cc_xcache_wrapper_v4.h"
#include "vci_simple_ram.h"
#include "vci_xicu.h"
#include "vci_local_ring_fast.h"
#include "virtual_dspin_router.h"
#include "vci_multi_tty.h"
#include "vci_block_device_tsar_v4.h"
#include "vci_framebuffer.h"
#include "vci_multi_dma.h"

namespace soclib {
namespace caba	{

///////////////////////////////////////////////////////////////////////////
template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
class TsarV4ClusterRing 
///////////////////////////////////////////////////////////////////////////
    : public soclib::caba::BaseModule
{

  public:

	// Ports
    	sc_in<bool>                             		p_clk;
    	sc_in<bool>                             		p_resetn;
	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
        soclib::caba::DspinOutput<rsp_width>                   	**p_rsp_out;
        soclib::caba::DspinInput<rsp_width>                   	**p_rsp_in;

        // interrupt signals
	sc_signal<bool>     		signal_false;
	sc_signal<bool> 		signal_proc_it[4];
	sc_signal<bool> 		signal_irq_mdma[4];
	sc_signal<bool>			signal_irq_mtty;
	sc_signal<bool> 		signal_irq_bdev;
	
	// DSPIN signals between local ring & global interconnects
	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_d; 
	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_d; 
	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_c;
	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_c; 
	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_d; 
	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_d; 
	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_c;
	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_c;

	// Direct VCI signals
	VciSignals<vci_param> 		signal_vci_ini_d_proc[4]; 
	VciSignals<vci_param>  		signal_vci_ini_d_bdev; 
	VciSignals<vci_param>  		signal_vci_ini_d_mdma; 

	VciSignals<vci_param>		signal_vci_tgt_d_memc;
	VciSignals<vci_param> 		signal_vci_tgt_d_mtty;
	VciSignals<vci_param> 		signal_vci_tgt_d_xicu;
	VciSignals<vci_param> 		signal_vci_tgt_d_bdev;
	VciSignals<vci_param> 		signal_vci_tgt_d_mdma;
	VciSignals<vci_param> 		signal_vci_tgt_d_brom;
	VciSignals<vci_param> 		signal_vci_tgt_d_fbuf;

	// Coherence VCi signals
	VciSignals<vci_param> 		signal_vci_ini_c_proc[4];
	VciSignals<vci_param> 		signal_vci_tgt_c_proc[4];
	VciSignals<vci_param> 		signal_vci_ini_c_memc;
	VciSignals<vci_param> 		signal_vci_tgt_c_memc;

	// external RAM VCI signal
	VciSignals<vci_param> 		signal_vci_xram;
	
        // Components

        VciCcXCacheWrapperV4<vci_param, iss_t>*                 proc[4];
        VciMemCacheV4<vci_param>*                               memc;
        VciXicu<vci_param>*                                     xicu;
        VciLocalRingFast<vci_param,cmd_width,rsp_width>*        ringd;
        VciLocalRingFast<vci_param,cmd_width,rsp_width>*        ringc;
        VirtualDspinRouter<cmd_width>*   	                cmdrouter;
        VirtualDspinRouter<rsp_width>*	                        rsprouter;
        VciSimpleRam<vci_param>*                 		brom;
        VciMultiTty<vci_param>*                  		mtty;
        VciFrameBuffer<vci_param>*               		fbuf;
        VciBlockDeviceTsarV4<vci_param>*         		bdev;
        VciMultiDma<vci_param>*                 		mdma;
        VciSimpleRam<vci_param>*				xram;

	TsarV4ClusterRing(	sc_module_name  insname,
                        size_t		nprocs,					// number of processors 
			size_t		n_x,					// x coordinate
			size_t		n_y,					// y coordinate
			size_t		n_cluster,				// y + ymax*x
			const 		soclib::common::MappingTable &mtd,	// direct mapping table
			const		soclib::common::MappingTable &mtc,	// coherence mapping table
			const		soclib::common::MappingTable &mtx,	// xram mapping table
			size_t		x_width,				// x field number of bits
			size_t		y_width,				// y field number of bits
                        size_t		tgtid_memc,
                        size_t		tgtid_xicu,
                        size_t		tgtid_fbuf,
                        size_t		tgtid_mtty,
                        size_t		tgtid_brom,
                        size_t		tgtid_bdev,
                        size_t		tgtid_mdma,
                        size_t		memc_ways,				// number of ways for MEMC
                        size_t		memc_sets,				// number of sets for MEMC
                        size_t		l1_i_ways,				// number of ways for L1 ICACHE
                        size_t		l1_i_sets,				// number of sets for L1 ICACHE
                        size_t		l1_d_ways,				// number of ways for L1 DCACHE
                        size_t		l1_d_sets,				// number of sets for L1 DCACHE
                        size_t		xram_latency,				// external ram latency
			bool		io,					// I/O cluster if true
                        size_t          xfb,					// frame buffer pixels
                        size_t          yfb,					// frame buffer lines
                        char*           disk_name,				// virtual disk name for BDEV
                        size_t          block_size,				// block size for BDEV
                        Loader          loader);				// loader for BROM

	~TsarV4ClusterRing();
};
}}

#endif
