Index: /trunk/platforms/tsar_generic_iob/arch.py =================================================================== --- /trunk/platforms/tsar_generic_iob/arch.py (revision 1001) +++ /trunk/platforms/tsar_generic_iob/arch.py (revision 1002) @@ -27,5 +27,5 @@ # - nb_ttys : number of TTY channels # - fbf_width : frame_buffer width = frame_buffer heigth -# - ioc_type : can be 'BDV','HBA','SDC', but not 'RDK' +# - ioc_type : can be 'BDV','HBA','SDC', 'SPI' but not 'RDK' # # @@ -76,5 +76,5 @@ irq_per_proc = 4 peri_increment = 0x10000 - mwr_type = 'GCD' + mwr_type = 'CPY' ### constructor parameters checking @@ -93,5 +93,5 @@ ((x_io == x_size-1) and (y_io == y_size-1)) ) - assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' ] ) + assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' , 'SPI' ] ) assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' , 'NONE' ] ) @@ -294,4 +294,5 @@ if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA' if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC' + if ( ioc_type == 'SPI' ): isr_ioc = 'ISR_SPI' mapping.addIrq( pic, index = 8, src = ioc, Index: /trunk/platforms/tsar_generic_iob/top.cpp =================================================================== --- /trunk/platforms/tsar_generic_iob/top.cpp (revision 1001) +++ /trunk/platforms/tsar_generic_iob/top.cpp (revision 1002) @@ -141,4 +141,6 @@ #include "vci_multi_ahci.h" #include "vci_block_device_tsar.h" +#include "vci_ahci_sdc.h" +#include "sd_card.h" #include "vci_framebuffer.h" #include "vci_iox_network.h" @@ -856,40 +858,104 @@ VciSignals signal_vci_tgt_iopi("signal_vci_tgt_iopi"); - // Horizontal inter-clusters INT network DSPIN - DspinSignals*** signal_dspin_int_cmd_h_inc = - alloc_elems >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); - DspinSignals*** signal_dspin_int_cmd_h_dec = - alloc_elems >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); - DspinSignals*** signal_dspin_int_rsp_h_inc = - alloc_elems >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); - DspinSignals*** signal_dspin_int_rsp_h_dec = - alloc_elems >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); - - // Vertical inter-clusters INT network DSPIN - DspinSignals*** signal_dspin_int_cmd_v_inc = - alloc_elems >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); - DspinSignals*** signal_dspin_int_cmd_v_dec = - alloc_elems >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); - DspinSignals*** signal_dspin_int_rsp_v_inc = - alloc_elems >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); - DspinSignals*** signal_dspin_int_rsp_v_dec = - alloc_elems >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); - - // Mesh boundaries INT network DSPIN - DspinSignals**** signal_dspin_false_int_cmd_in = - alloc_elems >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); - DspinSignals**** signal_dspin_false_int_cmd_out = - alloc_elems >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); - DspinSignals**** signal_dspin_false_int_rsp_in = - alloc_elems >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); - DspinSignals**** signal_dspin_false_int_rsp_out = - alloc_elems >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); - - - // Horizontal inter-clusters RAM network DSPIN + // Horizontal inter-clusters INT_CMD DSPIN + DspinSignals** signal_dspin_int_cmd_h_inc = + alloc_elems >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_int_cmd_h_dec = + alloc_elems >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX); + + // Horizontal inter-clusters INT_RSP DSPIN + DspinSignals** signal_dspin_int_rsp_h_inc = + alloc_elems >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_int_rsp_h_dec = + alloc_elems >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX); + + // Horizontal inter-clusters INT_M2P DSPIN + DspinSignals** signal_dspin_int_m2p_h_inc = + alloc_elems >("signal_dspin_int_m2p_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_int_m2p_h_dec = + alloc_elems >("signal_dspin_int_m2p_h_dec", XMAX-1, YMAX); + + // Horizontal inter-clusters INT_P2M DSPIN + DspinSignals** signal_dspin_int_p2m_h_inc = + alloc_elems >("signal_dspin_int_p2m_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_int_p2m_h_dec = + alloc_elems >("signal_dspin_int_p2m_h_dec", XMAX-1, YMAX); + + // Horizontal inter-clusters INT_CLA DSPIN + DspinSignals** signal_dspin_int_cla_h_inc = + alloc_elems >("signal_dspin_int_cla_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_int_cla_h_dec = + alloc_elems >("signal_dspin_int_cla_h_dec", XMAX-1, YMAX); + + + // Vertical inter-clusters INT_CMD DSPIN + DspinSignals** signal_dspin_int_cmd_v_inc = + alloc_elems >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_int_cmd_v_dec = + alloc_elems >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1); + + // Vertical inter-clusters INT_RSP DSPIN + DspinSignals** signal_dspin_int_rsp_v_inc = + alloc_elems >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_int_rsp_v_dec = + alloc_elems >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1); + + // Vertical inter-clusters INT_M2P DSPIN + DspinSignals** signal_dspin_int_m2p_v_inc = + alloc_elems >("signal_dspin_int_m2p_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_int_m2p_v_dec = + alloc_elems >("signal_dspin_int_m2p_v_dec", XMAX, YMAX-1); + + // Vertical inter-clusters INT_P2M DSPIN + DspinSignals** signal_dspin_int_p2m_v_inc = + alloc_elems >("signal_dspin_int_p2m_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_int_p2m_v_dec = + alloc_elems >("signal_dspin_int_p2m_v_dec", XMAX, YMAX-1); + + // Vertical inter-clusters INT_CLA DSPIN + DspinSignals** signal_dspin_int_cla_v_inc = + alloc_elems >("signal_dspin_int_cla_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_int_cla_v_dec = + alloc_elems >("signal_dspin_int_cla_v_dec", XMAX, YMAX-1); + + + // Mesh boundaries INT_CMD DSPIN + DspinSignals*** signal_dspin_false_int_cmd_in = + alloc_elems >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_int_cmd_out = + alloc_elems >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4); + + // Mesh boundaries INT_RSP DSPIN + DspinSignals*** signal_dspin_false_int_rsp_in = + alloc_elems >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_int_rsp_out = + alloc_elems >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4); + + // Mesh boundaries INT_M2P DSPIN + DspinSignals*** signal_dspin_false_int_m2p_in = + alloc_elems >("signal_dspin_false_int_m2p_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_int_m2p_out = + alloc_elems >("signal_dspin_false_int_m2P_out", XMAX, YMAX, 4); + + // Mesh boundaries INT_P2M DSPIN + DspinSignals*** signal_dspin_false_int_p2m_in = + alloc_elems >("signal_dspin_false_int_p2m_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_int_p2m_out = + alloc_elems >("signal_dspin_false_int_p2m_out", XMAX, YMAX, 4); + + // Mesh boundaries INT_CLA DSPIN + DspinSignals*** signal_dspin_false_int_cla_in = + alloc_elems >("signal_dspin_false_int_cla_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_int_cla_out = + alloc_elems >("signal_dspin_false_int_cla_out", XMAX, YMAX, 4); + + + // Horizontal inter-clusters RAM_CMD DSPIN DspinSignals** signal_dspin_ram_cmd_h_inc = alloc_elems >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); DspinSignals** signal_dspin_ram_cmd_h_dec = alloc_elems >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); + + // Horizontal inter-clusters RAM_RSP DSPIN DspinSignals** signal_dspin_ram_rsp_h_inc = alloc_elems >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); @@ -897,9 +963,11 @@ alloc_elems >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); - // Vertical inter-clusters RAM network DSPIN + // Vertical inter-clusters RAM_CMD DSPIN DspinSignals** signal_dspin_ram_cmd_v_inc = alloc_elems >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); DspinSignals** signal_dspin_ram_cmd_v_dec = alloc_elems >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); + + // Vertical inter-clusters RAM_RSP DSPIN DspinSignals** signal_dspin_ram_rsp_v_inc = alloc_elems >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); @@ -907,13 +975,26 @@ alloc_elems >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); - // Mesh boundaries RAM network DSPIN + // Mesh boundaries RAM_CMD DSPIN DspinSignals*** signal_dspin_false_ram_cmd_in = alloc_elems >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); DspinSignals*** signal_dspin_false_ram_cmd_out = alloc_elems >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); + + // Mesh boundaries RAM_RSP DSPIN DspinSignals*** signal_dspin_false_ram_rsp_in = alloc_elems >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); DspinSignals*** signal_dspin_false_ram_rsp_out = alloc_elems >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); + + // SD card signals + sc_signal signal_sdc_clk; + sc_signal signal_sdc_cmd_enable_to_card; + sc_signal signal_sdc_cmd_value_to_card; + sc_signal signal_sdc_dat_enable_to_card; + sc_signal signal_sdc_dat_value_to_card[4]; + sc_signal signal_sdc_cmd_enable_from_card; + sc_signal signal_sdc_cmd_value_from_card; + sc_signal signal_sdc_dat_enable_from_card; + sc_signal signal_sdc_dat_value_from_card[4]; //////////////////////////// @@ -985,5 +1066,5 @@ 64, // burst size (bytes) 0 ); // disk latency -#elif ( USE_IOC_BDV or USE_IOC_SDC ) +#elif ( USE_IOC_BDV ) VciBlockDeviceTsar* disk; @@ -996,4 +1077,17 @@ 64, // burst size (bytes) 0 ); // disk latency +#elif ( USE_IOC_SDC ) + + VciAhciSdc* disk; + disk = new VciAhciSdc( "disk", + maptab_iox, + IntTab(0, DISK_LOCAL_SRCID), + IntTab(0, IOX_DISK_TGT_ID), + 64 ); // burst size (bytes) + SdCard* card; + card = new SdCard( "card", + disk_name, + 10, // RX one block latency + 10 ); // TX one block latency #endif @@ -1175,12 +1269,64 @@ // DISK connexion + +#if ( USE_IOC_HBA ) + disk->p_clk (signal_clk); disk->p_resetn (signal_resetn); disk->p_vci_target (signal_vci_tgt_disk); disk->p_vci_initiator (signal_vci_ini_disk); -#if ( USE_IOC_HBA ) disk->p_channel_irq[0] (signal_irq_disk); -#else + +#elif ( USE_IOC_BDV ) + + disk->p_clk (signal_clk); + disk->p_resetn (signal_resetn); + disk->p_vci_target (signal_vci_tgt_disk); + disk->p_vci_initiator (signal_vci_ini_disk); disk->p_irq (signal_irq_disk); + +#elif ( USE_IOC_SDC ) + + disk->p_clk (signal_clk); + disk->p_resetn (signal_resetn); + disk->p_vci_target (signal_vci_tgt_disk); + disk->p_vci_initiator (signal_vci_ini_disk); + disk->p_irq (signal_irq_disk); + + disk->p_sdc_clk (signal_sdc_clk); + disk->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_to_card); + disk->p_sdc_cmd_value_out (signal_sdc_cmd_value_to_card); + disk->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_from_card); + disk->p_sdc_cmd_value_in (signal_sdc_cmd_value_from_card); + disk->p_sdc_dat_enable_out (signal_sdc_dat_enable_to_card); + disk->p_sdc_dat_value_out[0] (signal_sdc_dat_value_to_card[0]); + disk->p_sdc_dat_value_out[1] (signal_sdc_dat_value_to_card[1]); + disk->p_sdc_dat_value_out[2] (signal_sdc_dat_value_to_card[2]); + disk->p_sdc_dat_value_out[3] (signal_sdc_dat_value_to_card[3]); + disk->p_sdc_dat_enable_in (signal_sdc_dat_enable_from_card); + disk->p_sdc_dat_value_in[0] (signal_sdc_dat_value_from_card[0]); + disk->p_sdc_dat_value_in[1] (signal_sdc_dat_value_from_card[1]); + disk->p_sdc_dat_value_in[2] (signal_sdc_dat_value_from_card[2]); + disk->p_sdc_dat_value_in[3] (signal_sdc_dat_value_from_card[3]); + + card->p_clk (signal_clk); + card->p_resetn (signal_resetn); + + card->p_sdc_clk (signal_sdc_clk); + card->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_from_card); + card->p_sdc_cmd_value_out (signal_sdc_cmd_value_from_card); + card->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_to_card); + card->p_sdc_cmd_value_in (signal_sdc_cmd_value_to_card); + card->p_sdc_dat_enable_out (signal_sdc_dat_enable_from_card); + card->p_sdc_dat_value_out[0] (signal_sdc_dat_value_from_card[0]); + card->p_sdc_dat_value_out[1] (signal_sdc_dat_value_from_card[1]); + card->p_sdc_dat_value_out[2] (signal_sdc_dat_value_from_card[2]); + card->p_sdc_dat_value_out[3] (signal_sdc_dat_value_from_card[3]); + card->p_sdc_dat_enable_in (signal_sdc_dat_enable_to_card); + card->p_sdc_dat_value_in[0] (signal_sdc_dat_value_to_card[0]); + card->p_sdc_dat_value_in[1] (signal_sdc_dat_value_to_card[1]); + card->p_sdc_dat_value_in[2] (signal_sdc_dat_value_to_card[2]); + card->p_sdc_dat_value_in[3] (signal_sdc_dat_value_to_card[3]); + #endif @@ -1286,19 +1432,28 @@ for (size_t y = 0; y < YMAX; y++) { - for (size_t k = 0; k < 3; k++) - { - clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); - clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); - clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); - clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); - } - - for (size_t k = 0; k < 2; k++) - { - clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); - clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); - clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); - clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); - } + clusters[x][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_int_cmd_h_inc[x][y]); + clusters[x+1][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_int_cmd_h_inc[x][y]); + clusters[x][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_int_cmd_h_dec[x][y]); + clusters[x+1][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_int_cmd_h_dec[x][y]); + + clusters[x][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_int_rsp_h_inc[x][y]); + clusters[x+1][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_int_rsp_h_inc[x][y]); + clusters[x][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_int_rsp_h_dec[x][y]); + clusters[x+1][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_int_rsp_h_dec[x][y]); + + clusters[x][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_int_m2p_h_inc[x][y]); + clusters[x+1][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_int_m2p_h_inc[x][y]); + clusters[x][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_int_m2p_h_dec[x][y]); + clusters[x+1][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_int_m2p_h_dec[x][y]); + + clusters[x][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_int_p2m_h_inc[x][y]); + clusters[x+1][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_int_p2m_h_inc[x][y]); + clusters[x][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_int_p2m_h_dec[x][y]); + clusters[x+1][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_int_p2m_h_dec[x][y]); + + clusters[x][y]->p_dspin_int_cla_out[EAST] (signal_dspin_int_cla_h_inc[x][y]); + clusters[x+1][y]->p_dspin_int_cla_in[WEST] (signal_dspin_int_cla_h_inc[x][y]); + clusters[x][y]->p_dspin_int_cla_in[EAST] (signal_dspin_int_cla_h_dec[x][y]); + clusters[x+1][y]->p_dspin_int_cla_out[WEST] (signal_dspin_int_cla_h_dec[x][y]); clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); @@ -1306,4 +1461,5 @@ clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); @@ -1323,19 +1479,28 @@ for (size_t x = 0; x < XMAX; x++) { - for (size_t k = 0; k < 3; k++) - { - clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); - clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); - clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); - clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); - } - - for (size_t k = 0; k < 2; k++) - { - clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); - clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); - clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); - clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); - } + clusters[x][y]->p_dspin_int_cmd_out[NORTH] (signal_dspin_int_cmd_v_inc[x][y]); + clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_int_cmd_v_inc[x][y]); + clusters[x][y]->p_dspin_int_cmd_in[NORTH] (signal_dspin_int_cmd_v_dec[x][y]); + clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_int_cmd_v_dec[x][y]); + + clusters[x][y]->p_dspin_int_rsp_out[NORTH] (signal_dspin_int_rsp_v_inc[x][y]); + clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_int_rsp_v_inc[x][y]); + clusters[x][y]->p_dspin_int_rsp_in[NORTH] (signal_dspin_int_rsp_v_dec[x][y]); + clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_int_rsp_v_dec[x][y]); + + clusters[x][y]->p_dspin_int_m2p_out[NORTH] (signal_dspin_int_m2p_v_inc[x][y]); + clusters[x][y+1]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_int_m2p_v_inc[x][y]); + clusters[x][y]->p_dspin_int_m2p_in[NORTH] (signal_dspin_int_m2p_v_dec[x][y]); + clusters[x][y+1]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_int_m2p_v_dec[x][y]); + + clusters[x][y]->p_dspin_int_p2m_out[NORTH] (signal_dspin_int_p2m_v_inc[x][y]); + clusters[x][y+1]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_int_p2m_v_inc[x][y]); + clusters[x][y]->p_dspin_int_p2m_in[NORTH] (signal_dspin_int_p2m_v_dec[x][y]); + clusters[x][y+1]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_int_p2m_v_dec[x][y]); + + clusters[x][y]->p_dspin_int_cla_out[NORTH] (signal_dspin_int_cla_v_inc[x][y]); + clusters[x][y+1]->p_dspin_int_cla_in[SOUTH] (signal_dspin_int_cla_v_inc[x][y]); + clusters[x][y]->p_dspin_int_cla_in[NORTH] (signal_dspin_int_cla_v_dec[x][y]); + clusters[x][y+1]->p_dspin_int_cla_out[SOUTH] (signal_dspin_int_cla_v_dec[x][y]); clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); @@ -1343,4 +1508,5 @@ clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); @@ -1356,29 +1522,38 @@ for (size_t y = 0; y < YMAX; y++) { - for (size_t k = 0; k < 3; k++) - { - clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); - clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); - clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); - clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); - } - - for (size_t k = 0; k < 2; k++) - { - clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); - clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); - clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); - clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); - } - - clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); - clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); - clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); - clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); - - clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); - clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); - clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); - clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); + clusters[0][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_false_int_cmd_in[0][y][WEST]); + clusters[0][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_false_int_cmd_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST]); + + clusters[0][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_false_int_rsp_in[0][y][WEST]); + clusters[0][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_false_int_rsp_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST]); + + clusters[0][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_false_int_m2p_in[0][y][WEST]); + clusters[0][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_false_int_m2p_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_false_int_m2p_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_false_int_m2p_out[XMAX-1][y][EAST]); + + clusters[0][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_false_int_p2m_in[0][y][WEST]); + clusters[0][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_false_int_p2m_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_false_int_p2m_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_false_int_p2m_out[XMAX-1][y][EAST]); + + clusters[0][y]->p_dspin_int_cla_in[WEST] (signal_dspin_false_int_cla_in[0][y][WEST]); + clusters[0][y]->p_dspin_int_cla_out[WEST] (signal_dspin_false_int_cla_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_int_cla_in[EAST] (signal_dspin_false_int_cla_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_int_cla_out[EAST] (signal_dspin_false_int_cla_out[XMAX-1][y][EAST]); + + clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); + + clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); } @@ -1388,29 +1563,38 @@ for (size_t x = 0; x < XMAX; x++) { - for (size_t k = 0; k < 3; k++) - { - clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); - clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); - clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); - clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); - } - - for (size_t k = 0; k < 2; k++) - { - clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); - clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); - clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); - clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); - } - - clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); - clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); - clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); - clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); - - clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); - clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); - clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); - clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); + clusters[x][0]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_false_int_cmd_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_false_int_cmd_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH]); + + clusters[x][0]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_false_int_rsp_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_false_int_rsp_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH]); + + clusters[x][0]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_false_int_m2p_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_false_int_m2p_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_int_m2p_in[NORTH] (signal_dspin_false_int_m2p_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_m2p_out[NORTH] (signal_dspin_false_int_m2p_out[x][YMAX-1][NORTH]); + + clusters[x][0]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_false_int_p2m_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_false_int_p2m_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_int_p2m_in[NORTH] (signal_dspin_false_int_p2m_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_p2m_out[NORTH] (signal_dspin_false_int_p2m_out[x][YMAX-1][NORTH]); + + clusters[x][0]->p_dspin_int_cla_in[SOUTH] (signal_dspin_false_int_cla_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_int_cla_out[SOUTH] (signal_dspin_false_int_cla_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_int_cla_in[NORTH] (signal_dspin_false_int_cla_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_int_cla_out[NORTH] (signal_dspin_false_int_cla_out[x][YMAX-1][NORTH]); + + clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); + + clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); } @@ -1433,19 +1617,28 @@ for (size_t a = 0; a < 4; a++) { - for (size_t k = 0; k < 3; k++) - { - signal_dspin_false_int_cmd_in[x][y][a][k].write = false; - signal_dspin_false_int_cmd_in[x][y][a][k].read = true; - signal_dspin_false_int_cmd_out[x][y][a][k].write = false; - signal_dspin_false_int_cmd_out[x][y][a][k].read = true; - } - - for (size_t k = 0; k < 2; k++) - { - signal_dspin_false_int_rsp_in[x][y][a][k].write = false; - signal_dspin_false_int_rsp_in[x][y][a][k].read = true; - signal_dspin_false_int_rsp_out[x][y][a][k].write = false; - signal_dspin_false_int_rsp_out[x][y][a][k].read = true; - } + signal_dspin_false_int_cmd_in[x][y][a].write = false; + signal_dspin_false_int_cmd_in[x][y][a].read = true; + signal_dspin_false_int_cmd_out[x][y][a].write = false; + signal_dspin_false_int_cmd_out[x][y][a].read = true; + + signal_dspin_false_int_rsp_in[x][y][a].write = false; + signal_dspin_false_int_rsp_in[x][y][a].read = true; + signal_dspin_false_int_rsp_out[x][y][a].write = false; + signal_dspin_false_int_rsp_out[x][y][a].read = true; + + signal_dspin_false_int_m2p_in[x][y][a].write = false; + signal_dspin_false_int_m2p_in[x][y][a].read = true; + signal_dspin_false_int_m2p_out[x][y][a].write = false; + signal_dspin_false_int_m2p_out[x][y][a].read = true; + + signal_dspin_false_int_p2m_in[x][y][a].write = false; + signal_dspin_false_int_p2m_in[x][y][a].read = true; + signal_dspin_false_int_p2m_out[x][y][a].write = false; + signal_dspin_false_int_p2m_out[x][y][a].read = true; + + signal_dspin_false_int_cla_in[x][y][a].write = false; + signal_dspin_false_int_cla_in[x][y][a].read = true; + signal_dspin_false_int_cla_out[x][y][a].write = false; + signal_dspin_false_int_cla_out[x][y][a].read = true; signal_dspin_false_ram_cmd_in[x][y][a].write = false; @@ -1493,6 +1686,6 @@ // clusters[0][0]->proc[0]->cache_monitor(0x800080ULL); - // Monitor a specific address for one L2 cache - // clusters[0][0]->memc->cache_monitor( 0x800080ULL, false ); // full line + // Monitor a specific address for one L2 cache (single word if second argument true) + // clusters[0][0]->memc->cache_monitor( 0x00FF8000ULL, false ); // Monitor a specific address for one XRAM @@ -1523,14 +1716,14 @@ // coprocessor in cluster(x,y) - clusters[x][y]->mwmr->print_trace(); - std::ostringstream mwmr_tgt_signame; - mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; - clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); - std::ostringstream mwmr_ini_signame; - mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; - clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); - if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); - if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); - if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); +// clusters[x][y]->mwmr->print_trace(); +// std::ostringstream mwmr_tgt_signame; +// mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; +// clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); +// std::ostringstream mwmr_ini_signame; +// mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; +// clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); +// if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); +// if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); +// if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); // local interrupts in cluster(x,y) @@ -1597,7 +1790,7 @@ // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); - cdma->print_trace(); - signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT"); - signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI"); +// cdma->print_trace(); +// signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT"); +// signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI"); // brom->print_trace(); @@ -1607,10 +1800,14 @@ // signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); -// disk->print_trace(); -// signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); -// signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); - - mnic->print_trace( 0x000 ); - signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); + disk->print_trace(); + signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); + signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); + +#if ( USE_IOC_SDC ) + card->print_trace(); +#endif + +// mnic->print_trace( 0x000 ); +// signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); // fbuf->print_trace(); @@ -1624,10 +1821,15 @@ // interrupts - if (signal_irq_disk) std::cout << "### IRQ_DISK ACTIVE" << std::endl; - if (signal_irq_mtty_rx[0]) std::cout << "### IRQ_MTTY_RX[0] ACTIVE" << std::endl; - if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; - if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; - if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; - if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; + if ( signal_irq_disk.read() ) + std::cout << "### IRQ_DISK ACTIVE" << std::endl; + + if ( signal_irq_mtty_rx[0].read() ) + std::cout << "### IRQ_MTTY_RX[0] ACTIVE" << std::endl; + + if ( signal_irq_mnic_rx[0].read() ) + std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; + + if ( signal_irq_mnic_tx[0].read() ) + std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; } } Index: /trunk/platforms/tsar_generic_iob/top.desc =================================================================== --- /trunk/platforms/tsar_generic_iob/top.desc (revision 1001) +++ /trunk/platforms/tsar_generic_iob/top.desc (revision 1002) @@ -55,4 +55,9 @@ cell_size = vci_cell_size_ext), + Uses('caba:vci_ahci_sdc', + cell_size = vci_cell_size_ext), + + Uses('caba:sd_card'), + # NIC Uses('caba:vci_multi_nic', Index: /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 1001) +++ /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 1002) @@ -80,8 +80,8 @@ dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), - Uses('caba:virtual_dspin_router', + Uses('caba:dspin_router', flit_width = parameter.Reference('dspin_int_cmd_width')), - Uses('caba:virtual_dspin_router', + Uses('caba:dspin_router', flit_width = parameter.Reference('dspin_int_rsp_width')), Index: /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 1001) +++ /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 1002) @@ -27,5 +27,4 @@ #include "vci_dspin_target_wrapper.h" #include "dspin_router.h" -#include "virtual_dspin_router.h" #include "vci_mwmr_dma.h" #include "vci_mem_cache.h" @@ -62,8 +61,14 @@ // These arrays of ports are used to connect the INT & RAM networks in top cell - soclib::caba::DspinOutput** p_dspin_int_cmd_out; - soclib::caba::DspinInput** p_dspin_int_cmd_in; - soclib::caba::DspinOutput** p_dspin_int_rsp_out; - soclib::caba::DspinInput** p_dspin_int_rsp_in; + soclib::caba::DspinOutput* p_dspin_int_cmd_out; + soclib::caba::DspinInput* p_dspin_int_cmd_in; + soclib::caba::DspinOutput* p_dspin_int_rsp_out; + soclib::caba::DspinInput* p_dspin_int_rsp_in; + soclib::caba::DspinOutput* p_dspin_int_m2p_out; + soclib::caba::DspinInput* p_dspin_int_m2p_in; + soclib::caba::DspinOutput* p_dspin_int_p2m_out; + soclib::caba::DspinInput* p_dspin_int_p2m_in; + soclib::caba::DspinOutput* p_dspin_int_cla_out; + soclib::caba::DspinInput* p_dspin_int_cla_in; soclib::caba::DspinOutput* p_dspin_ram_cmd_out; @@ -87,12 +92,16 @@ DspinSignals signal_int_dspin_cmd_l2g_d; DspinSignals signal_int_dspin_cmd_g2l_d; + + DspinSignals signal_int_dspin_rsp_l2g_d; + DspinSignals signal_int_dspin_rsp_g2l_d; + DspinSignals signal_int_dspin_m2p_l2g_c; DspinSignals signal_int_dspin_m2p_g2l_c; - DspinSignals signal_int_dspin_clack_l2g_c; - DspinSignals signal_int_dspin_clack_g2l_c; - DspinSignals signal_int_dspin_rsp_l2g_d; - DspinSignals signal_int_dspin_rsp_g2l_d; + DspinSignals signal_int_dspin_p2m_l2g_c; DspinSignals signal_int_dspin_p2m_g2l_c; + + DspinSignals signal_int_dspin_cla_l2g_c; + DspinSignals signal_int_dspin_cla_g2l_c; // INT network VCI signals between VCI components and VCI local crossbar @@ -111,8 +120,8 @@ // Coherence DSPIN signals between DSPIN local crossbars and CC components DspinSignals signal_int_dspin_m2p_memc; - DspinSignals signal_int_dspin_clack_memc; + DspinSignals signal_int_dspin_cla_memc; DspinSignals signal_int_dspin_p2m_memc; DspinSignals signal_int_dspin_m2p_proc[8]; - DspinSignals signal_int_dspin_clack_proc[8]; + DspinSignals signal_int_dspin_cla_proc[8]; DspinSignals signal_int_dspin_p2m_proc[8]; @@ -174,6 +183,9 @@ DspinLocalCrossbar* int_xbar_clack_c; - VirtualDspinRouter* int_router_cmd; - VirtualDspinRouter* int_router_rsp; + DspinRouter* int_router_cmd; + DspinRouter* int_router_rsp; + DspinRouter* int_router_m2p; + DspinRouter* int_router_p2m; + DspinRouter* int_router_cla; VciSimpleRam* xram; Index: /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 1001) +++ /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 1002) @@ -97,11 +97,22 @@ // Vectors of DSPIN ports for inter-cluster communications - p_dspin_int_cmd_in = alloc_elems >("p_int_cmd_in", 4, 3); - p_dspin_int_cmd_out = alloc_elems >("p_int_cmd_out", 4, 3); - p_dspin_int_rsp_in = alloc_elems >("p_int_rsp_in", 4, 2); - p_dspin_int_rsp_out = alloc_elems >("p_int_rsp_out", 4, 2); + p_dspin_int_cmd_in = alloc_elems >("p_int_cmd_in", 4); + p_dspin_int_cmd_out = alloc_elems >("p_int_cmd_out", 4); + + p_dspin_int_rsp_in = alloc_elems >("p_int_rsp_in", 4); + p_dspin_int_rsp_out = alloc_elems >("p_int_rsp_out", 4); + + p_dspin_int_m2p_in = alloc_elems >("p_int_m2p_in", 4); + p_dspin_int_m2p_out = alloc_elems >("p_int_m2p_out", 4); + + p_dspin_int_p2m_in = alloc_elems >("p_int_p2m_in", 4); + p_dspin_int_p2m_out = alloc_elems >("p_int_p2m_out", 4); + + p_dspin_int_cla_in = alloc_elems >("p_int_cla_in", 4); + p_dspin_int_cla_out = alloc_elems >("p_int_cla_out", 4); p_dspin_ram_cmd_in = alloc_elems >("p_ext_cmd_in", 4); p_dspin_ram_cmd_out = alloc_elems >("p_ext_cmd_out", 4); + p_dspin_ram_rsp_in = alloc_elems >("p_ext_rsp_in", 4); p_dspin_ram_rsp_out = alloc_elems >("p_ext_rsp_out", 4); @@ -114,9 +125,9 @@ } - ///////////////////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////////////////////////// // Hardware components - ///////////////////////////////////////////////////////////////////////////// - - //////////// PROCS + ////////////////////////////////////////////////////////////////////////////////// + + //////////// PROCS ///////////////////////////////////////////////////////////// for (size_t p = 0; p < nb_procs; p++) { @@ -147,5 +158,5 @@ } - /////////// MEMC + //////////// MEMC ///////////////////////////////////////////////////////////// std::ostringstream s_memc; s_memc << "memc_" << x_id << "_" << y_id; @@ -178,5 +189,5 @@ x_width + y_width + l_width); - /////////// XICU + /////////// XICU ////////////////////////////////////////////////////////////// std::ostringstream s_xicu; s_xicu << "xicu_" << x_id << "_" << y_id; @@ -190,5 +201,5 @@ xcu_nb_out); // number of output IRQs - //////////// MWMR controller and coprocessor + //////////// MWMR controller and COPROC //////////////////////////////////////// std::ostringstream s_mwmr; std::ostringstream s_copro; @@ -244,5 +255,5 @@ } - /////////// Direct LOCAL_XBAR(S) + /////////// VCI INT_CMD/RSP LOCAL_XBAR ////////////////////////////////////// size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; size_t nb_direct_targets = is_io ? 4 : 3; @@ -276,5 +287,5 @@ x_width + y_width + l_width); - //////////// Coherence LOCAL_XBAR(S) + //////////// DSPIN INT_M2P LOCAL_XBAR //////////////////////////////////////// std::ostringstream s_int_xbar_m2p_c; s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; @@ -291,4 +302,5 @@ true ); // broacast + //////////// DSPIN INT_P2M LOCAL_XBAR //////////////////////////////////////// std::ostringstream s_int_xbar_p2m_c; s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; @@ -305,4 +317,5 @@ false ); // no broacast + //////////// DSPIN INT_CLA LOCAL_XBAR //////////////////////////////////////// std::ostringstream s_int_xbar_clack_c; s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; @@ -319,24 +332,51 @@ false); // broadcast - ////////////// INT ROUTER(S) + //////////// DSPIN INT_CMD ROUTER //////////////////////////////////////////// std::ostringstream s_int_router_cmd; - s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; - int_router_cmd = new VirtualDspinRouter( + s_int_router_cmd << "int_router_cmd_" << x_id << "_" << y_id; + int_router_cmd = new DspinRouter( s_int_router_cmd.str().c_str(), x_id,y_id, // coordinate in the mesh x_width, y_width, // x & y fields width - 3, // nb virtual channels 4,4); // input & output fifo depths + //////////// DSPIN INT_RSP ROUTER //////////////////////////////////////////// std::ostringstream s_int_router_rsp; - s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; - int_router_rsp = new VirtualDspinRouter( + s_int_router_rsp << "int_router_rsp_" << x_id << "_" << y_id; + int_router_rsp = new DspinRouter( s_int_router_rsp.str().c_str(), - x_id,y_id, // router coordinates in mesh + x_id,y_id, // coordinates in mesh x_width, y_width, // x & y fields width - 2, // nb virtual channels 4,4); // input & output fifo depths - ////////////// XRAM + //////////// DSPIN INT_M2P ROUTER //////////////////////////////////////////// + std::ostringstream s_int_router_m2p; + s_int_router_m2p << "int_router_m2p_" << x_id << "_" << y_id; + int_router_m2p = new DspinRouter( + s_int_router_m2p.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4, // input & output fifo depths + true); // broadcast supported + + //////////// DSPIN INT_P2M ROUTER //////////////////////////////////////////// + std::ostringstream s_int_router_p2m; + s_int_router_p2m << "int_router_p2m_" << x_id << "_" << y_id; + int_router_p2m = new DspinRouter( + s_int_router_p2m.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + //////////// DSPIN INT_CLA ROUTER //////////////////////////////////////////// + std::ostringstream s_int_router_cla; + s_int_router_cla << "int_router_cla_" << x_id << "_" << y_id; + int_router_cla = new DspinRouter( + s_int_router_cla.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ////////////// XRAM ///////////////////////////////////////////////////////// std::ostringstream s_xram; s_xram << "xram_" << x_id << "_" << y_id; @@ -356,5 +396,5 @@ x_width + y_width + l_width); - ///////////// RAM ROUTER(S) + //////////// DSPIN RAM_CMD ROUTER /////////////////////////////////////////// std::ostringstream s_ram_router_cmd; s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; @@ -366,4 +406,5 @@ 4, 4); // input & output fifo depths + //////////// DSPIN RAM_RSP ROUTER /////////////////////////////////////////// std::ostringstream s_ram_router_rsp; s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; @@ -376,8 +417,8 @@ - ////////////////////// I/O CLUSTER ONLY /////////////////////// + ////////////////////// I/O CLUSTER ONLY /////////////////////////////////// if ( is_io ) { - /////////// IO_BRIDGE + /////////// IO_BRIDGE //////////////////////////////////////////////////// std::ostringstream s_iob; s_iob << "iob_" << x_id << "_" << y_id; @@ -406,4 +447,5 @@ vci_param_int::S); + //////////// DSPIN RAM_CMD LOCAL_XBAR /////////////////////////////////// std::ostringstream s_ram_xbar_cmd; s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; @@ -419,4 +461,5 @@ false); // support broadcast ? + //////////// DSPIN RAM_RSP LOCAL_XBAR /////////////////////////////////// std::ostringstream s_ram_xbar_rsp; s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; @@ -431,4 +474,5 @@ true, // use routing table ? false); // support broadcast ? + } // end if IO @@ -440,96 +484,4 @@ // : local srcid[memc] = nb_procs - //////////////////////// internal CMD & RSP routers - int_router_cmd->p_clk (this->p_clk); - int_router_cmd->p_resetn (this->p_resetn); - int_router_rsp->p_clk (this->p_clk); - int_router_rsp->p_resetn (this->p_resetn); - - for (int i = 0; i < 4; i++) - { - for(int k = 0; k < 3; k++) - { - int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); - int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); - } - - for(int k = 0; k < 2; k++) - { - int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); - int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); - } - } - - // local ports - int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); - int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); - int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); - int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); - int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); - int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); - - int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); - int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); - int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); - int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); - - ///////////////////// CMD DSPIN local crossbar direct - int_xbar_d->p_clk (this->p_clk); - int_xbar_d->p_resetn (this->p_resetn); - int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); - int_xbar_d->p_target_to_up (signal_int_vci_g2l); - - int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); - int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); - int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr); - int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr); - for (size_t p = 0; p < nb_procs; p++) - int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); - - if ( is_io ) - { - int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); - int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); - } - - int_wi_gate_d->p_clk (this->p_clk); - int_wi_gate_d->p_resetn (this->p_resetn); - int_wi_gate_d->p_vci (signal_int_vci_l2g); - int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); - int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); - - int_wt_gate_d->p_clk (this->p_clk); - int_wt_gate_d->p_resetn (this->p_resetn); - int_wt_gate_d->p_vci (signal_int_vci_g2l); - int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); - int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); - - ////////////////////// M2P DSPIN local crossbar coherence - int_xbar_m2p_c->p_clk (this->p_clk); - int_xbar_m2p_c->p_resetn (this->p_resetn); - int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); - int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); - int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); - for (size_t p = 0; p < nb_procs; p++) - int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); - - ////////////////////////// P2M DSPIN local crossbar coherence - int_xbar_p2m_c->p_clk (this->p_clk); - int_xbar_p2m_c->p_resetn (this->p_resetn); - int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); - int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); - int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); - for (size_t p = 0; p < nb_procs; p++) - int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); - - ////////////////////// CLACK DSPIN local crossbar coherence - int_xbar_clack_c->p_clk (this->p_clk); - int_xbar_clack_c->p_resetn (this->p_resetn); - int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); - int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); - int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); - for (size_t p = 0; p < nb_procs; p++) - int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); - //////////////////////////////////// Processors for (size_t p = 0; p < nb_procs; p++) @@ -537,8 +489,9 @@ proc[p]->p_clk (this->p_clk); proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_int_vci_ini_proc[p]); proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); - proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); + proc[p]->p_dspin_clack (signal_int_dspin_cla_proc[p]); for ( size_t j = 0 ; j < 6 ; j++) @@ -549,4 +502,6 @@ } + std::cout << " - processors connected" << std::endl; + ///////////////////////////////////// XICU xicu->p_clk (this->p_clk); @@ -563,4 +518,6 @@ else xicu->p_hwi[i] (signal_false); } + + std::cout << " - xcu connected" << std::endl; ///////////////////////////////////// MEMC @@ -571,5 +528,5 @@ memc->p_dspin_p2m (signal_int_dspin_p2m_memc); memc->p_dspin_m2p (signal_int_dspin_m2p_memc); - memc->p_dspin_clack (signal_int_dspin_clack_memc); + memc->p_dspin_clack (signal_int_dspin_cla_memc); memc->p_irq (signal_irq_memc); @@ -581,4 +538,6 @@ memc_ram_wi->p_vci (signal_ram_vci_ini_memc); + std::cout << " - memc connected" << std::endl; + //////////////////////////////////// XRAM xram->p_clk (this->p_clk); @@ -592,4 +551,6 @@ xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); + + std::cout << " - xram connected" << std::endl; /////////////////////////////////// GCD coprocessor @@ -633,4 +594,6 @@ } + std::cout << " - coproc connected" << std::endl; + /////////////////////////////////// CPY coprocessor if ( coproc_type == MWR_COPROC_CPY ) @@ -652,9 +615,10 @@ } - //////////////////////////// RAM network CMD & RSP routers + //////////////////////////// RAM NETWORK ROUTERS ram_router_cmd->p_clk (this->p_clk); ram_router_cmd->p_resetn (this->p_resetn); ram_router_rsp->p_clk (this->p_clk); ram_router_rsp->p_resetn (this->p_resetn); + for( size_t n=0 ; n<4 ; n++) { @@ -678,4 +642,112 @@ ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); } + + ///////////////////////////// INT NETWORK ROUTERS + int_router_cmd->p_clk (this->p_clk); + int_router_cmd->p_resetn (this->p_resetn); + int_router_rsp->p_clk (this->p_clk); + int_router_rsp->p_resetn (this->p_resetn); + int_router_m2p->p_clk (this->p_clk); + int_router_m2p->p_resetn (this->p_resetn); + int_router_p2m->p_clk (this->p_clk); + int_router_p2m->p_resetn (this->p_resetn); + int_router_cla->p_clk (this->p_clk); + int_router_cla->p_resetn (this->p_resetn); + + // loop on N/S/E/W ports + for (size_t i = 0; i < 4; i++) + { + int_router_cmd->p_out[i] (this->p_dspin_int_cmd_out[i]); + int_router_cmd->p_in[i] (this->p_dspin_int_cmd_in[i]); + + int_router_rsp->p_out[i] (this->p_dspin_int_rsp_out[i]); + int_router_rsp->p_in[i] (this->p_dspin_int_rsp_in[i]); + + int_router_m2p->p_out[i] (this->p_dspin_int_m2p_out[i]); + int_router_m2p->p_in[i] (this->p_dspin_int_m2p_in[i]); + + int_router_p2m->p_out[i] (this->p_dspin_int_p2m_out[i]); + int_router_p2m->p_in[i] (this->p_dspin_int_p2m_in[i]); + + int_router_cla->p_out[i] (this->p_dspin_int_cla_out[i]); + int_router_cla->p_in[i] (this->p_dspin_int_cla_in[i]); + } + + int_router_cmd->p_out[4] (signal_int_dspin_cmd_g2l_d); + int_router_cmd->p_in[4] (signal_int_dspin_cmd_l2g_d); + + int_router_rsp->p_out[4] (signal_int_dspin_rsp_g2l_d); + int_router_rsp->p_in[4] (signal_int_dspin_rsp_l2g_d); + + int_router_m2p->p_out[4] (signal_int_dspin_m2p_g2l_c); + int_router_m2p->p_in[4] (signal_int_dspin_m2p_l2g_c); + + int_router_p2m->p_out[4] (signal_int_dspin_p2m_g2l_c); + int_router_p2m->p_in[4] (signal_int_dspin_p2m_l2g_c); + + int_router_cla->p_out[4] (signal_int_dspin_cla_g2l_c); + int_router_cla->p_in[4] (signal_int_dspin_cla_l2g_c); + + std::cout << " - internal routers connected" << std::endl; + + + ///////////////////// CMD DSPIN local crossbar direct + int_xbar_d->p_clk (this->p_clk); + int_xbar_d->p_resetn (this->p_resetn); + int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); + int_xbar_d->p_target_to_up (signal_int_vci_g2l); + + int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); + int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); + int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr); + int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); + + if ( is_io ) + { + int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); + int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); + } + + int_wi_gate_d->p_clk (this->p_clk); + int_wi_gate_d->p_resetn (this->p_resetn); + int_wi_gate_d->p_vci (signal_int_vci_l2g); + int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); + int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); + + int_wt_gate_d->p_clk (this->p_clk); + int_wt_gate_d->p_resetn (this->p_resetn); + int_wt_gate_d->p_vci (signal_int_vci_g2l); + int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); + int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); + + ////////////////////// M2P DSPIN local crossbar coherence + int_xbar_m2p_c->p_clk (this->p_clk); + int_xbar_m2p_c->p_resetn (this->p_resetn); + int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); + int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); + int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); + + ////////////////////////// P2M DSPIN local crossbar coherence + int_xbar_p2m_c->p_clk (this->p_clk); + int_xbar_p2m_c->p_resetn (this->p_resetn); + int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); + int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); + int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); + + ////////////////////// CLACK DSPIN local crossbar coherence + int_xbar_clack_c->p_clk (this->p_clk); + int_xbar_clack_c->p_resetn (this->p_resetn); + int_xbar_clack_c->p_global_out (signal_int_dspin_cla_l2g_c); + int_xbar_clack_c->p_global_in (signal_int_dspin_cla_g2l_c); + int_xbar_clack_c->p_local_in[0] (signal_int_dspin_cla_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_clack_c->p_local_out[p] (signal_int_dspin_cla_proc[p]); + ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.