Changeset 1017 for trunk/modules/vci_block_device_tsar/caba
- Timestamp:
- Sep 30, 2015, 4:53:16 PM (9 years ago)
- Location:
- trunk/modules/vci_block_device_tsar/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
r733 r1017 168 168 T_WRITE_LBA = 7, 169 169 T_READ_LBA = 8, 170 T_WRITE_ OP= 9,170 T_WRITE_STATUS = 9, 171 171 T_READ_STATUS = 10, 172 172 T_WRITE_IRQEN = 11, 173 173 T_READ_IRQEN = 12, 174 T_READ_SIZE = 13, 175 T_READ_BLOCK = 14, 176 T_READ_ERROR = 15, 177 T_WRITE_ERROR = 16, 178 }; 179 180 // Error codes values 181 enum { 182 VCI_READ_OK = 0, 183 VCI_READ_ERROR = 1, 184 VCI_WRITE_OK = 2, 185 VCI_WRITE_ERROR = 3, 174 T_WRITE_OP = 13, 175 T_READ_SIZE = 14, 176 T_READ_BLOCK = 15, 177 T_ERROR = 16, 186 178 }; 187 179 -
trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp
r983 r1017 77 77 bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); 78 78 uint32_t cell = (uint32_t)((address & 0x3F)>>2); 79 bool pending = (r_initiator_fsm.read() != M_IDLE); 80 81 if ( !read && not found ) r_target_fsm = T_WRITE_ERROR; 82 else if( read && not found ) r_target_fsm = T_READ_ERROR; 83 else if( !read && not p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; 84 else if( read && not p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; 85 else if( !read && pending ) r_target_fsm = T_WRITE_ERROR; 79 bool running = (r_initiator_fsm.read() != M_IDLE); 80 81 if ( not found ) r_target_fsm = T_ERROR; 82 else if( not p_vci_target.eop.read() ) r_target_fsm = T_ERROR; 83 else if( running && (cell != BLOCK_DEVICE_STATUS) ) r_target_fsm = T_ERROR; 86 84 else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; 87 85 else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; … … 92 90 else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; 93 91 else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; 94 else if( !read && (cell == BLOCK_DEVICE_ OP) ) r_target_fsm = T_WRITE_OP;92 else if( !read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_WRITE_STATUS; 95 93 else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; 96 94 else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; 97 95 else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; 96 else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; 98 97 else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; 99 98 else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; 99 else r_target_fsm = T_ERROR; 100 100 101 101 // get write data value for both 32 bits and 64 bits data width … … 185 185 r_read = false; 186 186 r_go = true; 187 }188 else189 {190 191 #if SOCLIB_MODULE_DEBUG192 std::cout << " <BDEV_TGT WRITE_OP> value = SOFT RESET" << std::endl;193 #endif194 r_go = false;195 187 } 196 188 r_target_fsm = T_IDLE; … … 220 212 case T_READ_SIZE: 221 213 case T_READ_BLOCK: 222 case T_READ_ERROR: 223 case T_WRITE_ERROR: 214 case T_ERROR: 224 215 { 225 216 if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; … … 236 227 (r_initiator_fsm == M_WRITE_SUCCESS) || 237 228 (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; 229 } 230 break; 231 } 232 //////////////////// 233 case T_WRITE_STATUS: 234 { 235 if ( p_vci_target.rspack.read() ) 236 { 237 r_target_fsm = T_IDLE; 238 r_go = false; 238 239 } 239 240 break; … … 323 324 // in case of 8 bytes flits... 324 325 { 326 if ( r_go.read() == false ) // soft reset 327 { 328 r_initiator_fsm = M_IDLE; 329 break; 330 } 331 325 332 uint32_t nwords; 326 333 uint32_t offset = r_burst_offset.read(); … … 435 442 case M_WRITE_BURST: // Compute the number of words in the burst 436 443 { 444 if ( r_go.read() == false ) // soft reset 445 { 446 r_initiator_fsm = M_IDLE; 447 break; 448 } 449 437 450 uint32_t nwords; 438 451 uint32_t offset = r_burst_offset.read(); … … 584 597 else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; 585 598 else p_vci_target.rdata = BLOCK_DEVICE_BUSY; 586 p_vci_target.rerror = VCI_READ_OK;599 p_vci_target.rerror = 0; 587 600 break; 588 601 case T_READ_BUFFER: … … 590 603 p_vci_target.rspval = true; 591 604 p_vci_target.rdata = (uint32_t)r_buf_address.read(); 592 p_vci_target.rerror = VCI_READ_OK;605 p_vci_target.rerror = 0; 593 606 break; 594 607 case T_READ_BUFFER_EXT: … … 596 609 p_vci_target.rspval = true; 597 610 p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); 598 p_vci_target.rerror = VCI_READ_OK;611 p_vci_target.rerror = 0; 599 612 break; 600 613 case T_READ_COUNT: … … 602 615 p_vci_target.rspval = true; 603 616 p_vci_target.rdata = r_nblocks.read(); 604 p_vci_target.rerror = VCI_READ_OK;617 p_vci_target.rerror = 0; 605 618 break; 606 619 case T_READ_LBA: … … 608 621 p_vci_target.rspval = true; 609 622 p_vci_target.rdata = r_lba.read(); 610 p_vci_target.rerror = VCI_READ_OK;623 p_vci_target.rerror = 0; 611 624 break; 612 625 case T_READ_IRQEN: … … 614 627 p_vci_target.rspval = true; 615 628 p_vci_target.rdata = r_irq_enable.read(); 616 p_vci_target.rerror = VCI_READ_OK;629 p_vci_target.rerror = 0; 617 630 break; 618 631 case T_READ_SIZE: … … 620 633 p_vci_target.rspval = true; 621 634 p_vci_target.rdata = m_device_size; 622 p_vci_target.rerror = VCI_READ_OK;635 p_vci_target.rerror = 0; 623 636 break; 624 637 case T_READ_BLOCK: … … 626 639 p_vci_target.rspval = true; 627 640 p_vci_target.rdata = m_words_per_block*4; 628 p_vci_target.rerror = VCI_READ_OK;629 break; 630 case T_ READ_ERROR:641 p_vci_target.rerror = 0; 642 break; 643 case T_ERROR: 631 644 p_vci_target.cmdack = false; 632 645 p_vci_target.rspval = true; 633 646 p_vci_target.rdata = 0; 634 p_vci_target.rerror = VCI_READ_ERROR;635 break; 636 case T_WRITE_ERROR:647 p_vci_target.rerror = 1; 648 break; 649 default: // all write 637 650 p_vci_target.cmdack = false; 638 651 p_vci_target.rspval = true; 639 652 p_vci_target.rdata = 0; 640 p_vci_target.rerror = VCI_WRITE_ERROR; 641 break; 642 default: 643 p_vci_target.cmdack = false; 644 p_vci_target.rspval = true; 645 p_vci_target.rdata = 0; 646 p_vci_target.rerror = VCI_WRITE_OK; 653 p_vci_target.rerror = 0; 647 654 break; 648 655 } // end switch target fsm
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