Index: trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp
===================================================================
--- trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp	(revision 983)
+++ trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp	(revision 1017)
@@ -77,11 +77,9 @@
             bool     read = (p_vci_target.cmd.read() == vci_param::CMD_READ);
             uint32_t cell = (uint32_t)((address & 0x3F)>>2);
-            bool     pending = (r_initiator_fsm.read() != M_IDLE);
-
-            if     ( !read && not found )                         r_target_fsm = T_WRITE_ERROR;
-            else if(  read && not found )                         r_target_fsm = T_READ_ERROR;
-            else if( !read && not p_vci_target.eop.read() )       r_target_fsm = T_WRITE_ERROR;
-            else if(  read && not p_vci_target.eop.read() )       r_target_fsm = T_READ_ERROR;
-            else if( !read && pending )                           r_target_fsm = T_WRITE_ERROR;
+            bool     running = (r_initiator_fsm.read() != M_IDLE);
+
+            if     ( not found )                                  r_target_fsm = T_ERROR;
+            else if( not p_vci_target.eop.read() )                r_target_fsm = T_ERROR;
+            else if( running && (cell != BLOCK_DEVICE_STATUS) )   r_target_fsm = T_ERROR;
             else if( !read && (cell == BLOCK_DEVICE_BUFFER) )     r_target_fsm = T_WRITE_BUFFER;
             else if(  read && (cell == BLOCK_DEVICE_BUFFER) )     r_target_fsm = T_READ_BUFFER;
@@ -92,10 +90,12 @@
             else if( !read && (cell == BLOCK_DEVICE_LBA) )        r_target_fsm = T_WRITE_LBA;
             else if(  read && (cell == BLOCK_DEVICE_LBA) )        r_target_fsm = T_READ_LBA;
-            else if( !read && (cell == BLOCK_DEVICE_OP) )         r_target_fsm = T_WRITE_OP;
+            else if( !read && (cell == BLOCK_DEVICE_STATUS) )     r_target_fsm = T_WRITE_STATUS;
             else if(  read && (cell == BLOCK_DEVICE_STATUS) )     r_target_fsm = T_READ_STATUS;
             else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN;
             else if(  read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN;
+            else if( !read && (cell == BLOCK_DEVICE_OP) )         r_target_fsm = T_WRITE_OP;
             else if(  read && (cell == BLOCK_DEVICE_SIZE) )       r_target_fsm = T_READ_SIZE;
             else if(  read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK;
+            else                                                  r_target_fsm = T_ERROR;
 
             // get write data value for both 32 bits and 64 bits data width
@@ -185,12 +185,4 @@
                 r_read = false;
                 r_go   = true;
-            }
-            else
-            {
-
-#if SOCLIB_MODULE_DEBUG
-std::cout << "  <BDEV_TGT WRITE_OP> value = SOFT RESET" << std::endl;
-#endif
-                r_go   = false;
             }
             r_target_fsm = T_IDLE;
@@ -220,6 +212,5 @@
     case T_READ_SIZE:
     case T_READ_BLOCK:
-    case T_READ_ERROR:
-    case T_WRITE_ERROR:
+    case T_ERROR:
     {
         if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
@@ -236,4 +227,14 @@
                 (r_initiator_fsm == M_WRITE_SUCCESS) ||
                 (r_initiator_fsm == M_WRITE_ERROR  ) ) r_go = false;
+        }
+        break;
+    }
+    ////////////////////
+    case T_WRITE_STATUS:
+    {
+        if ( p_vci_target.rspack.read() )
+        {
+            r_target_fsm = T_IDLE;
+            r_go         = false;
         }
         break;
@@ -323,4 +324,10 @@
                         // in case of 8 bytes flits...
     {
+        if ( r_go.read() == false )   // soft reset
+        {
+            r_initiator_fsm = M_IDLE;
+            break;
+        }
+
         uint32_t nwords;
         uint32_t offset = r_burst_offset.read();
@@ -435,4 +442,10 @@
     case M_WRITE_BURST:  // Compute the number of words in the burst
     {
+        if ( r_go.read() == false )   // soft reset
+        {
+            r_initiator_fsm = M_IDLE;
+            break;
+        }
+
         uint32_t nwords;
         uint32_t offset = r_burst_offset.read();
@@ -584,5 +597,5 @@
         else if(r_initiator_fsm == M_WRITE_ERROR)   p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR;
         else                                        p_vci_target.rdata = BLOCK_DEVICE_BUSY;
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_BUFFER:
@@ -590,5 +603,5 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = (uint32_t)r_buf_address.read();
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_BUFFER_EXT:
@@ -596,5 +609,5 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = (uint32_t)(r_buf_address.read()>>32);
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_COUNT:
@@ -602,5 +615,5 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = r_nblocks.read();
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_LBA:
@@ -608,5 +621,5 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = r_lba.read();
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_IRQEN:
@@ -614,5 +627,5 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = r_irq_enable.read();
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_SIZE:
@@ -620,5 +633,5 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = m_device_size;
-        p_vci_target.rerror = VCI_READ_OK;
+        p_vci_target.rerror = 0;
         break;
     case T_READ_BLOCK:
@@ -626,23 +639,17 @@
         p_vci_target.rspval = true;
         p_vci_target.rdata  = m_words_per_block*4;
-        p_vci_target.rerror = VCI_READ_OK;
-        break;
-    case T_READ_ERROR:
+        p_vci_target.rerror = 0;
+        break;
+    case T_ERROR:
         p_vci_target.cmdack = false;
         p_vci_target.rspval = true;
         p_vci_target.rdata  = 0;
-        p_vci_target.rerror = VCI_READ_ERROR;
-        break;
-    case T_WRITE_ERROR:
+        p_vci_target.rerror = 1;
+        break;
+    default:      // all write
         p_vci_target.cmdack = false;
         p_vci_target.rspval = true;
         p_vci_target.rdata  = 0;
-        p_vci_target.rerror = VCI_WRITE_ERROR;
-        break;
-    default:
-        p_vci_target.cmdack = false;
-        p_vci_target.rspval = true;
-        p_vci_target.rdata  = 0;
-        p_vci_target.rerror = VCI_WRITE_OK;
+        p_vci_target.rerror = 0;
         break;
     } // end switch target fsm
