Changeset 1035 for trunk/modules/vci_mem_cache/caba/source
- Timestamp:
- Feb 23, 2016, 6:29:28 PM (9 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
-
include/vci_mem_cache.h (modified) (1 diff)
-
src/vci_mem_cache.cpp (modified) (44 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r917 r1035 979 979 980 980 sc_signal<int> r_alloc_trt_fsm; 981 sc_signal<int> r_alloc_trt_last; 981 982 982 983 //////////////////////////////////////////////////// -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r1021 r1035 465 465 r_alloc_dir_reset_cpt("r_alloc_dir_reset_cpt"), 466 466 r_alloc_trt_fsm("r_alloc_trt_fsm"), 467 r_alloc_trt_last("r_alloc_trt_last"), 467 468 r_alloc_upt_fsm("r_alloc_upt_fsm"), 468 469 r_alloc_ivt_fsm("r_alloc_ivt_fsm"), … … 690 691 } 691 692 692 ///////////////////////////////////////////////////// 693 //////////////////////////////////////////////////////////////////// 693 694 tmpl(int)::read_instrumentation(uint32_t regr, uint32_t & rdata) 694 ///////////////////////////////////////////////////// 695 //////////////////////////////////////////////////////////////////// 695 696 { 696 697 int error = 0; … … 1019 1020 r_alloc_heap_fsm = ALLOC_HEAP_RESET; 1020 1021 r_alloc_trt_fsm = ALLOC_TRT_READ; 1022 r_alloc_trt_last = ALLOC_TRT_READ; 1021 1023 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 1022 1024 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; … … 2965 2967 if (m_debug) 2966 2968 { 2967 std::cout << " <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:" 2968 << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() 2969 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 2970 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 2969 std::cout << " <MEMC " << name() 2970 << " READ_RSP> Request TGT_RSP FSM to return data:" 2971 << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() 2972 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 2973 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() 2974 << std::endl; 2971 2975 } 2972 2976 #endif … … 3031 3035 { 3032 3036 std::cout << " <MEMC " << name() << " READ_TRT_SET> Set a GET in TRT:" 3033 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 3034 << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; 3037 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 3038 << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() 3039 << std::endl; 3035 3040 } 3036 3041 #endif … … 3053 3058 if (m_debug) 3054 3059 { 3055 std::cout << " <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address " 3056 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 3060 std::cout << " <MEMC " << name() 3061 << " READ_TRT_REQ> Request GET transaction for address " 3062 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 3057 3063 } 3058 3064 #endif … … 3144 3150 { 3145 3151 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 3146 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()3147 << " / address = " << std::hex << m_cmd_write_addr_fifo.read()3148 << " / data = " << m_cmd_write_data_fifo.read() << std::endl;3152 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 3153 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 3154 << " / data = " << m_cmd_write_data_fifo.read() << std::endl; 3149 3155 } 3150 3156 #endif … … 3196 3202 { 3197 3203 std::cout << " <MEMC " << name() 3198 << " WRITE_NEXT> Write another word in local buffer" 3199 << std::endl; 3204 << " WRITE_NEXT> Write another word in local buffer" << std::endl; 3200 3205 } 3201 3206 #endif … … 3238 3243 if (m_debug) 3239 3244 { 3240 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock "3241 << std::endl;3245 std::cout << " <MEMC " << name() 3246 << " WRITE_DIR_REQ> Requesting DIR lock " << std::endl; 3242 3247 } 3243 3248 #endif … … 3276 3281 if (m_debug) 3277 3282 { 3278 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: " 3279 << " address = " << std::hex << r_write_address.read() 3280 << " / hit = " << std::dec << entry.valid 3281 << " / count = " << entry.count 3282 << " / is_cnt = " << entry.is_cnt ; 3283 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 3284 { 3285 std::cout << " / SC access" << std::endl; 3286 } 3287 else 3288 { 3289 std::cout << " / SW access" << std::endl; 3290 } 3283 std::cout << " <MEMC " << name() 3284 << " WRITE_DIR_LOCK> Check the directory: " 3285 << " address = " << std::hex << r_write_address.read() 3286 << " / hit = " << std::dec << entry.valid 3287 << " / count = " << entry.count 3288 << " / is_cnt = " << entry.is_cnt; 3289 if ((r_write_pktid.read() & 0x7) == TYPE_SC) std::cout << " / SC access"; 3290 else std::cout << " / SW access"; 3291 std::cout << std::endl; 3291 3292 } 3292 3293 #endif … … 3374 3375 { 3375 3376 std::cout << " <MEMC " << name() 3376 << " WRITE_DIR_HIT> Write into cache / No coherence transaction" << std::endl; 3377 << " WRITE_DIR_HIT> Write into cache / No coherence transaction" 3378 << std::endl; 3377 3379 } 3378 3380 else 3379 3381 { 3380 3382 std::cout << " <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:" 3381 << " is_cnt = " << r_write_is_cnt.read() 3382 << " nb_copies = " << std::dec << r_write_count.read() << std::endl; 3383 if (owner) 3384 { 3385 std::cout << " ... but the first copy is the writer" << std::endl; 3386 } 3383 << " is_cnt = " << r_write_is_cnt.read() 3384 << " nb_copies = " << std::dec << r_write_count.read() << std::endl; 3385 if (owner) std::cout << " ... but the first copy is the writer" << std::endl; 3387 3386 } 3388 3387 } … … 3569 3568 if (m_debug) 3570 3569 { 3571 std::cout << " <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM" 3572 << " / heap_index = " << std::dec << r_write_ptr.read() 3573 << " / srcid = " << std::dec << r_write_copy.read() 3574 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; 3570 std::cout << " <MEMC " << name() 3571 << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM" 3572 << " / heap_index = " << std::dec << r_write_ptr.read() 3573 << " / srcid = " << std::dec << r_write_copy.read() 3574 << " / inst = " << std::dec << r_write_copy_inst.read() 3575 << std::endl; 3575 3576 if (entry.next == r_write_ptr.read()) 3576 {3577 3577 std::cout << " ... and this is the last" << std::endl; 3578 }3579 3578 } 3580 3579 #endif … … 3586 3585 if (m_debug) 3587 3586 { 3588 std::cout << " <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer" 3589 << " / heap_index = " << std::dec << r_write_ptr.read() 3590 << " / srcid = " << std::dec << r_write_copy.read() 3591 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; 3587 std::cout << " <MEMC " << name() 3588 << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer" 3589 << " / heap_index = " << std::dec << r_write_ptr.read() 3590 << " / srcid = " << std::dec << r_write_copy.read() 3591 << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; 3592 3592 if (entry.next == r_write_ptr.read()) 3593 {3594 3593 std::cout << " ... and this is the last" << std::endl; 3595 }3596 3594 } 3597 3595 #endif … … 3724 3722 if (m_debug) 3725 3723 { 3726 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl; 3724 std::cout << " <MEMC " << name() 3725 << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl; 3727 3726 } 3728 3727 #endif … … 3779 3778 if (m_debug) 3780 3779 { 3781 std::cout << " <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl; 3780 std::cout << " <MEMC " << name() 3781 << " WRITE_WAIT> Releases the locks before retry" << std::endl; 3782 3782 } 3783 3783 #endif … … 3816 3816 if (m_debug) 3817 3817 { 3818 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 3818 std::cout << " <MEMC " << name() 3819 << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 3819 3820 } 3820 3821 #endif … … 3845 3846 if (m_debug) 3846 3847 { 3847 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 3848 std::cout << " <MEMC " << name() 3849 << " WRITE_MISS_TRT_DATA> Modify existing entry in TRT" << std::endl; 3848 3850 } 3849 3851 #endif … … 3864 3866 { 3865 3867 std::cout << " <MEMC " << name() 3866 << " WRITE_MISS_XRAM_REQ> Post a GET request to the"3867 << " IXR_CMD FSM"<< std::endl;3868 << " WRITE_MISS_XRAM_REQ> Post a GET request to IXR_CMD FSM" 3869 << std::endl; 3868 3870 } 3869 3871 #endif … … 3887 3889 if (m_debug) 3888 3890 { 3889 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_READ>" 3890 << " Read the cache to complete local buffer" << std::endl; 3891 std::cout << " <MEMC " << name() 3892 << " WRITE_BC_DIR_READ>" << " Read cache to complete local buffer" 3893 << std::endl; 3891 3894 } 3892 3895 #endif … … 3919 3922 (m_cache_data.read(way, set, word) & ~mask); 3920 3923 } 3924 3921 3925 #if DEBUG_MEMC_WRITE 3922 3926 if (m_debug) 3923 3927 { 3924 3928 std::cout << " <MEMC " << name() 3925 << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl;3929 << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl; 3926 3930 } 3927 3931 #endif … … 3952 3956 { 3953 3957 std::cout << " <MEMC " << name() 3954 << " WRITE_BC_TRT_LOCK> Check TRT : wok = " << wok3955 << " / index = " << wok_index << std::endl;3958 << " WRITE_BC_TRT_LOCK> Check TRT : wok = " << wok 3959 << " / index = " << wok_index << std::endl; 3956 3960 } 3957 3961 #endif … … 3988 3992 index); 3989 3993 #if DEBUG_MEMC_WRITE 3994 3990 3995 if (m_debug and wok) 3991 3996 { 3992 std::cout << " <MEMC " << name() << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT" 3993 << " / nb_copies = " << r_write_count.read() << std::endl; 3997 std::cout << " <MEMC " << name() 3998 << " WRITE_BC_IVT_LOCK> Register broadcast inval in IVT" 3999 << " / nb_copies = " << r_write_count.read() << std::endl; 3994 4000 } 3995 4001 #endif … … 4057 4063 if (m_debug) 4058 4064 { 4059 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:" 4060 << " address = " << std::hex << r_write_address.read() << std::endl; 4065 std::cout << " <MEMC " << name() 4066 << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:" 4067 << " address = " << std::hex << r_write_address.read() << std::endl; 4061 4068 } 4062 4069 #endif … … 4088 4095 { 4089 4096 std::cout << " <MEMC " << name() 4090 << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl; 4097 << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" 4098 << std::endl; 4091 4099 } 4092 4100 #endif … … 4108 4116 { 4109 4117 std::cout << " <MEMC " << name() 4110 << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl; 4118 << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" 4119 << std::endl; 4111 4120 } 4112 4121 #endif … … 4206 4215 { 4207 4216 std::cout << " <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access" 4208 << " index = " << std::dec << r_read_to_ixr_cmd_index.read() 4209 << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; 4217 << " index = " << std::dec << r_read_to_ixr_cmd_index.read() 4218 << " / address = " << std::hex << (entry.nline * (m_words << 2)) 4219 << std::endl; 4210 4220 } 4211 4221 #endif … … 4238 4248 { 4239 4249 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access" 4240 << " index = " << std::dec << r_write_to_ixr_cmd_index.read() 4241 << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; 4250 << " index = " << std::dec << r_write_to_ixr_cmd_index.read() 4251 << " / address = " << std::hex << (entry.nline * (m_words << 2)) 4252 << std::endl; 4242 4253 } 4243 4254 #endif … … 4270 4281 { 4271 4282 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access" 4272 << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() 4273 << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; 4283 << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() 4284 << " / address = " << std::hex << (entry.nline * (m_words << 2)) 4285 << std::endl; 4274 4286 } 4275 4287 #endif … … 4297 4309 { 4298 4310 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access" 4299 << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() 4300 << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; 4311 << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() 4312 << " / address = " << std::hex << (entry.nline*(m_words<<2)) 4313 << std::endl; 4301 4314 } 4302 4315 #endif … … 4324 4337 { 4325 4338 std::cout << " <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access" 4326 << " index = " << std::dec << r_config_to_ixr_cmd_index.read() 4327 << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; 4339 << " index = " << std::dec << r_config_to_ixr_cmd_index.read() 4340 << " / address = " << std::hex << (entry.nline*(m_words<<2)) 4341 << std::endl; 4328 4342 } 4329 4343 #endif … … 4344 4358 { 4345 4359 std::cout << " <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex 4346 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; 4360 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) 4361 << std::endl; 4347 4362 } 4348 4363 #endif … … 4616 4631 // of entries in the TRT, that are handled with a round-robin priority... 4617 4632 // 4618 // The FSM takes the lock protecting TRT, and the lock protecting DIR.4633 // The FSM takes first the DIR lock, then the TRT lock. 4619 4634 // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf. 4620 4635 // It selects a cache slot and save the victim line in another local buffer … … 4633 4648 { 4634 4649 /////////////////// 4635 case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) 4650 case XRAM_RSP_IDLE: // scan the XRAM responses 4651 // select a TRT index (round robin) 4636 4652 { 4637 4653 size_t old = r_xram_rsp_trt_index.read(); … … 4660 4676 } 4661 4677 /////////////////////// 4662 case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock 4663 // Copy the TRT entry in a local buffer 4664 { 4665 if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and 4666 (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) 4678 case XRAM_RSP_DIR_LOCK: // Takes the DIR lock 4679 { 4680 if (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) 4681 { 4682 r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; 4683 4684 #if DEBUG_MEMC_XRAM_RSP 4685 if (m_debug) 4686 { 4687 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_LOCK>" 4688 << " Get access to DIR" << std::endl; 4689 } 4690 #endif 4691 } 4692 break; 4693 } 4694 /////////////////////// 4695 case XRAM_RSP_TRT_COPY: // Keep the DIR lock and take the TRT lock 4696 // Copy the TRT entry in a local buffer 4697 // Select a victim cache line and copy it in a local buffer 4698 { 4699 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and 4700 "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); 4701 4702 if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 4667 4703 { 4668 4704 // copy the TRT entry in the r_xram_rsp_trt_buf local buffer 4669 4705 size_t index = r_xram_rsp_trt_index.read(); 4670 4706 r_xram_rsp_trt_buf.copy(m_trt.read(index)); 4671 r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; 4707 4708 // selects & extracts a victim line from cache 4709 size_t way = 0; 4710 size_t set = m_y[(addr_t) (r_xram_rsp_trt_buf.nline * m_words * 4)]; 4711 4712 DirectoryEntry victim(m_cache_directory.select(set, way)); 4713 4714 bool inval = (victim.count and victim.valid) ; 4715 4716 // copy the victim line in a local buffer (both data dir) 4717 m_cache_data.read_line(way, set, r_xram_rsp_victim_data); 4718 4719 r_xram_rsp_victim_copy = victim.owner.srcid; 4720 r_xram_rsp_victim_copy_inst = victim.owner.inst; 4721 r_xram_rsp_victim_count = victim.count; 4722 r_xram_rsp_victim_ptr = victim.ptr; 4723 r_xram_rsp_victim_way = way; 4724 r_xram_rsp_victim_set = set; 4725 r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; 4726 r_xram_rsp_victim_is_cnt = victim.is_cnt; 4727 r_xram_rsp_victim_inval = inval ; 4728 r_xram_rsp_victim_dirty = victim.dirty; 4729 4730 if (not r_xram_rsp_trt_buf.rerror) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; 4731 else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; 4672 4732 4673 4733 #if DEBUG_MEMC_XRAM_RSP 4674 4734 if (m_debug) 4675 4735 { 4676 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_LOCK>" 4677 << " Get access to DIR and TRT" << std::endl; 4678 } 4679 #endif 4680 } 4681 break; 4682 } 4683 /////////////////////// 4684 case XRAM_RSP_TRT_COPY: // Select a victim cache line 4685 // and copy it in a local buffer 4686 { 4687 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and 4688 "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); 4689 4690 assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and 4691 "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation"); 4692 4693 // selects & extracts a victim line from cache 4694 size_t way = 0; 4695 size_t set = m_y[(addr_t) (r_xram_rsp_trt_buf.nline * m_words * 4)]; 4696 4697 DirectoryEntry victim(m_cache_directory.select(set, way)); 4698 4699 bool inval = (victim.count and victim.valid) ; 4700 4701 // copy the victim line in a local buffer (both data dir) 4702 m_cache_data.read_line(way, set, r_xram_rsp_victim_data); 4703 4704 r_xram_rsp_victim_copy = victim.owner.srcid; 4705 r_xram_rsp_victim_copy_inst = victim.owner.inst; 4706 r_xram_rsp_victim_count = victim.count; 4707 r_xram_rsp_victim_ptr = victim.ptr; 4708 r_xram_rsp_victim_way = way; 4709 r_xram_rsp_victim_set = set; 4710 r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; 4711 r_xram_rsp_victim_is_cnt = victim.is_cnt; 4712 r_xram_rsp_victim_inval = inval ; 4713 r_xram_rsp_victim_dirty = victim.dirty; 4714 4715 if (not r_xram_rsp_trt_buf.rerror) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; 4716 else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; 4717 4718 #if DEBUG_MEMC_XRAM_RSP 4719 if (m_debug) 4720 { 4721 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 4722 << " Select a victim slot: " 4723 << " way = " << std::dec << way 4724 << " / set = " << set 4725 << " / inval_required = " << inval << std::endl; 4726 } 4727 #endif 4736 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 4737 << " Select a victim slot: " 4738 << " way = " << std::dec << way 4739 << " / set = " << set 4740 << " / inval_required = " << inval << std::endl; 4741 } 4742 #endif 4743 } 4728 4744 break; 4729 4745 } 4730 4746 /////////////////////// 4731 4747 case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock 4732 // to check a possible pending inval4748 // to check a possible pending inval 4733 4749 { 4734 4750 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and … … 4799 4815 /////////////////////// 4800 4816 case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory), 4801 // erases the TRT entry if victim not dirty,4802 // and set inval request in IVT if required4817 // erases the TRT entry if victim not dirty, 4818 // and set inval request in IVT if required 4803 4819 { 4804 4820 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and … … 7847 7863 ///////////////////// 7848 7864 case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. 7849 // All the WAYS of a SET initialized in parallel7865 // All the WAYS of a SET initialized in parallel 7850 7866 7851 7867 r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); … … 7858 7874 break; 7859 7875 7860 7876 ////////////////////// 7861 7877 case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM 7862 7878 if ((r_config_fsm.read() != CONFIG_DIR_REQ) and … … 7883 7899 break; 7884 7900 7885 7901 //////////////////// 7886 7902 case ALLOC_DIR_READ: // allocated to READ FSM 7887 7903 if (((r_read_fsm.read() != READ_DIR_REQ) and … … 7910 7926 break; 7911 7927 7912 7928 ///////////////////// 7913 7929 case ALLOC_DIR_WRITE: // allocated to WRITE FSM 7914 7930 if (((r_write_fsm.read() != WRITE_DIR_REQ) and … … 7945 7961 break; 7946 7962 7947 7963 /////////////////// 7948 7964 case ALLOC_DIR_CAS: // allocated to CAS FSM 7949 7965 if (((r_cas_fsm.read() != CAS_DIR_REQ) and … … 7981 7997 break; 7982 7998 7983 7999 /////////////////////// 7984 8000 case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM 7985 8001 if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and 7986 7987 7988 8002 (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and 8003 (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and 8004 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) 7989 8005 { 7990 8006 if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) … … 8005 8021 break; 8006 8022 8007 8023 //////////////////////// 8008 8024 case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM 8009 8025 if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and 8010 8011 8026 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 8027 (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) 8012 8028 { 8013 8029 if (r_config_fsm.read() == CONFIG_DIR_REQ) … … 8034 8050 //////////////////////////////////////////////////////////////////////////////////// 8035 8051 // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) 8036 // with a round robin priority between 7 user FSMs : 8037 // The priority is READ > WRITE > CAS > IXR_CMD > XRAM_RSP > IXR_RSP > CONFIG 8038 // The ressource is always allocated. 8052 // to seven FSMs, with a mix of static and round-robin priorities: 8053 // - FSMs that remove TRT entries (IXR_RSP and XRAM_RSP) have highest priority, 8054 // - FSM that read a TRT entry (IXR_CMD) has medium priority, 8055 // - FSMs that add TRT entries (READ , WRITE , CAS , CONFIG) have the lowest 8056 // priority, with a round robin priority between these 4 FSMS, and they get 8057 // access only if the TRT is not full. 8058 // To maximize the throughput, the TRT is always allocated: 8059 // - The r_alloc_trt_fsm register define the current owner. 8060 // - The r_alloc_trt_last register define the previous owner for round robin. 8039 8061 /////////////////////////////////////////////////////////////////////////////////// 8040 8062 8041 //std::cout << std::endl << "alloc_trt_fsm" << std::endl; 8042 8063 size_t index = 0; 8064 8065 bool trt_req_read = (r_read_fsm.read() == READ_TRT_LOCK) and 8066 not m_trt.full(index); 8067 8068 bool trt_req_write = ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8069 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) and 8070 not m_trt.full(index); 8071 8072 bool trt_req_cas = ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8073 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) and 8074 not m_trt.full(index); 8075 8076 bool trt_req_config = (r_config_fsm.read() == CONFIG_TRT_LOCK) and 8077 not m_trt.full(index); 8078 8079 bool trt_req_ixr_cmd = (r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8080 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8081 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8082 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8083 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT); 8084 8085 bool trt_req_ixr_rsp = (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8086 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ); 8087 8088 bool trt_req_xram_rsp = (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY); 8089 8090 bool trt_allocate = false; 8091 8092 // compute allocation condition: 8093 // allocation is done if owner FSM does not use the TRT 8043 8094 switch(r_alloc_trt_fsm.read()) 8044 8095 { 8045 //////////////////// 8046 case ALLOC_TRT_READ: 8047 if (r_read_fsm.read() != READ_TRT_LOCK) 8048 { 8049 if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8050 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8051 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8052 8053 else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8054 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8055 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8056 8057 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8058 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8059 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8060 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8061 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) 8062 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8063 8064 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8065 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8066 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8067 8068 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8069 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8070 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8071 8072 else if (r_config_fsm.read() == CONFIG_TRT_LOCK) 8073 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8074 } 8075 break; 8076 8077 ///////////////////// 8096 case ALLOC_TRT_READ: 8097 if ((r_read_fsm.read() != READ_TRT_LOCK) and 8098 (r_read_fsm.read() != READ_TRT_SET)) 8099 { 8100 r_alloc_trt_last = ALLOC_TRT_READ; 8101 trt_allocate = true; 8102 } 8103 break; 8078 8104 case ALLOC_TRT_WRITE: 8079 if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 8080 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 8081 (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) 8082 { 8083 if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8084 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8085 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8086 8087 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8088 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8089 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8090 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8091 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) 8092 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8093 8094 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8095 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8096 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8097 8098 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8099 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8100 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8101 8102 else if (r_config_fsm.read() == CONFIG_TRT_LOCK) 8103 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8104 8105 else if (r_read_fsm.read() == READ_TRT_LOCK) 8106 r_alloc_trt_fsm = ALLOC_TRT_READ; 8107 } 8108 break; 8109 8110 /////////////////// 8111 case ALLOC_TRT_CAS: 8112 if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 8113 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 8114 (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) 8115 { 8116 if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8117 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8118 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8119 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8120 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) 8121 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8122 8123 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8124 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8125 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8126 8127 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8128 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8129 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8130 8131 else if (r_config_fsm.read() == CONFIG_TRT_LOCK) 8132 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8133 8134 else if (r_read_fsm.read() == READ_TRT_LOCK) 8135 r_alloc_trt_fsm = ALLOC_TRT_READ; 8136 8137 else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8138 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8139 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8140 } 8141 break; 8142 8143 /////////////////////// 8105 if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 8106 (r_write_fsm.read() != WRITE_MISS_TRT_DATA) and 8107 (r_write_fsm.read() != WRITE_MISS_TRT_SET) and 8108 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 8109 (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and 8110 (r_write_fsm.read() != WRITE_BC_DIR_INVAL)) 8111 { 8112 r_alloc_trt_last = ALLOC_TRT_WRITE; 8113 trt_allocate = true; 8114 } 8115 break; 8116 case ALLOC_TRT_CAS: 8117 if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 8118 (r_cas_fsm.read() != CAS_MISS_TRT_SET) and 8119 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 8120 (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and 8121 (r_cas_fsm.read() != CAS_BC_DIR_INVAL)) 8122 { 8123 r_alloc_trt_last = ALLOC_TRT_CAS; 8124 trt_allocate = true; 8125 } 8126 break; 8127 case ALLOC_TRT_CONFIG: 8128 if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and 8129 (r_config_fsm.read() != CONFIG_TRT_SET)) 8130 { 8131 r_alloc_trt_last = ALLOC_TRT_CONFIG; 8132 trt_allocate = true; 8133 } 8134 break; 8144 8135 case ALLOC_TRT_IXR_CMD: 8145 if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and 8146 (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and 8147 (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and 8148 (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and 8149 (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) 8150 { 8151 if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8152 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8153 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8154 8155 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8156 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8157 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8158 8159 else if (r_config_fsm.read() == CONFIG_TRT_LOCK) 8160 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8161 8162 else if (r_read_fsm.read() == READ_TRT_LOCK) 8163 r_alloc_trt_fsm = ALLOC_TRT_READ; 8164 8165 else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8166 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8167 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8168 8169 else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8170 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8171 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8172 } 8173 break; 8174 8175 //////////////////////// 8136 if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and 8137 (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and 8138 (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and 8139 (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and 8140 (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) 8141 { 8142 trt_allocate = true; 8143 } 8144 break; 8176 8145 case ALLOC_TRT_XRAM_RSP: 8177 if (((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or 8178 (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and 8179 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 8180 (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and 8181 (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) 8182 { 8183 if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8184 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8185 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8186 8187 else if (r_config_fsm.read() == CONFIG_TRT_LOCK) 8188 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8189 8190 else if (r_read_fsm.read() == READ_TRT_LOCK) 8191 r_alloc_trt_fsm = ALLOC_TRT_READ; 8192 8193 else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8194 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8195 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8196 8197 else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8198 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8199 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8200 8201 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8202 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8203 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8204 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8205 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) 8206 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8207 8208 } 8209 break; 8210 8211 /////////////////////// 8146 if ((r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 8147 (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) and 8148 (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and 8149 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_DIRTY)) 8150 { 8151 trt_allocate = true; 8152 } 8153 break; 8212 8154 case ALLOC_TRT_IXR_RSP: 8213 if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and 8214 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 8215 { 8216 if (r_config_fsm.read() == CONFIG_TRT_LOCK) 8217 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8218 8219 else if (r_read_fsm.read() == READ_TRT_LOCK) 8220 r_alloc_trt_fsm = ALLOC_TRT_READ; 8221 8222 else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8223 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8224 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8225 8226 else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8227 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8228 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8229 8230 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8231 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8232 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8233 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8234 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) 8235 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8236 8237 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8238 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8239 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8240 } 8241 break; 8242 8243 ////////////////////// 8244 case ALLOC_TRT_CONFIG: 8245 if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and 8246 (r_config_fsm.read() != CONFIG_TRT_SET)) 8247 { 8248 if (r_read_fsm.read() == READ_TRT_LOCK) 8249 r_alloc_trt_fsm = ALLOC_TRT_READ; 8250 8251 else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8252 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8253 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8254 8255 else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8256 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8257 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8258 8259 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8260 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8261 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8262 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8263 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) 8264 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8265 8266 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 8267 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8268 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8269 8270 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8271 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8272 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8273 } 8274 break; 8275 8276 } // end switch alloc_trt_fsm 8155 if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and 8156 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 8157 { 8158 trt_allocate = true; 8159 } 8160 } // end switch on r_alloc_trt_fsm 8161 8162 // allocate if required 8163 if ( trt_allocate ) 8164 { 8165 // static priorities for XRAM_RSP > IXR_RSP > IXR_CMD 8166 if ( trt_req_xram_rsp ) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8167 else if ( trt_req_ixr_rsp ) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 8168 else if ( trt_req_ixr_cmd ) r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 8169 8170 // round robin priorities for READ / WRITE / CAS / CONFIG 8171 else if ( r_alloc_trt_last.read() == ALLOC_TRT_READ ) 8172 { 8173 if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8174 else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; 8175 else if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8176 else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; 8177 } 8178 else if ( r_alloc_trt_last.read() == ALLOC_TRT_WRITE ) 8179 { 8180 if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; 8181 else if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8182 else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; 8183 else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8184 } 8185 else if ( r_alloc_trt_last.read() == ALLOC_TRT_CAS ) 8186 { 8187 if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8188 else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; 8189 else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8190 else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; 8191 } 8192 else if ( r_alloc_trt_last.read() == ALLOC_TRT_CONFIG ) 8193 { 8194 if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; 8195 else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8196 else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; 8197 else if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 8198 } 8199 } // end if trt_allocate 8200 8277 8201 8278 8202 //////////////////////////////////////////////////////////////////////////////////// … … 8576 8500 ///////////////////////////// 8577 8501 tmpl(void)::genMoore() 8578 8502 ///////////////////////////// 8579 8503 { 8580 8504 #if MONITOR_MEMCACHE_FSM == 1
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