Index: /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 1034) +++ /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 1035) @@ -979,4 +979,5 @@ sc_signal r_alloc_trt_fsm; + sc_signal r_alloc_trt_last; //////////////////////////////////////////////////// Index: /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 1034) +++ /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 1035) @@ -465,4 +465,5 @@ r_alloc_dir_reset_cpt("r_alloc_dir_reset_cpt"), r_alloc_trt_fsm("r_alloc_trt_fsm"), + r_alloc_trt_last("r_alloc_trt_last"), r_alloc_upt_fsm("r_alloc_upt_fsm"), r_alloc_ivt_fsm("r_alloc_ivt_fsm"), @@ -690,7 +691,7 @@ } - ///////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////// tmpl(int)::read_instrumentation(uint32_t regr, uint32_t & rdata) - ///////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////// { int error = 0; @@ -1019,4 +1020,5 @@ r_alloc_heap_fsm = ALLOC_HEAP_RESET; r_alloc_trt_fsm = ALLOC_TRT_READ; + r_alloc_trt_last = ALLOC_TRT_READ; r_alloc_upt_fsm = ALLOC_UPT_WRITE; r_alloc_ivt_fsm = ALLOC_IVT_WRITE; @@ -2965,8 +2967,10 @@ if (m_debug) { - std::cout << " Request TGT_RSP FSM to return data:" - << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + std::cout << " Request TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() + << std::endl; } #endif @@ -3031,6 +3035,7 @@ { std::cout << " Set a GET in TRT:" - << " address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() + << std::endl; } #endif @@ -3053,6 +3058,7 @@ if (m_debug) { - std::cout << " Request GET transaction for address " - << std::hex << m_cmd_read_addr_fifo.read() << std::endl; + std::cout << " Request GET transaction for address " + << std::hex << m_cmd_read_addr_fifo.read() << std::endl; } #endif @@ -3144,7 +3150,7 @@ { std::cout << " Write request " - << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; } #endif @@ -3196,6 +3202,5 @@ { std::cout << " Write another word in local buffer" - << std::endl; + << " WRITE_NEXT> Write another word in local buffer" << std::endl; } #endif @@ -3238,6 +3243,6 @@ if (m_debug) { - std::cout << " Requesting DIR lock " - << std::endl; + std::cout << " Requesting DIR lock " << std::endl; } #endif @@ -3276,17 +3281,13 @@ if (m_debug) { - std::cout << " Check the directory: " - << " address = " << std::hex << r_write_address.read() - << " / hit = " << std::dec << entry.valid - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt ; - if ((r_write_pktid.read() & 0x7) == TYPE_SC) - { - std::cout << " / SC access" << std::endl; - } - else - { - std::cout << " / SW access" << std::endl; - } + std::cout << " Check the directory: " + << " address = " << std::hex << r_write_address.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt; + if ((r_write_pktid.read() & 0x7) == TYPE_SC) std::cout << " / SC access"; + else std::cout << " / SW access"; + std::cout << std::endl; } #endif @@ -3374,15 +3375,13 @@ { std::cout << " Write into cache / No coherence transaction" << std::endl; + << " WRITE_DIR_HIT> Write into cache / No coherence transaction" + << std::endl; } else { std::cout << " Coherence update required:" - << " is_cnt = " << r_write_is_cnt.read() - << " nb_copies = " << std::dec << r_write_count.read() << std::endl; - if (owner) - { - std::cout << " ... but the first copy is the writer" << std::endl; - } + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if (owner) std::cout << " ... but the first copy is the writer" << std::endl; } } @@ -3569,12 +3568,12 @@ if (m_debug) { - std::cout << " Post another request to CC_SEND FSM" - << " / heap_index = " << std::dec << r_write_ptr.read() - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + std::cout << " Post another request to CC_SEND FSM" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() + << std::endl; if (entry.next == r_write_ptr.read()) - { std::cout << " ... and this is the last" << std::endl; - } } #endif @@ -3586,12 +3585,11 @@ if (m_debug) { - std::cout << " Skip one entry in heap matching the writer" - << " / heap_index = " << std::dec << r_write_ptr.read() - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + std::cout << " Skip one entry in heap matching the writer" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; if (entry.next == r_write_ptr.read()) - { std::cout << " ... and this is the last" << std::endl; - } } #endif @@ -3724,5 +3722,6 @@ if (m_debug) { - std::cout << " Check the TRT" << std::endl; + std::cout << " Check the TRT" << std::endl; } #endif @@ -3779,5 +3778,6 @@ if (m_debug) { - std::cout << " Releases the locks before retry" << std::endl; + std::cout << " Releases the locks before retry" << std::endl; } #endif @@ -3816,5 +3816,6 @@ if (m_debug) { - std::cout << " Set a new entry in TRT" << std::endl; + std::cout << " Set a new entry in TRT" << std::endl; } #endif @@ -3845,5 +3846,6 @@ if (m_debug) { - std::cout << " Modify an existing entry in TRT" << std::endl; + std::cout << " Modify existing entry in TRT" << std::endl; } #endif @@ -3864,6 +3866,6 @@ { std::cout << " Post a GET request to the" - << " IXR_CMD FSM" << std::endl; + << " WRITE_MISS_XRAM_REQ> Post a GET request to IXR_CMD FSM" + << std::endl; } #endif @@ -3887,6 +3889,7 @@ if (m_debug) { - std::cout << " " - << " Read the cache to complete local buffer" << std::endl; + std::cout << " " << " Read cache to complete local buffer" + << std::endl; } #endif @@ -3919,9 +3922,10 @@ (m_cache_data.read(way, set, word) & ~mask); } + #if DEBUG_MEMC_WRITE if (m_debug) { std::cout << " Complete data buffer" << std::endl; + << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl; } #endif @@ -3952,6 +3956,6 @@ { std::cout << " Check TRT : wok = " << wok - << " / index = " << wok_index << std::endl; + << " WRITE_BC_TRT_LOCK> Check TRT : wok = " << wok + << " / index = " << wok_index << std::endl; } #endif @@ -3988,8 +3992,10 @@ index); #if DEBUG_MEMC_WRITE + if (m_debug and wok) { - std::cout << " Register broadcast inval in IVT" - << " / nb_copies = " << r_write_count.read() << std::endl; + std::cout << " Register broadcast inval in IVT" + << " / nb_copies = " << r_write_count.read() << std::endl; } #endif @@ -4057,6 +4063,7 @@ if (m_debug) { - std::cout << " Inval DIR and register in TRT:" - << " address = " << std::hex << r_write_address.read() << std::endl; + std::cout << " Inval DIR and register in TRT:" + << " address = " << std::hex << r_write_address.read() << std::endl; } #endif @@ -4088,5 +4095,6 @@ { std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; + << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" + << std::endl; } #endif @@ -4108,5 +4116,6 @@ { std::cout << " Post a put request to IXR_CMD FSM" << std::endl; + << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" + << std::endl; } #endif @@ -4206,6 +4215,7 @@ { std::cout << " TRT access" - << " index = " << std::dec << r_read_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; + << " index = " << std::dec << r_read_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline * (m_words << 2)) + << std::endl; } #endif @@ -4238,6 +4248,7 @@ { std::cout << " TRT access" - << " index = " << std::dec << r_write_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; + << " index = " << std::dec << r_write_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline * (m_words << 2)) + << std::endl; } #endif @@ -4270,6 +4281,7 @@ { std::cout << " TRT access" - << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; + << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline * (m_words << 2)) + << std::endl; } #endif @@ -4297,6 +4309,7 @@ { std::cout << " TRT access" - << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; + << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) + << std::endl; } #endif @@ -4324,6 +4337,7 @@ { std::cout << " TRT access" - << " index = " << std::dec << r_config_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; + << " index = " << std::dec << r_config_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) + << std::endl; } #endif @@ -4344,5 +4358,6 @@ { std::cout << " GET request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) + << std::endl; } #endif @@ -4616,5 +4631,5 @@ // of entries in the TRT, that are handled with a round-robin priority... // - // The FSM takes the lock protecting TRT, and the lock protecting DIR. + // The FSM takes first the DIR lock, then the TRT lock. // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf. // It selects a cache slot and save the victim line in another local buffer @@ -4633,5 +4648,6 @@ { /////////////////// - case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) + case XRAM_RSP_IDLE: // scan the XRAM responses + // select a TRT index (round robin) { size_t old = r_xram_rsp_trt_index.read(); @@ -4660,75 +4676,75 @@ } /////////////////////// - case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock - // Copy the TRT entry in a local buffer - { - if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and - (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) + case XRAM_RSP_DIR_LOCK: // Takes the DIR lock + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) + { + r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Get access to DIR" << std::endl; + } +#endif + } + break; + } + /////////////////////// + case XRAM_RSP_TRT_COPY: // Keep the DIR lock and take the TRT lock + // Copy the TRT entry in a local buffer + // Select a victim cache line and copy it in a local buffer + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); + + if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) { // copy the TRT entry in the r_xram_rsp_trt_buf local buffer size_t index = r_xram_rsp_trt_index.read(); r_xram_rsp_trt_buf.copy(m_trt.read(index)); - r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; + + // selects & extracts a victim line from cache + size_t way = 0; + size_t set = m_y[(addr_t) (r_xram_rsp_trt_buf.nline * m_words * 4)]; + + DirectoryEntry victim(m_cache_directory.select(set, way)); + + bool inval = (victim.count and victim.valid) ; + + // copy the victim line in a local buffer (both data dir) + m_cache_data.read_line(way, set, r_xram_rsp_victim_data); + + r_xram_rsp_victim_copy = victim.owner.srcid; + r_xram_rsp_victim_copy_inst = victim.owner.inst; + r_xram_rsp_victim_count = victim.count; + r_xram_rsp_victim_ptr = victim.ptr; + r_xram_rsp_victim_way = way; + r_xram_rsp_victim_set = set; + r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; + r_xram_rsp_victim_is_cnt = victim.is_cnt; + r_xram_rsp_victim_inval = inval ; + r_xram_rsp_victim_dirty = victim.dirty; + + if (not r_xram_rsp_trt_buf.rerror) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; + else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; #if DEBUG_MEMC_XRAM_RSP if (m_debug) { - std::cout << " " - << " Get access to DIR and TRT" << std::endl; - } -#endif - } - break; - } - /////////////////////// - case XRAM_RSP_TRT_COPY: // Select a victim cache line - // and copy it in a local buffer - { - assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); - - assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation"); - - // selects & extracts a victim line from cache - size_t way = 0; - size_t set = m_y[(addr_t) (r_xram_rsp_trt_buf.nline * m_words * 4)]; - - DirectoryEntry victim(m_cache_directory.select(set, way)); - - bool inval = (victim.count and victim.valid) ; - - // copy the victim line in a local buffer (both data dir) - m_cache_data.read_line(way, set, r_xram_rsp_victim_data); - - r_xram_rsp_victim_copy = victim.owner.srcid; - r_xram_rsp_victim_copy_inst = victim.owner.inst; - r_xram_rsp_victim_count = victim.count; - r_xram_rsp_victim_ptr = victim.ptr; - r_xram_rsp_victim_way = way; - r_xram_rsp_victim_set = set; - r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; - r_xram_rsp_victim_is_cnt = victim.is_cnt; - r_xram_rsp_victim_inval = inval ; - r_xram_rsp_victim_dirty = victim.dirty; - - if (not r_xram_rsp_trt_buf.rerror) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; - else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - { - std::cout << " " - << " Select a victim slot: " - << " way = " << std::dec << way - << " / set = " << set - << " / inval_required = " << inval << std::endl; - } -#endif + std::cout << " " + << " Select a victim slot: " + << " way = " << std::dec << way + << " / set = " << set + << " / inval_required = " << inval << std::endl; + } +#endif + } break; } /////////////////////// case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock - // to check a possible pending inval + // to check a possible pending inval { assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and @@ -4799,6 +4815,6 @@ /////////////////////// case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory), - // erases the TRT entry if victim not dirty, - // and set inval request in IVT if required + // erases the TRT entry if victim not dirty, + // and set inval request in IVT if required { assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and @@ -7847,5 +7863,5 @@ ///////////////////// case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. - // All the WAYS of a SET initialized in parallel + // All the WAYS of a SET initialized in parallel r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); @@ -7858,5 +7874,5 @@ break; - ////////////////////// + ////////////////////// case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM if ((r_config_fsm.read() != CONFIG_DIR_REQ) and @@ -7883,5 +7899,5 @@ break; - //////////////////// + //////////////////// case ALLOC_DIR_READ: // allocated to READ FSM if (((r_read_fsm.read() != READ_DIR_REQ) and @@ -7910,5 +7926,5 @@ break; - ///////////////////// + ///////////////////// case ALLOC_DIR_WRITE: // allocated to WRITE FSM if (((r_write_fsm.read() != WRITE_DIR_REQ) and @@ -7945,5 +7961,5 @@ break; - /////////////////// + /////////////////// case ALLOC_DIR_CAS: // allocated to CAS FSM if (((r_cas_fsm.read() != CAS_DIR_REQ) and @@ -7981,10 +7997,10 @@ break; - /////////////////////// + /////////////////////// case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and - (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and - (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and - (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) + (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) { if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) @@ -8005,9 +8021,9 @@ break; - //////////////////////// + //////////////////////// case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and - (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and - (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) { if (r_config_fsm.read() == CONFIG_DIR_REQ) @@ -8034,245 +8050,153 @@ //////////////////////////////////////////////////////////////////////////////////// // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) - // with a round robin priority between 7 user FSMs : - // The priority is READ > WRITE > CAS > IXR_CMD > XRAM_RSP > IXR_RSP > CONFIG - // The ressource is always allocated. + // to seven FSMs, with a mix of static and round-robin priorities: + // - FSMs that remove TRT entries (IXR_RSP and XRAM_RSP) have highest priority, + // - FSM that read a TRT entry (IXR_CMD) has medium priority, + // - FSMs that add TRT entries (READ , WRITE , CAS , CONFIG) have the lowest + // priority, with a round robin priority between these 4 FSMS, and they get + // access only if the TRT is not full. + // To maximize the throughput, the TRT is always allocated: + // - The r_alloc_trt_fsm register define the current owner. + // - The r_alloc_trt_last register define the previous owner for round robin. /////////////////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "alloc_trt_fsm" << std::endl; - + size_t index = 0; + + bool trt_req_read = (r_read_fsm.read() == READ_TRT_LOCK) and + not m_trt.full(index); + + bool trt_req_write = ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) and + not m_trt.full(index); + + bool trt_req_cas = ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) and + not m_trt.full(index); + + bool trt_req_config = (r_config_fsm.read() == CONFIG_TRT_LOCK) and + not m_trt.full(index); + + bool trt_req_ixr_cmd = (r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT); + + bool trt_req_ixr_rsp = (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ); + + bool trt_req_xram_rsp = (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY); + + bool trt_allocate = false; + + // compute allocation condition: + // allocation is done if owner FSM does not use the TRT switch(r_alloc_trt_fsm.read()) { - //////////////////// - case ALLOC_TRT_READ: - if (r_read_fsm.read() != READ_TRT_LOCK) - { - if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; - - else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if (r_config_fsm.read() == CONFIG_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - } - break; - - ///////////////////// + case ALLOC_TRT_READ: + if ((r_read_fsm.read() != READ_TRT_LOCK) and + (r_read_fsm.read() != READ_TRT_SET)) + { + r_alloc_trt_last = ALLOC_TRT_READ; + trt_allocate = true; + } + break; case ALLOC_TRT_WRITE: - if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) - { - if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; - - else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if (r_config_fsm.read() == CONFIG_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - - else if (r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - } - break; - - /////////////////// - case ALLOC_TRT_CAS: - if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) - { - if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; - - else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if (r_config_fsm.read() == CONFIG_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - - else if (r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - } - break; - - /////////////////////// + if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_MISS_TRT_DATA) and + (r_write_fsm.read() != WRITE_MISS_TRT_SET) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and + (r_write_fsm.read() != WRITE_BC_DIR_INVAL)) + { + r_alloc_trt_last = ALLOC_TRT_WRITE; + trt_allocate = true; + } + break; + case ALLOC_TRT_CAS: + if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_MISS_TRT_SET) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and + (r_cas_fsm.read() != CAS_BC_DIR_INVAL)) + { + r_alloc_trt_last = ALLOC_TRT_CAS; + trt_allocate = true; + } + break; + case ALLOC_TRT_CONFIG: + if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET)) + { + r_alloc_trt_last = ALLOC_TRT_CONFIG; + trt_allocate = true; + } + break; case ALLOC_TRT_IXR_CMD: - if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and - (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and - (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and - (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and - (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) - { - if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if (r_config_fsm.read() == CONFIG_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - - else if (r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - } - break; - - //////////////////////// + if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) + { + trt_allocate = true; + } + break; case ALLOC_TRT_XRAM_RSP: - if (((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or - (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and - (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and - (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and - (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) - { - if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - - else if (r_config_fsm.read() == CONFIG_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - - else if (r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; - - } - break; - - /////////////////////// + if ((r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) and + (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_DIRTY)) + { + trt_allocate = true; + } + break; case ALLOC_TRT_IXR_RSP: - if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and - (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) - { - if (r_config_fsm.read() == CONFIG_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_CONFIG; - - else if (r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; - - else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - } - break; - - ////////////////////// - case ALLOC_TRT_CONFIG: - if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and - (r_config_fsm.read() != CONFIG_TRT_SET)) - { - if (r_read_fsm.read() == READ_TRT_LOCK) - r_alloc_trt_fsm = ALLOC_TRT_READ; - - else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_WRITE; - - else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or - (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) - r_alloc_trt_fsm = ALLOC_TRT_CAS; - - else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or - (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; - - else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and - (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) - r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; - - else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) - r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - } - break; - - } // end switch alloc_trt_fsm + if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and + (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) + { + trt_allocate = true; + } + } // end switch on r_alloc_trt_fsm + + // allocate if required + if ( trt_allocate ) + { + // static priorities for XRAM_RSP > IXR_RSP > IXR_CMD + if ( trt_req_xram_rsp ) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + else if ( trt_req_ixr_rsp ) r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + else if ( trt_req_ixr_cmd ) r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + // round robin priorities for READ / WRITE / CAS / CONFIG + else if ( r_alloc_trt_last.read() == ALLOC_TRT_READ ) + { + if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; + else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; + else if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; + } + else if ( r_alloc_trt_last.read() == ALLOC_TRT_WRITE ) + { + if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; + else if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; + else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; + } + else if ( r_alloc_trt_last.read() == ALLOC_TRT_CAS ) + { + if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; + else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; + else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; + } + else if ( r_alloc_trt_last.read() == ALLOC_TRT_CONFIG ) + { + if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; + else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; + else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; + else if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + } + } // end if trt_allocate + //////////////////////////////////////////////////////////////////////////////////// @@ -8576,5 +8500,5 @@ ///////////////////////////// tmpl(void)::genMoore() - ///////////////////////////// + ///////////////////////////// { #if MONITOR_MEMCACHE_FSM == 1