- Timestamp:
- Mar 1, 2016, 6:01:20 PM (9 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
-
include/vci_mem_cache.h (modified) (1 diff)
-
src/vci_mem_cache.cpp (modified) (95 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r1035 r1036 972 972 973 973 sc_signal<int> r_alloc_dir_fsm; 974 sc_signal<int> r_alloc_dir_last; 974 975 sc_signal<unsigned> r_alloc_dir_reset_cpt; 975 976 -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r1035 r1036 1018 1018 r_cleanup_fsm = CLEANUP_IDLE; 1019 1019 r_alloc_dir_fsm = ALLOC_DIR_RESET; 1020 r_alloc_dir_last = ALLOC_DIR_READ; 1020 1021 r_alloc_heap_fsm = ALLOC_HEAP_RESET; 1021 1022 r_alloc_trt_fsm = ALLOC_TRT_READ; … … 2464 2465 case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM 2465 2466 { 2467 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) and 2468 "MEMC ERROR in CONFIG_HEAP_SCAN state: bad HEAP allocation"); 2469 2466 2470 HeapEntry entry = m_heap.read(r_config_heap_next.read()); 2467 2471 bool last_copy = (entry.next == r_config_heap_next.read()); … … 2473 2477 2474 2478 assert ( (m_config_to_cc_send_inst_fifo.wok()) and 2475 "MEMC ERROR in CONFIG_HEAP_SCAN: The m_config_to_cc_send fifo should neveroverflow");2479 "MEMC ERROR in CONFIG_HEAP_SCAN: The m_config_to_cc_send fifo overflow"); 2476 2480 2477 2481 r_config_heap_next = entry.next; … … 2502 2506 case CONFIG_HEAP_LAST: // HEAP housekeeping 2503 2507 { 2508 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) and 2509 "MEMC ERROR in CONFIG_HEAP_LAST state: bad HEAP allocation"); 2510 2504 2511 size_t free_pointer = m_heap.next_free_ptr(); 2505 2512 HeapEntry last_entry; … … 2570 2577 { 2571 2578 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 2572 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() 2573 << " / srcid = " << m_cmd_read_srcid_fifo.read() 2574 << " / trdid = " << m_cmd_read_trdid_fifo.read() 2575 << " / pktid = " << m_cmd_read_pktid_fifo.read() 2576 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 2579 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() 2580 << " / srcid = " << m_cmd_read_srcid_fifo.read() 2581 << " / trdid = " << m_cmd_read_trdid_fifo.read() 2582 << " / pktid = " << m_cmd_read_pktid_fifo.read() 2583 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() 2584 << std::endl; 2577 2585 } 2578 2586 #endif … … 2592 2600 if (m_debug) 2593 2601 { 2594 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 2602 std::cout << " <MEMC " << name() 2603 << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 2595 2604 } 2596 2605 #endif … … 2647 2656 { 2648 2657 std::cout << " <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: " 2649 << " address = " << std::hex << m_cmd_read_addr_fifo.read()2650 << " / hit = " << std::dec << entry.valid2651 << " / count = " <<std::dec << entry.count2652 << " / is_cnt = " << entry.is_cnt;2658 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 2659 << " / hit = " << std::dec << entry.valid 2660 << " / count = " <<std::dec << entry.count 2661 << " / is_cnt = " << entry.is_cnt; 2653 2662 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) 2654 2663 { … … 2665 2674 ////////////////// 2666 2675 case READ_DIR_HIT: // read data in cache & update the directory 2667 // we enter this state in 3 cases:2668 // - the read request is uncachable2669 // - the cache line is in counter mode2670 // - the cache line is valid but not replicated2676 // we enter this state in 3 cases: 2677 // - the read request is uncachable 2678 // - the cache line is in counter mode 2679 // - the cache line is valid but not replicated 2671 2680 { 2672 2681 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and … … 2724 2733 { 2725 2734 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 2726 << " addr = " << std::hex << m_cmd_read_addr_fifo.read()2727 << " / set = " << std::dec << set2728 << " / way = " << way2729 << " / owner_id = " << std::hex << entry.owner.srcid2730 << " / owner_ins = " << std::dec << entry.owner.inst2731 << " / count = " << entry.count2732 << " / is_cnt = " << entry.is_cnt << std::endl;2735 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 2736 << " / set = " << std::dec << set 2737 << " / way = " << way 2738 << " / owner_id = " << std::hex << entry.owner.srcid 2739 << " / owner_ins = " << std::dec << entry.owner.inst 2740 << " / count = " << entry.count 2741 << " / is_cnt = " << entry.is_cnt << std::endl; 2733 2742 } 2734 2743 #endif … … 2740 2749 case READ_HEAP_REQ: // Get the lock to the HEAP directory 2741 2750 { 2751 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and 2752 "MEMC ERROR in READ_HEAP_REQ state: Bad DIR allocation"); 2753 2742 2754 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 2743 2755 { … … 2749 2761 { 2750 2762 std::cout << " <MEMC " << name() << " READ_HEAP_REQ>" 2751 << " Requesting HEAP lock " << std::endl;2763 << " Requesting HEAP lock " << std::endl; 2752 2764 } 2753 2765 #endif … … 2757 2769 //////////////////// 2758 2770 case READ_HEAP_LOCK: // read data in cache, update the directory 2759 // and prepare the HEAP update 2760 { 2761 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 2762 { 2763 // enter counter mode when we reach the limit of copies or the heap is full 2764 bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); 2765 2766 // read data in the cache 2767 size_t set = m_y[(addr_t) (m_cmd_read_addr_fifo.read())]; 2768 size_t way = r_read_way.read(); 2769 2770 m_cache_data.read_line(way, set, r_read_data); 2771 2772 // update the cache directory 2773 DirectoryEntry entry; 2774 entry.valid = true; 2775 entry.is_cnt = go_cnt; 2776 entry.dirty = r_read_dirty.read(); 2777 entry.tag = r_read_tag.read(); 2778 entry.lock = r_read_lock.read(); 2779 entry.count = r_read_count.read() + 1; 2780 2781 if (not go_cnt) // Not entering counter mode 2782 { 2783 entry.owner.srcid = r_read_copy.read(); 2784 entry.owner.inst = r_read_copy_inst.read(); 2785 entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap 2786 } 2787 else // Entering Counter mode 2788 { 2789 entry.owner.srcid = 0; 2790 entry.owner.inst = false; 2791 entry.ptr = 0; 2792 } 2793 2794 m_cache_directory.write(set, way, entry); 2795 2796 // prepare the heap update (add an entry, or clear the linked list) 2797 if (not go_cnt) // not switching to counter mode 2798 { 2799 // We test if the next free entry in the heap is the last 2800 HeapEntry heap_entry = m_heap.next_free_entry(); 2801 r_read_next_ptr = heap_entry.next; 2802 r_read_last_free = (heap_entry.next == m_heap.next_free_ptr()); 2803 2804 r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP 2805 } 2806 else // switching to counter mode 2807 { 2808 if (r_read_count.read() > 1) // heap must be cleared 2771 // and prepare the HEAP update 2772 { 2773 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and 2774 "MEMC ERROR in READ_HEAP_LOCK state: Bad DIR allocation"); 2775 2776 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) and 2777 "MEMC ERROR in READ_HEAP_LOCK state: Bad HEAP allocation"); 2778 2779 // enter counter mode when we reach the limit of copies or the heap is full 2780 bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); 2781 2782 // read data in the cache 2783 size_t set = m_y[(addr_t) (m_cmd_read_addr_fifo.read())]; 2784 size_t way = r_read_way.read(); 2785 2786 m_cache_data.read_line(way, set, r_read_data); 2787 2788 // update the cache directory 2789 DirectoryEntry entry; 2790 entry.valid = true; 2791 entry.is_cnt = go_cnt; 2792 entry.dirty = r_read_dirty.read(); 2793 entry.tag = r_read_tag.read(); 2794 entry.lock = r_read_lock.read(); 2795 entry.count = r_read_count.read() + 1; 2796 2797 if (not go_cnt) // Not entering counter mode 2798 { 2799 entry.owner.srcid = r_read_copy.read(); 2800 entry.owner.inst = r_read_copy_inst.read(); 2801 entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap 2802 } 2803 else // Entering Counter mode 2804 { 2805 entry.owner.srcid = 0; 2806 entry.owner.inst = false; 2807 entry.ptr = 0; 2808 } 2809 2810 m_cache_directory.write(set, way, entry); 2811 2812 // prepare the heap update (add an entry, or clear the linked list) 2813 if (not go_cnt) // not switching to counter mode 2814 { 2815 // We test if the next free entry in the heap is the last 2816 HeapEntry heap_entry = m_heap.next_free_entry(); 2817 r_read_next_ptr = heap_entry.next; 2818 r_read_last_free = (heap_entry.next == m_heap.next_free_ptr()); 2819 2820 r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP 2821 } 2822 else // switching to counter mode 2823 { 2824 if (r_read_count.read() > 1) // heap must be cleared 2825 { 2826 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); 2827 r_read_next_ptr = m_heap.next_free_ptr(); 2828 m_heap.write_free_ptr(r_read_ptr.read()); 2829 2830 if (next_entry.next == r_read_ptr.read()) // last entry 2809 2831 { 2810 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); 2811 r_read_next_ptr = m_heap.next_free_ptr(); 2812 m_heap.write_free_ptr(r_read_ptr.read()); 2813 2814 if (next_entry.next == r_read_ptr.read()) // last entry 2815 { 2816 r_read_fsm = READ_HEAP_LAST; // erase the entry 2817 } 2818 else // not the last entry 2819 { 2820 r_read_ptr = next_entry.next; 2821 r_read_fsm = READ_HEAP_ERASE; // erase the list 2822 } 2832 r_read_fsm = READ_HEAP_LAST; // erase the entry 2823 2833 } 2824 else // the heap is not used / nothing to do2834 else // not the last entry 2825 2835 { 2826 r_read_fsm = READ_RSP; 2836 r_read_ptr = next_entry.next; 2837 r_read_fsm = READ_HEAP_ERASE; // erase the list 2827 2838 } 2828 2839 } 2840 else // the heap is not used / nothing to do 2841 { 2842 r_read_fsm = READ_RSP; 2843 } 2844 } 2829 2845 2830 2846 #if DEBUG_MEMC_READ 2831 if (m_debug) 2832 { 2833 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 2834 << " tag = " << std::hex << entry.tag 2835 << " set = " << std::dec << set 2836 << " way = " << way 2837 << " count = " << entry.count 2838 << " is_cnt = " << entry.is_cnt << std::endl; 2839 } 2840 #endif 2841 } 2842 else 2843 { 2844 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" 2845 << "Bad HEAP allocation" << std::endl; 2846 exit(0); 2847 } 2847 if (m_debug) 2848 { 2849 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 2850 << " tag = " << std::hex << entry.tag 2851 << " set = " << std::dec << set 2852 << " way = " << way 2853 << " count = " << entry.count 2854 << " is_cnt = " << entry.is_cnt << std::endl; 2855 } 2856 #endif 2848 2857 break; 2849 2858 } … … 2851 2860 case READ_HEAP_WRITE: // add an entry in the heap 2852 2861 { 2853 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 2854 { 2855 HeapEntry heap_entry; 2856 heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 2857 heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2858 2859 if (r_read_count.read() == 1) // creation of a new linked list 2860 { 2861 heap_entry.next = m_heap.next_free_ptr(); 2862 } 2863 else // head insertion in existing list 2864 { 2865 heap_entry.next = r_read_ptr.read(); 2866 } 2867 m_heap.write_free_entry(heap_entry); 2868 m_heap.write_free_ptr(r_read_next_ptr.read()); 2869 if (r_read_last_free.read()) 2870 { 2871 m_heap.set_full(); 2872 } 2873 2874 r_read_fsm = READ_RSP; 2862 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) and 2863 "MEMC ERROR in READ_HEAP_WRITE state: Bad HEAP allocation"); 2864 2865 HeapEntry heap_entry; 2866 heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 2867 heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2868 2869 if (r_read_count.read() == 1) // creation of a new linked list 2870 { 2871 heap_entry.next = m_heap.next_free_ptr(); 2872 } 2873 else // head insertion in existing list 2874 { 2875 heap_entry.next = r_read_ptr.read(); 2876 } 2877 m_heap.write_free_entry(heap_entry); 2878 m_heap.write_free_ptr(r_read_next_ptr.read()); 2879 if (r_read_last_free.read()) 2880 { 2881 m_heap.set_full(); 2882 } 2883 2884 r_read_fsm = READ_RSP; 2875 2885 2876 2886 #if DEBUG_MEMC_READ 2877 if (m_debug) 2878 { 2879 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 2880 << " owner_id = " << std::hex << heap_entry.owner.srcid 2881 << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; 2882 } 2883 #endif 2884 } 2885 else 2886 { 2887 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" 2888 << "Bad HEAP allocation" << std::endl; 2889 exit(0); 2890 } 2887 if (m_debug) 2888 { 2889 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 2890 << " owner_id = " << std::hex << heap_entry.owner.srcid 2891 << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; 2892 } 2893 #endif 2891 2894 break; 2892 2895 } … … 2894 2897 case READ_HEAP_ERASE: 2895 2898 { 2896 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 2897 { 2898 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); 2899 if (next_entry.next == r_read_ptr.read()) 2900 { 2901 r_read_fsm = READ_HEAP_LAST; 2902 } 2903 else 2904 { 2905 r_read_ptr = next_entry.next; 2906 r_read_fsm = READ_HEAP_ERASE; 2907 } 2899 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) and 2900 "MEMC ERROR in READ_HEAP_ERASE state: Bad HEAP allocation"); 2901 2902 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); 2903 if (next_entry.next == r_read_ptr.read()) 2904 { 2905 r_read_fsm = READ_HEAP_LAST; 2908 2906 } 2909 2907 else 2910 2908 { 2911 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" 2912 << "Bad HEAP allocation" << std::endl; 2913 exit(0); 2909 r_read_ptr = next_entry.next; 2910 r_read_fsm = READ_HEAP_ERASE; 2914 2911 } 2915 2912 break; … … 2919 2916 case READ_HEAP_LAST: 2920 2917 { 2921 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 2922 { 2923 HeapEntry last_entry; 2924 last_entry.owner.srcid = 0; 2925 last_entry.owner.inst = false; 2926 2927 if (m_heap.is_full()) 2928 { 2929 last_entry.next = r_read_ptr.read(); 2930 m_heap.unset_full(); 2931 } 2932 else 2933 { 2934 last_entry.next = r_read_next_ptr.read(); 2935 } 2936 m_heap.write(r_read_ptr.read(),last_entry); 2937 r_read_fsm = READ_RSP; 2918 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) and 2919 "MEMC ERROR in READ_HEAP_LAST state: Bad HEAP allocation"); 2920 2921 HeapEntry last_entry; 2922 last_entry.owner.srcid = 0; 2923 last_entry.owner.inst = false; 2924 2925 if (m_heap.is_full()) 2926 { 2927 last_entry.next = r_read_ptr.read(); 2928 m_heap.unset_full(); 2938 2929 } 2939 2930 else 2940 2931 { 2941 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST"2942 << "Bad HEAP allocation" << std::endl;2943 exit(0);2944 }2932 last_entry.next = r_read_next_ptr.read(); 2933 } 2934 m_heap.write(r_read_ptr.read(),last_entry); 2935 r_read_fsm = READ_RSP; 2945 2936 break; 2946 2937 } … … 3006 2997 { 3007 2998 std::cout << " <MEMC " << name() << " READ_TRT_LOCK> Check TRT:" 3008 << " hit_read = " << hit_read3009 << " / hit_write = " << hit_write3010 << " / full = " << !wok << std::endl;2999 << " hit_read = " << hit_read 3000 << " / hit_write = " << hit_write 3001 << " / full = " << !wok << std::endl; 3011 3002 } 3012 3003 #endif … … 3017 3008 case READ_TRT_SET: // register get transaction in TRT 3018 3009 { 3019 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) 3020 { 3021 m_trt.set(r_read_trt_index.read(), 3022 true, // GET 3023 m_nline[(addr_t) (m_cmd_read_addr_fifo.read())], 3024 m_cmd_read_srcid_fifo.read(), 3025 m_cmd_read_trdid_fifo.read(), 3026 m_cmd_read_pktid_fifo.read(), 3027 true, // proc read 3028 m_cmd_read_length_fifo.read(), 3029 m_x[(addr_t) (m_cmd_read_addr_fifo.read())], 3030 std::vector<be_t> (m_words, 0), 3031 std::vector<data_t> (m_words, 0), 3032 r_read_ll_key.read()); 3010 assert((r_alloc_trt_fsm.read() == ALLOC_TRT_READ) and 3011 "MEMC ERROR in READ_TRT_SET state: Bad TRT allocation"); 3012 3013 m_trt.set(r_read_trt_index.read(), 3014 true, // GET 3015 m_nline[(addr_t) (m_cmd_read_addr_fifo.read())], 3016 m_cmd_read_srcid_fifo.read(), 3017 m_cmd_read_trdid_fifo.read(), 3018 m_cmd_read_pktid_fifo.read(), 3019 true, // proc read 3020 m_cmd_read_length_fifo.read(), 3021 m_x[(addr_t) (m_cmd_read_addr_fifo.read())], 3022 std::vector<be_t> (m_words, 0), 3023 std::vector<data_t> (m_words, 0), 3024 r_read_ll_key.read()); 3033 3025 #if DEBUG_MEMC_READ 3034 if (m_debug) 3035 { 3036 std::cout << " <MEMC " << name() << " READ_TRT_SET> Set a GET in TRT:" 3037 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 3038 << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() 3039 << std::endl; 3040 } 3041 #endif 3042 r_read_fsm = READ_TRT_REQ; 3043 } 3026 if (m_debug) 3027 { 3028 std::cout << " <MEMC " << name() << " READ_TRT_SET> Set a GET in TRT:" 3029 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 3030 << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() 3031 << std::endl; 3032 } 3033 #endif 3034 r_read_fsm = READ_TRT_REQ; 3044 3035 break; 3045 3036 } … … 3253 3244 { 3254 3245 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and 3255 "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation");3246 "MEMC ERROR in WRITE_DIR_LOCK state: Bad DIR allocation"); 3256 3247 3257 3248 size_t way = 0; … … 3296 3287 /////////////////// 3297 3288 case WRITE_DIR_HIT: // update the cache directory with Dirty bit 3298 // and update data cache3289 // and update data cache 3299 3290 { 3300 3291 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and 3301 "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation");3292 "MEMC ERROR in WRITE_DIR_HIT state: Bad DIR allocation"); 3302 3293 3303 3294 DirectoryEntry entry; … … 3324 3315 // no_update is true when there is no need for coherence transaction 3325 3316 bool no_update = ((r_write_count.read() == 0) or 3326 (owner and (r_write_count.read() == 1) and3327 ((r_write_pktid.read() & 0x7) != TYPE_SC)));3317 (owner and (r_write_count.read() == 1) and 3318 ((r_write_pktid.read() & 0x7) != TYPE_SC))); 3328 3319 3329 3320 // write data in the cache if no coherence transaction … … 3333 3324 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 3334 3325 { 3335 m_llsc_table.sc(r_write_address.read(), 3336 r_write_sc_key.read()); 3326 m_llsc_table.sc(r_write_address.read(), r_write_sc_key.read()); 3337 3327 } 3338 3328 … … 3340 3330 { 3341 3331 m_cache_data.write(way, 3342 set,3343 word,3344 r_write_data[word].read(),3345 r_write_be[word].read());3332 set, 3333 word, 3334 r_write_data[word].read(), 3335 r_write_be[word].read()); 3346 3336 } 3347 3337 } … … 3359 3349 { 3360 3350 if (!r_write_to_cc_send_multi_req.read() and 3361 3351 !r_write_to_cc_send_brdcast_req.read()) 3362 3352 { 3363 3353 r_write_fsm = WRITE_UPT_LOCK; … … 3392 3382 case WRITE_UPT_LOCK: // Try to register the update request in UPT 3393 3383 { 3384 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and 3385 "MEMC ERROR in WRITE_UPT_LOCK state: Bad DIR allocation"); 3386 3394 3387 if (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) 3395 3388 { … … 3405 3398 3406 3399 wok = m_upt.set(true, // it's an update transaction 3407 false, // it's not a broadcast3408 true, // response required3409 false, // no acknowledge required3410 srcid,3411 trdid,3412 pktid,3413 nline,3414 nb_copies,3415 index);3400 false, // it's not a broadcast 3401 true, // response required 3402 false, // no acknowledge required 3403 srcid, 3404 trdid, 3405 pktid, 3406 nline, 3407 nb_copies, 3408 index); 3416 3409 3417 3410 if (wok) // write data in cache … … 3419 3412 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 3420 3413 { 3421 m_llsc_table.sc(r_write_address.read(), 3422 r_write_sc_key.read()); 3414 m_llsc_table.sc(r_write_address.read(), r_write_sc_key.read()); 3423 3415 } 3424 3416 … … 3426 3418 { 3427 3419 m_cache_data.write(way, 3428 set,3429 word,3430 r_write_data[word].read(),3431 r_write_be[word].read());3420 set, 3421 word, 3422 r_write_data[word].read(), 3423 r_write_be[word].read()); 3432 3424 } 3433 3425 } … … 3459 3451 { 3460 3452 std::cout << " <MEMC " << name() 3461 << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl; 3453 << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" 3454 << std::endl; 3462 3455 } 3463 3456 #endif … … 3469 3462 ////////////////// 3470 3463 case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM 3471 // and write the first copy in the FIFO3472 // send the request if only one copy3464 // and write the first copy in the FIFO 3465 // send the request if only one copy 3473 3466 { 3474 3467 assert(not r_write_to_cc_send_multi_req.read() and … … 3789 3782 case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) 3790 3783 { 3784 assert((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and 3785 "MEMC ERROR in WRITE_MISS_TRT_SET state: Bad TRT allocation"); 3786 3791 3787 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 3792 3788 { … … 3827 3823 case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) 3828 3824 { 3825 assert((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and 3826 "MEMC ERROR in WRITE_MISS_TRT_DATA state: Bad TRT allocation"); 3827 3829 3828 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 3830 3829 { … … 4009 4008 //////////////////////// 4010 4009 case WRITE_BC_DIR_INVAL: // Register a put transaction in TRT 4011 // and invalidate the line in directory4010 // and invalidate the line in directory 4012 4011 { 4013 4012 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and … … 4385 4384 if (m_debug) 4386 4385 { 4387 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex 4388 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; 4386 std::cout << " <MEMC " << name() 4387 << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex 4388 << " address = " << r_ixr_cmd_address.read() + 4389 (r_ixr_cmd_word.read()<<2) << std::endl; 4389 4390 } 4390 4391 #endif … … 4398 4399 if (m_debug) 4399 4400 { 4400 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex 4401 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; 4401 std::cout << " <MEMC " << name() 4402 << " IXR_CMD_WRITE_SEND> GET request:" << std::hex 4403 << " address = " << r_ixr_cmd_address.read() + 4404 (r_ixr_cmd_word.read()<<2) << std::endl; 4402 4405 } 4403 4406 #endif … … 4426 4429 if (m_debug) 4427 4430 { 4428 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex 4429 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl; 4431 std::cout << " <MEMC " << name() 4432 << " IXR_CMD_CAS_SEND> PUT request:" << std::hex 4433 << " address = " << r_ixr_cmd_address.read() + 4434 (r_ixr_cmd_word.read() << 2) << std::endl; 4430 4435 } 4431 4436 #endif … … 4439 4444 if (m_debug) 4440 4445 { 4441 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex 4442 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl; 4446 std::cout << " <MEMC " << name() 4447 << " IXR_CMD_CAS_SEND> GET request:" << std::hex 4448 << " address = " << r_ixr_cmd_address.read() + 4449 (r_ixr_cmd_word.read() << 2) << std::endl; 4443 4450 } 4444 4451 #endif … … 4465 4472 if (m_debug) 4466 4473 { 4467 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex 4468 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl; 4474 std::cout << " <MEMC " << name() 4475 << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex 4476 << " address = " << r_ixr_cmd_address.read() + 4477 (r_ixr_cmd_word.read() << 2) << std::endl; 4469 4478 } 4470 4479 #endif … … 4490 4499 if (m_debug) 4491 4500 { 4492 std::cout << " <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex 4493 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; 4501 std::cout << " <MEMC " << name() 4502 << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex 4503 << " address = " << r_ixr_cmd_address.read() + 4504 (r_ixr_cmd_word.read()<<2) << std::endl; 4494 4505 } 4495 4506 #endif … … 4519 4530 // signal is set to inform the XRAM_RSP FSM. 4520 4531 /////////////////////////////////////////////////////////////////////////////// 4521 4522 //std::cout << std::endl << "ixr_rsp_fsm" << std::endl;4523 4532 4524 4533 switch(r_ixr_rsp_fsm.read()) … … 5813 5822 /////////////////////////////////////////////////////////////////////////////////// 5814 5823 5815 //std::cout << std::endl << "cas_fsm" << std::endl;5816 5817 5824 switch (r_cas_fsm.read()) 5818 5825 { 5819 //////////// 5826 ////////////// 5820 5827 case CAS_IDLE: // fill the local rdata buffers 5821 5828 { … … 5827 5834 { 5828 5835 std::cout << " <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex 5829 << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read()5830 << " addr = " << std::hex << m_cmd_cas_addr_fifo.read()5831 << " wdata = " << m_cmd_cas_wdata_fifo.read()5832 << " eop = " << std::dec << m_cmd_cas_eop_fifo.read()5833 << " cpt = " << std::dec << r_cas_cpt.read() << std::endl;5836 << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() 5837 << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() 5838 << " wdata = " << m_cmd_cas_wdata_fifo.read() 5839 << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() 5840 << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; 5834 5841 } 5835 5842 #endif … … 5877 5884 if (m_debug) 5878 5885 { 5879 std::cout << " <MEMC " << name() << " CAS_DIR_REQ> Requesting DIR lock " << std::endl; 5880 } 5881 #endif 5882 break; 5883 } 5884 ///////////////// 5886 std::cout << " <MEMC " << name() 5887 << " CAS_DIR_REQ> Requesting DIR lock " << std::endl; 5888 } 5889 #endif 5890 break; 5891 } 5892 ////////////////// 5885 5893 case CAS_DIR_LOCK: // Read the directory 5886 5894 { … … 5906 5914 if (m_debug) 5907 5915 { 5908 std::cout << " <MEMC " << name() << " CAS_DIR_LOCK> Directory acces" 5909 << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() 5910 << " / hit = " << std::dec << entry.valid 5911 << " / count = " << entry.count 5912 << " / is_cnt = " << entry.is_cnt << std::endl; 5916 std::cout << " <MEMC " << name() 5917 << " CAS_DIR_LOCK> Directory acces" 5918 << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() 5919 << " / hit = " << std::dec << entry.valid 5920 << " / count = " << entry.count 5921 << " / is_cnt = " << entry.is_cnt << std::endl; 5913 5922 } 5914 5923 #endif … … 5948 5957 if (m_debug) 5949 5958 { 5950 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from " 5951 << " cache and store it in buffer" << std::endl; 5959 std::cout << " <MEMC " << name() 5960 << " CAS_DIR_HIT_READ> Read data from " 5961 << " cache and store it in buffer" << std::endl; 5952 5962 } 5953 5963 #endif … … 5975 5985 if (m_debug) 5976 5986 { 5977 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare old and new data" 5978 << " / expected value = " << std::hex << r_cas_rdata[0].read() 5979 << " / actual value = " << std::hex << r_cas_data[word].read() 5980 << " / forced_fail = " << std::dec << forced_fail << std::endl; 5987 std::cout << " <MEMC " << name() 5988 << " CAS_DIR_HIT_COMPARE> Compare old and new data" 5989 << " / expected value = " << std::hex << r_cas_rdata[0].read() 5990 << " / actual value = " << std::hex << r_cas_data[word].read() 5991 << " / forced_fail = " << std::dec << forced_fail << std::endl; 5981 5992 } 5982 5993 #endif … … 6004 6015 { 6005 6016 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>" 6006 << " Broacast Inval required"6007 << " / copies = " << r_cas_count.read() << std::endl;6017 << " Broacast Inval required" 6018 << " / copies = " << r_cas_count.read() << std::endl; 6008 6019 } 6009 6020 #endif … … 6017 6028 if (m_debug) 6018 6029 { 6019 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>"6020 << "Multi Inval required"6021 << " / copies = " << r_cas_count.read() << std::endl;6030 std::cout << " <MEMC " << name() 6031 << " CAS_DIR_HIT_WRITE> Multi Inval required" 6032 << " / copies = " << r_cas_count.read() << std::endl; 6022 6033 } 6023 6034 #endif … … 6030 6041 if (m_debug) 6031 6042 { 6032 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>" 6033 << " CC_SEND FSM busy: release all locks and retry" << std::endl; 6043 std::cout << " <MEMC " << name() 6044 << " CAS_DIR_HIT_WRITE> CC_SEND FSM busy: " 6045 << "release all locks and retry" << std::endl; 6034 6046 } 6035 6047 #endif … … 6054 6066 if (m_debug) 6055 6067 { 6056 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:" 6057 << " way = " << std::dec << way 6058 << " / set = " << set 6059 << " / word = " << word 6060 << " / value = " << r_cas_wdata.read() 6061 << " / count = " << r_cas_count.read() 6062 << " / global_llsc_table access" << std::endl; 6068 std::cout << " <MEMC " << name() 6069 << " CAS_DIR_HIT_WRITE> Update cache:" 6070 << " way = " << std::dec << way 6071 << " / set = " << set 6072 << " / word = " << word 6073 << " / value = " << r_cas_wdata.read() 6074 << " / count = " << r_cas_count.read() 6075 << " / global_llsc_table access" << std::endl; 6063 6076 } 6064 6077 #endif … … 6068 6081 ///////////////// 6069 6082 case CAS_UPT_LOCK: // try to register the transaction in UPT 6070 // and write data in cache if successful registration6071 // releases locks to retry later if UPT full6083 // and write data in cache if successful registration 6084 // releases locks to retry later if UPT full 6072 6085 { 6073 6086 if (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) … … 6082 6095 6083 6096 wok = m_upt.set(true, // it's an update transaction 6084 false, // it's not a broadcast6085 true, // response required6086 false, // no acknowledge required6087 srcid,6088 trdid,6089 pktid,6090 nline,6091 nb_copies,6092 index);6097 false, // it's not a broadcast 6098 true, // response required 6099 false, // no acknowledge required 6100 srcid, 6101 trdid, 6102 pktid, 6103 nline, 6104 nb_copies, 6105 index); 6093 6106 if (wok) // coherence transaction registered in UPT 6094 6107 { … … 6116 6129 { 6117 6130 std::cout << " <MEMC " << name() 6118 << " CAS_UPT_LOCK> Register multi-update transaction in UPT"6119 << " / wok = " << wok6120 << " / address = " << std::hex << nline * m_words * 46121 << " / count = " << nb_copies << std::endl;6131 << " CAS_UPT_LOCK> Register multi-update transaction in UPT" 6132 << " / wok = " << wok 6133 << " / address = " << std::hex << nline * m_words * 4 6134 << " / count = " << nb_copies << std::endl; 6122 6135 } 6123 6136 #endif … … 6132 6145 if (m_debug) 6133 6146 { 6134 std::cout << " <MEMC " << name() << " CAS_WAIT> Release all locks" << std::endl; 6147 std::cout << " <MEMC " << name() 6148 << " CAS_WAIT> Release all locks" << std::endl; 6135 6149 } 6136 6150 #endif … … 6139 6153 } 6140 6154 ////////////////////// 6141 case CAS_UPT_HEAP_LOCK: // lockthe heap6155 case CAS_UPT_HEAP_LOCK: // get the lock protecting the heap 6142 6156 { 6143 6157 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) … … 6148 6162 { 6149 6163 std::cout << " <MEMC " << name() 6150 << " CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;6164 << " CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl; 6151 6165 } 6152 6166 #endif … … 6159 6173 { 6160 6174 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and 6161 " VCI_MEM_CACHE ERROR: bad HEAP allocation");6175 "MEMC ERROR in state CAS_UPT_REQ: bad HEAP allocation"); 6162 6176 6163 6177 if (!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) … … 6200 6214 if (m_debug) 6201 6215 { 6202 std::cout << " <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM " 6203 << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() 6204 << " / wdata = " << std::hex << r_cas_wdata.read() 6205 << " / srcid = " << std::dec << r_cas_copy.read() 6206 << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; 6207 } 6208 #endif 6209 } 6210 break; 6211 } 6212 ///////////////// 6216 std::cout << " <MEMC " << name() 6217 << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM " 6218 << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() 6219 << " / wdata = " << std::hex << r_cas_wdata.read() 6220 << " / srcid = " << std::dec << r_cas_copy.read() 6221 << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; 6222 } 6223 #endif 6224 } 6225 break; 6226 } 6227 ////////////////// 6213 6228 case CAS_UPT_NEXT: // send a multi-update request to CC_SEND FSM 6214 6229 { 6215 6230 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) 6216 and " VCI_MEM_CACHE ERROR: bad HEAP allocation");6231 and "MEMC ERROR in state CAS_UPT_NEXT : bad HEAP allocation"); 6217 6232 6218 6233 HeapEntry entry = m_heap.read(r_cas_ptr.read()); … … 6228 6243 r_cas_to_cc_send_multi_req = true; 6229 6244 r_cas_fsm = CAS_IDLE; // Response will be sent after receiving 6230 // all update responses6245 // all update responses 6231 6246 cmd_cas_fifo_get = true; 6232 6247 r_cas_cpt = 0; … … 6237 6252 if (m_debug) 6238 6253 { 6239 std::cout << " <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM " 6240 << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() 6241 << " / wdata = " << std::hex << r_cas_wdata.read() 6242 << " / srcid = " << std::dec << entry.owner.srcid 6243 << " / inst = " << std::dec << entry.owner.inst << std::endl; 6254 std::cout << " <MEMC " << name() 6255 << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM " 6256 << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() 6257 << " / wdata = " << std::hex << r_cas_wdata.read() 6258 << " / srcid = " << std::dec << entry.owner.srcid 6259 << " / inst = " << std::dec << entry.owner.inst << std::endl; 6244 6260 } 6245 6261 #endif … … 6269 6285 if (m_debug) 6270 6286 { 6271 std::cout << " <MEMC " << name() << " CAS_BC_TRT_LOCK> Check TRT" 6272 << " : wok = " << wok << " / index = " << wok_index << std::endl; 6287 std::cout << " <MEMC " << name() 6288 << " CAS_BC_TRT_LOCK> Check TRT" 6289 << " : wok = " << wok 6290 << " / index = " << wok_index << std::endl; 6273 6291 } 6274 6292 #endif … … 6297 6315 6298 6316 wok = m_ivt.set(false, // it's an inval transaction 6299 true, // it's a broadcast6300 true, // response required6301 false, // no acknowledge required6302 srcid,6303 trdid,6304 pktid,6305 nline,6306 nb_copies,6307 index);6317 true, // it's a broadcast 6318 true, // response required 6319 false, // no acknowledge required 6320 srcid, 6321 trdid, 6322 pktid, 6323 nline, 6324 nb_copies, 6325 index); 6308 6326 #if DEBUG_MEMC_CAS 6309 6327 if (m_debug and wok) 6310 6328 { 6311 std::cout << " <MEMC " << name() << " CAS_BC_IVT_LOCK> Register broadcast inval in IVT" 6312 << " / copies = " << r_cas_count.read() << std::endl; 6329 std::cout << " <MEMC " << name() 6330 << " CAS_BC_IVT_LOCK> Register broadcast inval in IVT" 6331 << " / copies = " << r_cas_count.read() << std::endl; 6313 6332 } 6314 6333 #endif … … 6355 6374 } 6356 6375 m_trt.set(r_cas_trt_index.read(), 6357 false, // PUT request6358 m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],6359 0,6360 0,6361 0,6362 false, // not a processor read6363 0,6364 0,6365 std::vector<be_t> (m_words,0),6366 data_vector);6376 false, // PUT request 6377 m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())], 6378 0, 6379 0, 6380 0, 6381 false, // not a processor read 6382 0, 6383 0, 6384 std::vector<be_t> (m_words,0), 6385 data_vector); 6367 6386 6368 6387 // invalidate directory entry … … 6387 6406 if (m_debug) 6388 6407 { 6389 std::cout << " <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:" 6390 << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; 6408 std::cout << " <MEMC " << name() 6409 << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:" 6410 << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; 6391 6411 } 6392 6412 #endif … … 6412 6432 { 6413 6433 std::cout << " <MEMC " << name() 6414 << " CAS_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl; 6434 << " CAS_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" 6435 << std::endl; 6415 6436 } 6416 6437 #endif … … 6433 6454 { 6434 6455 std::cout << " <MEMC " << name() 6435 << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex6436 << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read()6437 << " / trt_index = " << r_cas_trt_index.read() << std::endl;6456 << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" 6457 << std::hex << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() 6458 << " / trt_index = " << r_cas_trt_index.read() << std::endl; 6438 6459 } 6439 6460 #endif … … 6458 6479 if (m_debug) 6459 6480 std::cout << " <MEMC " << name() 6460 << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; 6481 << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" 6482 << std::endl; 6461 6483 #endif 6462 6484 } … … 6481 6503 { 6482 6504 std::cout << " <MEMC " << name() 6483 << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; 6505 << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" 6506 << std::endl; 6484 6507 } 6485 6508 #endif … … 6503 6526 { 6504 6527 std::cout << " <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state" 6505 << " / hit_read = " << hit_read6506 << " / hit_write = " << hit_write6507 << " / wok = " << wok6508 << " / index = " << index << std::endl;6528 << " / hit_read = " << hit_read 6529 << " / hit_write = " << hit_write 6530 << " / wok = " << wok 6531 << " / index = " << index << std::endl; 6509 6532 } 6510 6533 #endif … … 6539 6562 6540 6563 m_trt.set(r_cas_trt_index.read(), 6541 true, // GET6542 m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],6543 m_cmd_cas_srcid_fifo.read(),6544 m_cmd_cas_trdid_fifo.read(),6545 m_cmd_cas_pktid_fifo.read(),6546 false, // write request from processor6547 0,6548 0,6549 std::vector<be_t>(m_words, 0),6550 std::vector<data_t>(m_words, 0));6564 true, // GET 6565 m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], 6566 m_cmd_cas_srcid_fifo.read(), 6567 m_cmd_cas_trdid_fifo.read(), 6568 m_cmd_cas_pktid_fifo.read(), 6569 false, // write request from processor 6570 0, 6571 0, 6572 std::vector<be_t>(m_words, 0), 6573 std::vector<data_t>(m_words, 0)); 6551 6574 6552 6575 r_cas_fsm = CAS_MISS_XRAM_REQ; … … 6555 6578 if (m_debug) 6556 6579 { 6557 std::cout << " <MEMC " << name() << " CAS_MISS_TRT_SET> Register GET transaction in TRT" 6558 << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() 6559 << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; 6580 std::cout << " <MEMC " << name() 6581 << " CAS_MISS_TRT_SET> Register GET transaction in TRT" 6582 << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() 6583 << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; 6560 6584 } 6561 6585 #endif … … 6574 6598 if (m_debug) 6575 6599 { 6576 std::cout << " <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction" 6577 << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() 6578 << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; 6600 std::cout << " <MEMC " << name() 6601 << " CAS_MISS_XRAM_REQ> Request a GET transaction" 6602 << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() 6603 << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; 6579 6604 } 6580 6605 #endif … … 7852 7877 //////////////////////////////////////////////////////////////////////////////////// 7853 7878 // The ALLOC_DIR FSM allocates the access to the directory and 7854 // the data cache with a round robin priority between 6 user FSMs : 7855 // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP 7856 // The ressource is always allocated. 7879 // the data cache with a higher priority for the XRAM_RSP FSM, 7880 // and a round robin priority between the five other FSMs : 7881 // (the cyclic ordering is READ > WRITE > CAS > CONFIG > CLEANUP) 7882 // To maximize the throughput, the ressource is always allocated. 7883 // A new allocation is done when the owner FSM does not access the cache. 7884 // - The r_alloc_dir_fsm register define the current owner. 7885 // - The r_alloc_dir_last register define the previous owner for round robin. 7857 7886 ///////////////////////////////////////////////////////////////////////////////////// 7858 7887 7859 //std::cout << std::endl << "alloc_dir_fsm" << std::endl; 7860 7888 // compute the request conditions for the 6 FSMs 7889 bool dir_req_config = (r_config_fsm.read() == CONFIG_DIR_REQ); 7890 bool dir_req_read = (r_read_fsm.read() == READ_DIR_REQ); 7891 bool dir_req_write = (r_write_fsm.read() == WRITE_DIR_REQ); 7892 bool dir_req_cas = (r_cas_fsm.read() == CAS_DIR_REQ); 7893 bool dir_req_cleanup = (r_cleanup_fsm.read() == CLEANUP_DIR_REQ); 7894 bool dir_req_xram_rsp = (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK); 7895 7896 // compute dir_allocate, that is actually a release condition: 7897 // allocation can be done if the owner FSM doest not use the cache 7898 bool dir_allocate = false; 7899 int dir_last; 7861 7900 switch(r_alloc_dir_fsm.read()) 7862 7901 { 7863 ///////////////////// 7864 case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. 7865 // All the WAYS of a SET initialized in parallel 7866 7867 r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); 7902 case ALLOC_DIR_RESET: // Initializes the directory one cycle per set 7903 { 7904 r_alloc_dir_reset_cpt = r_alloc_dir_reset_cpt.read() + 1; 7868 7905 7869 7906 if (r_alloc_dir_reset_cpt.read() == (m_sets - 1)) … … 7873 7910 } 7874 7911 break; 7875 7876 ////////////////////// 7877 case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM 7878 if ((r_config_fsm.read() != CONFIG_DIR_REQ) and 7879 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 7880 (r_config_fsm.read() != CONFIG_TRT_LOCK) and 7881 (r_config_fsm.read() != CONFIG_TRT_SET) and 7882 (r_config_fsm.read() != CONFIG_IVT_LOCK)) 7883 { 7884 if (r_read_fsm.read() == READ_DIR_REQ) 7885 r_alloc_dir_fsm = ALLOC_DIR_READ; 7886 7887 else if (r_write_fsm.read() == WRITE_DIR_REQ) 7888 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 7889 7890 else if (r_cas_fsm.read() == CAS_DIR_REQ) 7891 r_alloc_dir_fsm = ALLOC_DIR_CAS; 7892 7893 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 7894 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 7895 7896 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 7897 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 7898 } 7899 break; 7900 7901 //////////////////// 7902 case ALLOC_DIR_READ: // allocated to READ FSM 7903 if (((r_read_fsm.read() != READ_DIR_REQ) and 7904 (r_read_fsm.read() != READ_DIR_LOCK) and 7905 (r_read_fsm.read() != READ_TRT_LOCK) and 7912 } 7913 case ALLOC_DIR_READ: // owner is READ FSM 7914 { 7915 if (((r_read_fsm.read() != READ_DIR_REQ) and 7916 (r_read_fsm.read() != READ_DIR_LOCK) and 7917 (r_read_fsm.read() != READ_TRT_LOCK) and 7906 7918 (r_read_fsm.read() != READ_HEAP_REQ)) 7907 7919 or … … 7909 7921 (r_alloc_trt_fsm.read() == ALLOC_TRT_READ))) 7910 7922 { 7911 if (r_write_fsm.read() == WRITE_DIR_REQ) 7912 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 7913 7914 else if (r_cas_fsm.read() == CAS_DIR_REQ) 7915 r_alloc_dir_fsm = ALLOC_DIR_CAS; 7916 7917 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 7918 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 7919 7920 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 7921 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 7922 7923 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 7924 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7925 } 7926 break; 7927 7928 ///////////////////// 7929 case ALLOC_DIR_WRITE: // allocated to WRITE FSM 7930 if (((r_write_fsm.read() != WRITE_DIR_REQ) and 7931 (r_write_fsm.read() != WRITE_DIR_LOCK) and 7932 (r_write_fsm.read() != WRITE_BC_DIR_READ) and 7933 (r_write_fsm.read() != WRITE_DIR_HIT) and 7934 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7935 (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and 7923 dir_last = ALLOC_DIR_READ; 7924 dir_allocate = true; 7925 } 7926 break; 7927 } 7928 case ALLOC_DIR_WRITE: // owner is WRITE FSM 7929 { 7930 if (((r_write_fsm.read() != WRITE_DIR_REQ) and 7931 (r_write_fsm.read() != WRITE_DIR_LOCK) and 7932 (r_write_fsm.read() != WRITE_DIR_HIT) and 7933 (r_write_fsm.read() != WRITE_UPT_LOCK) and 7934 (r_write_fsm.read() != WRITE_BC_DIR_READ) and 7935 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 7936 (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and 7936 7937 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7937 (r_write_fsm.read() != WRITE_UPT_LOCK) and7938 7938 (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) 7939 7939 or … … 7944 7944 (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) 7945 7945 { 7946 if (r_cas_fsm.read() == CAS_DIR_REQ) 7947 r_alloc_dir_fsm = ALLOC_DIR_CAS; 7948 7949 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 7950 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 7951 7952 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 7953 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 7954 7955 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 7956 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7957 7958 else if (r_read_fsm.read() == READ_DIR_REQ) 7959 r_alloc_dir_fsm = ALLOC_DIR_READ; 7960 } 7961 break; 7962 7963 /////////////////// 7964 case ALLOC_DIR_CAS: // allocated to CAS FSM 7965 if (((r_cas_fsm.read() != CAS_DIR_REQ) and 7966 (r_cas_fsm.read() != CAS_DIR_LOCK) and 7967 (r_cas_fsm.read() != CAS_DIR_HIT_READ) and 7946 dir_last = ALLOC_DIR_WRITE; 7947 dir_allocate = true; 7948 } 7949 break; 7950 } 7951 case ALLOC_DIR_CAS: // owner is CAS FSM 7952 { 7953 if (((r_cas_fsm.read() != CAS_DIR_REQ) and 7954 (r_cas_fsm.read() != CAS_DIR_LOCK) and 7955 (r_cas_fsm.read() != CAS_DIR_HIT_READ) and 7968 7956 (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and 7969 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and7970 (r_cas_fsm.read() != CAS_ BC_TRT_LOCK)and7971 (r_cas_fsm.read() != CAS_BC_ IVT_LOCK)and7972 (r_cas_fsm.read() != CAS_ MISS_TRT_LOCK)and7973 (r_cas_fsm.read() != CAS_ UPT_LOCK)and7957 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and 7958 (r_cas_fsm.read() != CAS_UPT_LOCK) and 7959 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 7960 (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and 7961 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 7974 7962 (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) 7975 7963 or … … 7980 7968 (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) 7981 7969 { 7982 if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 7983 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 7984 7985 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 7986 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 7987 7988 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 7989 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7990 7991 else if (r_read_fsm.read() == READ_DIR_REQ) 7992 r_alloc_dir_fsm = ALLOC_DIR_READ; 7993 7994 else if (r_write_fsm.read() == WRITE_DIR_REQ) 7995 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 7996 } 7997 break; 7998 7999 /////////////////////// 8000 case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM 7970 dir_last = ALLOC_DIR_CAS; 7971 dir_allocate = true; 7972 } 7973 break; 7974 } 7975 case ALLOC_DIR_CONFIG: // owner is CONFIG FSM 7976 { 7977 if ((r_config_fsm.read() != CONFIG_DIR_REQ) and 7978 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 7979 (r_config_fsm.read() != CONFIG_TRT_LOCK) and 7980 (r_config_fsm.read() != CONFIG_TRT_SET) and 7981 (r_config_fsm.read() != CONFIG_IVT_LOCK)) 7982 { 7983 dir_last = ALLOC_DIR_CONFIG; 7984 dir_allocate = true; 7985 } 7986 break; 7987 } 7988 case ALLOC_DIR_CLEANUP: // owner is CLEANUP FSM 7989 { 8001 7990 if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and 8002 7991 (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and … … 8004 7993 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) 8005 7994 { 8006 if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 8007 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 8008 8009 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 8010 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8011 8012 else if (r_read_fsm.read() == READ_DIR_REQ) 8013 r_alloc_dir_fsm = ALLOC_DIR_READ; 8014 8015 else if (r_write_fsm.read() == WRITE_DIR_REQ) 8016 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8017 8018 else if (r_cas_fsm.read() == CAS_DIR_REQ) 8019 r_alloc_dir_fsm = ALLOC_DIR_CAS; 8020 } 8021 break; 8022 8023 //////////////////////// 8024 case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM 7995 dir_last = ALLOC_DIR_CLEANUP; 7996 dir_allocate = true; 7997 } 7998 7999 break; 8000 } 8001 case ALLOC_DIR_XRAM_RSP: // owner is XRAM_RSP FSM 8002 { 8025 8003 if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and 8026 8004 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 8027 8005 (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) 8028 8006 { 8029 if (r_config_fsm.read() == CONFIG_DIR_REQ) 8030 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8031 8032 else if (r_read_fsm.read() == READ_DIR_REQ) 8033 r_alloc_dir_fsm = ALLOC_DIR_READ; 8034 8035 else if (r_write_fsm.read() == WRITE_DIR_REQ) 8036 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8037 8038 else if (r_cas_fsm.read() == CAS_DIR_REQ) 8039 r_alloc_dir_fsm = ALLOC_DIR_CAS; 8040 8041 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 8042 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 8043 } 8044 break; 8045 8046 } // end switch alloc_dir_fsm 8007 dir_last = r_alloc_dir_last.read(); 8008 dir_allocate = true; 8009 } 8010 break; 8011 } 8012 } // end switch r_alloc_dir_fsm 8013 8014 // set r_alloc_dir_fsm and r_alloc_dir_last registers if required 8015 if ( dir_allocate ) 8016 { 8017 // register last owner for round-robin allocation 8018 r_alloc_dir_last = dir_last; 8019 8020 // higher priority for XRAM_FSM 8021 if ( dir_req_xram_rsp ) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 8022 8023 // round-robin priority for READ > WRITE > CAS > CONFIG > CLEANUP 8024 else if ( dir_last == ALLOC_DIR_READ ) 8025 { 8026 if (dir_req_write) r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8027 else if (dir_req_cas) r_alloc_dir_fsm = ALLOC_DIR_CAS; 8028 else if (dir_req_config) r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8029 else if (dir_req_cleanup) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 8030 else if (dir_req_read) r_alloc_dir_fsm = ALLOC_DIR_READ; 8031 } 8032 else if ( dir_last == ALLOC_DIR_WRITE ) 8033 { 8034 if (dir_req_cas) r_alloc_dir_fsm = ALLOC_DIR_CAS; 8035 else if (dir_req_config) r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8036 else if (dir_req_cleanup) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 8037 else if (dir_req_read) r_alloc_dir_fsm = ALLOC_DIR_READ; 8038 else if (dir_req_write) r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8039 } 8040 else if ( dir_last == ALLOC_DIR_CAS ) 8041 { 8042 if (dir_req_config) r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8043 else if (dir_req_cleanup) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 8044 else if (dir_req_read) r_alloc_dir_fsm = ALLOC_DIR_READ; 8045 else if (dir_req_write) r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8046 else if (dir_req_cas) r_alloc_dir_fsm = ALLOC_DIR_CAS; 8047 } 8048 else if ( dir_last == ALLOC_DIR_CONFIG ) 8049 { 8050 if (dir_req_cleanup) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 8051 else if (dir_req_read) r_alloc_dir_fsm = ALLOC_DIR_READ; 8052 else if (dir_req_write) r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8053 else if (dir_req_cas) r_alloc_dir_fsm = ALLOC_DIR_CAS; 8054 else if (dir_req_config) r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8055 } 8056 else if ( dir_last == ALLOC_DIR_CLEANUP ) 8057 { 8058 if (dir_req_read) r_alloc_dir_fsm = ALLOC_DIR_READ; 8059 else if (dir_req_write) r_alloc_dir_fsm = ALLOC_DIR_WRITE; 8060 else if (dir_req_cas) r_alloc_dir_fsm = ALLOC_DIR_CAS; 8061 else if (dir_req_config) r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 8062 else if (dir_req_cleanup) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 8063 } 8064 } // end if dir_allocate 8047 8065 8048 8066 //////////////////////////////////////////////////////////////////////////////////// … … 8061 8079 /////////////////////////////////////////////////////////////////////////////////// 8062 8080 8063 size_t index = 0; 8064 8065 bool trt_req_read = (r_read_fsm.read() == READ_TRT_LOCK) and 8066 not m_trt.full(index); 8067 8068 bool trt_req_write = ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8069 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) and 8070 not m_trt.full(index); 8071 8072 bool trt_req_cas = ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8073 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) and 8074 not m_trt.full(index); 8075 8076 bool trt_req_config = (r_config_fsm.read() == CONFIG_TRT_LOCK) and 8077 not m_trt.full(index); 8078 8079 bool trt_req_ixr_cmd = (r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8081 // Compute requests for the 7 FSMS 8082 bool trt_req_read = (r_read_fsm.read() == READ_TRT_LOCK); 8083 bool trt_req_write = (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 8084 (r_write_fsm.read() == WRITE_BC_TRT_LOCK); 8085 bool trt_req_cas = (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 8086 (r_cas_fsm.read() == CAS_BC_TRT_LOCK); 8087 bool trt_req_config = (r_config_fsm.read() == CONFIG_TRT_LOCK); 8088 bool trt_req_ixr_cmd = (r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 8080 8089 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 8081 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or8082 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or8090 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or 8091 (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or 8083 8092 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT); 8084 8085 8093 bool trt_req_ixr_rsp = (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 8086 8094 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ); 8087 8088 8095 bool trt_req_xram_rsp = (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY); 8089 8096 8097 // Compute trt_allocate, that is actually a release condition: 8098 // allocation can be done if owner FSM does not use the TRT 8090 8099 bool trt_allocate = false; 8091 8092 // compute allocation condition: 8093 // allocation is done if owner FSM does not use the TRT 8100 int trt_last; 8094 8101 switch(r_alloc_trt_fsm.read()) 8095 8102 { … … 8098 8105 (r_read_fsm.read() != READ_TRT_SET)) 8099 8106 { 8100 r_alloc_trt_last= ALLOC_TRT_READ;8101 trt_allocate 8107 trt_last = ALLOC_TRT_READ; 8108 trt_allocate = true; 8102 8109 } 8103 8110 break; … … 8110 8117 (r_write_fsm.read() != WRITE_BC_DIR_INVAL)) 8111 8118 { 8112 r_alloc_trt_last= ALLOC_TRT_WRITE;8113 trt_allocate 8119 trt_last = ALLOC_TRT_WRITE; 8120 trt_allocate = true; 8114 8121 } 8115 8122 break; … … 8121 8128 (r_cas_fsm.read() != CAS_BC_DIR_INVAL)) 8122 8129 { 8123 r_alloc_trt_last= ALLOC_TRT_CAS;8124 trt_allocate 8130 trt_last = ALLOC_TRT_CAS; 8131 trt_allocate = true; 8125 8132 } 8126 8133 break; … … 8129 8136 (r_config_fsm.read() != CONFIG_TRT_SET)) 8130 8137 { 8131 r_alloc_trt_last= ALLOC_TRT_CONFIG;8132 trt_allocate 8138 trt_last = ALLOC_TRT_CONFIG; 8139 trt_allocate = true; 8133 8140 } 8134 8141 break; … … 8140 8147 (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) 8141 8148 { 8142 trt_allocate = true; 8149 trt_last = r_alloc_trt_last.read(); 8150 trt_allocate = true; 8143 8151 } 8144 8152 break; … … 8149 8157 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_DIRTY)) 8150 8158 { 8151 trt_allocate = true; 8159 trt_last = r_alloc_trt_last.read(); 8160 trt_allocate = true; 8152 8161 } 8153 8162 break; … … 8156 8165 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 8157 8166 { 8158 trt_allocate = true; 8167 trt_last = r_alloc_trt_last.read(); 8168 trt_allocate = true; 8159 8169 } 8160 8170 } // end switch on r_alloc_trt_fsm 8161 8171 8162 // allocateif required8172 // set r_alloc_trt_fsm and r_alloc_trt_last registers if required 8163 8173 if ( trt_allocate ) 8164 8174 { 8175 // register last owner for round-robin 8176 r_alloc_trt_last = trt_last; 8177 8165 8178 // static priorities for XRAM_RSP > IXR_RSP > IXR_CMD 8166 8179 if ( trt_req_xram_rsp ) r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; … … 8169 8182 8170 8183 // round robin priorities for READ / WRITE / CAS / CONFIG 8171 else if ( r_alloc_trt_last.read()== ALLOC_TRT_READ )8184 else if ( trt_last == ALLOC_TRT_READ ) 8172 8185 { 8173 8186 if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; … … 8176 8189 else if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; 8177 8190 } 8178 else if ( r_alloc_trt_last.read()== ALLOC_TRT_WRITE )8191 else if ( trt_last == ALLOC_TRT_WRITE ) 8179 8192 { 8180 8193 if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; … … 8183 8196 else if ( trt_req_write ) r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8184 8197 } 8185 else if ( r_alloc_trt_last.read()== ALLOC_TRT_CAS )8198 else if ( trt_last == ALLOC_TRT_CAS ) 8186 8199 { 8187 8200 if ( trt_req_config ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; … … 8190 8203 else if ( trt_req_cas ) r_alloc_trt_fsm = ALLOC_TRT_CAS; 8191 8204 } 8192 else if ( r_alloc_trt_last.read()== ALLOC_TRT_CONFIG )8205 else if ( trt_last == ALLOC_TRT_CONFIG ) 8193 8206 { 8194 8207 if ( trt_req_read ) r_alloc_trt_fsm = ALLOC_TRT_READ; … … 8209 8222 ///////////////////////////////////////////////////////////////////////////////////// 8210 8223 8211 //std::cout << std::endl << "alloc_heap_fsm" << std::endl; 8224 // compute requests for the 6 FSMs 8225 bool req_heap_read = (r_read_fsm.read() == READ_HEAP_REQ); 8226 bool req_heap_write = (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK); 8227 bool req_heap_cas = (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK); 8228 bool req_heap_cleanup = (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ); 8229 bool req_heap_xram_rsp = (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ); 8230 bool req_heap_config = (r_config_fsm.read() == CONFIG_HEAP_REQ); 8212 8231 8213 8232 switch (r_alloc_heap_fsm.read()) 8214 8233 { 8215 //////////////////// 8234 ////////////////////// 8216 8235 case ALLOC_HEAP_RESET: 8217 8236 // Initializes the heap one ENTRY each cycle. … … 8227 8246 break; 8228 8247 8229 8248 ///////////////////// 8230 8249 case ALLOC_HEAP_READ: 8231 if ((r_read_fsm.read() != READ_HEAP_REQ) and 8232 (r_read_fsm.read() != READ_HEAP_LOCK) and 8233 (r_read_fsm.read() != READ_HEAP_ERASE)) 8234 { 8235 if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) 8236 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8237 8238 else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) 8239 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8240 8241 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 8242 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8243 8244 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 8245 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8246 8247 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 8248 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8249 } 8250 break; 8251 8252 ///////////////////// 8250 if ((r_read_fsm.read() != READ_HEAP_REQ) and 8251 (r_read_fsm.read() != READ_HEAP_LOCK) and 8252 (r_read_fsm.read() != READ_HEAP_ERASE)) 8253 { 8254 if (req_heap_write) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8255 else if (req_heap_cas) r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8256 else if (req_heap_cleanup) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8257 else if (req_heap_xram_rsp) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8258 else if (req_heap_config) r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8259 } 8260 break; 8261 8262 ///////////////////// 8253 8263 case ALLOC_HEAP_WRITE: 8254 8264 if ((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and … … 8256 8266 (r_write_fsm.read() != WRITE_UPT_NEXT)) 8257 8267 { 8258 if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) 8259 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8260 8261 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 8262 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8263 8264 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 8265 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8266 8267 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 8268 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8269 8270 else if (r_read_fsm.read() == READ_HEAP_REQ) 8271 r_alloc_heap_fsm = ALLOC_HEAP_READ; 8272 } 8273 break; 8274 8275 //////////////////// 8268 if (req_heap_cas) r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8269 else if (req_heap_cleanup) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8270 else if (req_heap_xram_rsp) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8271 else if (req_heap_config) r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8272 else if (req_heap_read) r_alloc_heap_fsm = ALLOC_HEAP_READ; 8273 } 8274 break; 8275 8276 //////////////////// 8276 8277 case ALLOC_HEAP_CAS: 8277 8278 if ((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and … … 8279 8280 (r_cas_fsm.read() != CAS_UPT_NEXT)) 8280 8281 { 8281 if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 8282 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8283 8284 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 8285 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8286 8287 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 8288 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8289 8290 else if (r_read_fsm.read() == READ_HEAP_REQ) 8291 r_alloc_heap_fsm = ALLOC_HEAP_READ; 8292 8293 else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) 8294 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8295 } 8296 break; 8297 8298 /////////////////////// 8282 if (req_heap_cleanup) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8283 else if (req_heap_xram_rsp) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8284 else if (req_heap_config) r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8285 else if (req_heap_read) r_alloc_heap_fsm = ALLOC_HEAP_READ; 8286 else if (req_heap_write) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8287 } 8288 break; 8289 8290 //////////////////////// 8299 8291 case ALLOC_HEAP_CLEANUP: 8300 8292 if ((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and … … 8303 8295 (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)) 8304 8296 { 8305 if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 8306 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8307 8308 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 8309 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8310 8311 else if (r_read_fsm.read() == READ_HEAP_REQ) 8312 r_alloc_heap_fsm = ALLOC_HEAP_READ; 8313 8314 else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) 8315 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8316 8317 else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) 8318 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8319 } 8320 break; 8321 8322 //////////////////////// 8297 if (req_heap_xram_rsp) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8298 else if (req_heap_config) r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8299 else if (req_heap_read) r_alloc_heap_fsm = ALLOC_HEAP_READ; 8300 else if (req_heap_write) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8301 else if (req_heap_cas) r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8302 } 8303 break; 8304 8305 //////////////////////// 8323 8306 case ALLOC_HEAP_XRAM_RSP: 8324 8307 if ((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and 8325 8308 (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) 8326 8309 { 8327 if (r_config_fsm.read() == CONFIG_HEAP_REQ) 8328 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8329 8330 else if (r_read_fsm.read() == READ_HEAP_REQ) 8331 r_alloc_heap_fsm = ALLOC_HEAP_READ; 8332 8333 else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) 8334 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8335 8336 else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) 8337 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8338 8339 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 8340 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8341 8342 } 8343 break; 8344 8345 /////////////////////// 8310 if (req_heap_config) r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 8311 else if (req_heap_read) r_alloc_heap_fsm = ALLOC_HEAP_READ; 8312 else if (req_heap_write) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8313 else if (req_heap_cas) r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8314 else if (req_heap_cleanup) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8315 } 8316 break; 8317 8318 /////////////////////// 8346 8319 case ALLOC_HEAP_CONFIG: 8347 8320 if ((r_config_fsm.read() != CONFIG_HEAP_REQ) and 8348 8321 (r_config_fsm.read() != CONFIG_HEAP_SCAN)) 8349 8322 { 8350 if (r_read_fsm.read() == READ_HEAP_REQ) 8351 r_alloc_heap_fsm = ALLOC_HEAP_READ; 8352 8353 else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) 8354 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8355 8356 else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) 8357 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8358 8359 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 8360 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8361 8362 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 8363 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8323 if (req_heap_read) r_alloc_heap_fsm = ALLOC_HEAP_READ; 8324 else if (req_heap_write) r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 8325 else if (req_heap_cas) r_alloc_heap_fsm = ALLOC_HEAP_CAS; 8326 else if (req_heap_cleanup) r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 8327 else if (req_heap_xram_rsp) r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 8364 8328 } 8365 8329 break; … … 8367 8331 } // end switch alloc_heap_fsm 8368 8332 8369 //std::cout << std::endl << "fifo_update" << std::endl;8370 8333 8371 8334 /////////////////////////////////////////////////////////////////////
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