Index: /trunk/platforms/tsar_generic_iob/arch_info.py =================================================================== --- /trunk/platforms/tsar_generic_iob/arch_info.py (revision 1044) +++ /trunk/platforms/tsar_generic_iob/arch_info.py (revision 1044) @@ -0,0 +1,335 @@ +#!/usr/bin/env python + +from math import log, ceil +from genarch import * + +######################################################################################### +# file : arch_info.py (for the tsar_generic_iob architecture) +# date : may 2014 +# author : Alain Greiner +######################################################################################### +# This python script defines a specific instance of "tsar_generic_iob" architecture +# for the ALMOS-MK operating system. It is used to generate the "hard_config.h" +# and the "arch_info.bin files, used by bthe ALMOS-MK bootloader. +# +# The "tsar_generic_iob" architecture includes 7 external peripherals, accessed +# through an IOB components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. +# Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC. +# All clusters contain (nb_cores) processors, one L2 cache, one XCU, and +# one optional hardware coprocessor connected to a MWMR controller. +# +# The following parameters are constructor arguments: +# - x_size : number of clusters in a row (from 1 to 16) +# - y_size : number of clusters in a column (from & to 16) +# - nb_cores : number of processors per cluster (from 1 to 4) +# - nb_ttys : number of TTY channels (can be from 1 to 8) +# - fbf_width : frame_buffer width = frame_buffer heigth +# - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' +# - mwr_type : coprocessor type (can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE') +# - nb_nics : number of NIC channels (can be from 1 to 2) +# - nb_cmas : number of CMA channels (can be from 1 to 4) +# - io_cxy : cluster_io identifier +# - boot_cxy : boot cluster identifier +# +# The following parameters are imposed by the "tsar_generic_iob" architecture: +# - devices_max : max number of devices per cluster +# - x_width : number of bits for x coordinate +# - y_width : number of bits for y coordinate +# - paddr_width : number of bits for physical address +# - irqs_per_core : number of input IRQs per processor +######################################################################################## + +############################ +def arch( x_size = 2, + y_size = 2, + nb_cores = 2, + nb_ttys = 1, + fbf_width = 128, + ioc_type = 'IOC_BDV', + mwr_type = 'MWR_CPY', + nb_nics = 1, + nb_cmas = 2, + io_cxy = 0, + boot_cxy = 0 ): + + ### architecture constants + + p_width = 2 + x_width = 4 + y_width = 4 + paddr_width = 40 + irqs_per_core = 4 + devices_max = 16 + + ### constructor parameters checking + + assert( (x_size == 1) or (x_size == 2) or (x_size == 4) + or (x_size == 8) or (x_size == 16) ) + + assert( (y_size == 1) or (y_size == 2) or (y_size == 4) + or (y_size == 8) or (y_size == 16) ) + + assert( nb_cores <= 4 ) + + assert( (nb_ttys >= 1) and (nb_ttys <= 8) ) + + assert( (nb_nics >= 1) and (nb_nics <= 2) ) + + assert( (nb_cmas >= 1) and (nb_cmas <= 4) ) + + assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] ) + + assert( mwr_type in ['MWR_GCD','MWR_DCT','MWR_CPY'] ) + + assert( (io_cxy == 0) or (io_cxy == ((x_size-1)<> y_width) < x_size) and ((boot_cxy & ((1< boot cost two BIG pages in cluster[0][0] + + boot_archi_vbase = 0x00000000 # ident + boot_archi_size = 0x00100000 # 1 Mbytes + + boot_code_vbase = 0x00100000 # ident + boot_code_size = 0x00080000 # 512 Kbytes + + boot_stack_vbase = 0x00180000 # ident + boot_stack_size = 0x00080000 # 512 Kbytes + + boot_data_vbase = 0x00200000 # ident + boot_data_size = 0x00200000 # 2 Mbytes + + ### define kernel vsegs base addresses and sizes + ### code, init, ptab, heap & sched vsegs are replicated in all clusters. + ### data & uncdata vsegs are only mapped in cluster[0][0]. + + kernel_code_vbase = 0x80000000 + kernel_code_size = 0x00200000 # 2 Mbytes per cluster + + kernel_data_vbase = 0x90000000 + kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0] + + kernel_ptab_vbase = 0xE0000000 + kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster + + kernel_heap_vbase = 0xD0000000 + kernel_heap_size = 0x00400000 # 4 Mbytes per cluster + + kernel_sched_vbase = 0xA0000000 + kernel_sched_size = 0x00002000*nb_cores # 8 Kbytes per proc per cluster + + ############################ + ### call Header constructor + ############################ + + archi = Root( name = platform_name, + x_size = x_size, + y_size = y_size, + cores_max = nb_cores, + devices_max = devices_max, + paddr_width = paddr_width, + x_width = x_width, + y_width = y_width, + irqs_per_core = irqs_per_core, + use_ramdisk = (ioc_type == 'RDK'), + io_cxy = io_cxy, + boot_cxy = boot_cxy, + reset_address = rom_base ) + + ############################################## + ### construct replicated hardware components + ############################################## + + for x in xrange( x_size ): + for y in xrange( y_size ): + cxy = (x << y_width) + y; + offset = cxy << (paddr_width - x_width - y_width) + + ram = archi.addDevice( ptype = 'RAM' , + base = ram_base + offset, + size = ram_size ) + + xcu = archi.addDevice( ptype = 'XCU', + base = xcu_base + offset, + size = xcu_size, + channels = nb_cores * irqs_per_core, + arg0 = 16, + arg1 = 16, + arg2 = 16 ) + + mmc = archi.addDevice( ptype = 'MMC', + base = mmc_base + offset, + size = mmc_size ) + archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc, isrtype = 'ISR_MMC' ) + + if ( mwr_type == 'MWR_GCD' ): + mwr = archi.addDevice( ptype = 'MWR_GCD', + base = mwr_base + offset, + size = mwr_size, + arg0 = 2, + arg1 = 1, + arg2 = 1, + arg3 = 0 ) + archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) + + if ( mwr_type == 'MWR_DCT' ): + mwr = archi.addDevice( ptype = 'MWR_DCT', + base = mwr_base + offset, + size = mwr_size, + arg0 = 1, + arg1 = 1, + arg2 = 1, + arg3 = 0 ) + archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) + + if ( mwr_type == 'MWR_CPY' ): + mwr = archi.addDevice( ptype = 'MWR_CPY', + base = mwr_base + offset, + size = mwr_size, + arg0 = 1, + arg1 = 1, + arg2 = 1, + arg3 = 0 ) + archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) + + for p in xrange ( nb_cores ): + archi.addCore( (x<<(y_width+p_width)) + (y<proc[l]->print_frozen_stats(); + } + } + } }