Changeset 1045 for trunk/platforms/tsar_generic_iob
- Timestamp:
- Aug 21, 2016, 4:03:14 PM (8 years ago)
- File:
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- 1 edited
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trunk/platforms/tsar_generic_iob/arch_info.py (modified) (9 diffs)
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trunk/platforms/tsar_generic_iob/arch_info.py
r1044 r1045 1 1 #!/usr/bin/env python 2 2 3 from math import log, ceil 4 from genarch import * 3 from arch_classes import * 5 4 6 5 ######################################################################################### 7 # file : arch_info.py (for the tsar_generic_iob architecture)8 # date : may 20146 # file : arch_info.py for the tsar_generic_iob architecture) 7 # date : august 2016 9 8 # author : Alain Greiner 10 9 ######################################################################################### … … 13 12 # and the "arch_info.bin files, used by bthe ALMOS-MK bootloader. 14 13 # 14 # The constructor prototype format is imposed by the genarch.py application, 15 # and should not be modified. 16 # 15 17 # The "tsar_generic_iob" architecture includes 7 external peripherals, accessed 16 18 # through an IOB components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. … … 19 21 # one optional hardware coprocessor connected to a MWMR controller. 20 22 # 21 # The following parameters are constructor arguments: 23 # As the "tsar_generic_iob" architecture is generic, the following parameters 24 # are defined as constructor arguments and can be redefined in the Makefile when 25 # a new kernel image is generated : 22 26 # - x_size : number of clusters in a row (from 1 to 16) 23 27 # - y_size : number of clusters in a column (from & to 16) 24 28 # - nb_cores : number of processors per cluster (from 1 to 4) 25 29 # - nb_ttys : number of TTY channels (can be from 1 to 8) 30 # - nb_nics : number of NIC channels (from 1 to 2) 31 # - nb_cmas : number of CMA channels (from 1 to 4) 26 32 # - fbf_width : frame_buffer width = frame_buffer heigth 27 33 # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' 28 # - mwr_type : coprocessor type (can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE') 29 # - nb_nics : number of NIC channels (can be from 1 to 2) 30 # - nb_cmas : number of CMA channels (can be from 1 to 4) 31 # - io_cxy : cluster_io identifier 34 # - mwr_type : can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE' 35 # - io_cxy : IO cluster identifier 32 36 # - boot_cxy : boot cluster identifier 33 37 # … … 37 41 # - y_width : number of bits for y coordinate 38 42 # - paddr_width : number of bits for physical address 43 # - p_width : number of bits for local processor index 39 44 # - irqs_per_core : number of input IRQs per processor 40 45 ######################################################################################## … … 45 50 nb_cores = 2, 46 51 nb_ttys = 1, 52 nb_nics = 1, 53 nb_cmas = 2, 47 54 fbf_width = 128, 48 55 ioc_type = 'IOC_BDV', 49 56 mwr_type = 'MWR_CPY', 50 nb_nics = 1,51 nb_cmas = 2,52 57 io_cxy = 0, 53 58 boot_cxy = 0 ): … … 89 94 90 95 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_cores ) 91 platform_name += '_%d_%d_%s_%s' % ( fbf_width , nb_ttys , ioc_type , mwr_type )92 96 93 97 ### define physical segments replicated in all clusters … … 131 135 rom_base = 0x00BFC00000 132 136 rom_size = 0x4000 # 16 Kbytes 133 134 ### define bootloader vsegs base addresses and sizes135 ### We want to pack these 4 vsegs in 2 big pages136 ### => boot cost two BIG pages in cluster[0][0]137 138 boot_archi_vbase = 0x00000000 # ident139 boot_archi_size = 0x00100000 # 1 Mbytes140 141 boot_code_vbase = 0x00100000 # ident142 boot_code_size = 0x00080000 # 512 Kbytes143 144 boot_stack_vbase = 0x00180000 # ident145 boot_stack_size = 0x00080000 # 512 Kbytes146 147 boot_data_vbase = 0x00200000 # ident148 boot_data_size = 0x00200000 # 2 Mbytes149 150 ### define kernel vsegs base addresses and sizes151 ### code, init, ptab, heap & sched vsegs are replicated in all clusters.152 ### data & uncdata vsegs are only mapped in cluster[0][0].153 154 kernel_code_vbase = 0x80000000155 kernel_code_size = 0x00200000 # 2 Mbytes per cluster156 157 kernel_data_vbase = 0x90000000158 kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0]159 160 kernel_ptab_vbase = 0xE0000000161 kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster162 163 kernel_heap_vbase = 0xD0000000164 kernel_heap_size = 0x00400000 # 4 Mbytes per cluster165 166 kernel_sched_vbase = 0xA0000000167 kernel_sched_size = 0x00002000*nb_cores # 8 Kbytes per proc per cluster168 137 169 138 ############################ … … 171 140 ############################ 172 141 173 archi = Root( name = platform_name,174 x_size = x_size,175 y_size = y_size,176 cores_max = nb_cores,177 devices_max = devices_max,178 paddr_width = paddr_width,179 x_width = x_width,180 y_width = y_width,181 irqs_per_core = irqs_per_core,182 use_ramdisk = (ioc_type == 'RDK'),183 io_cxy = io_cxy,184 boot_cxy = boot_cxy,185 reset_address = rom_base )186 187 ############################################## 188 ### construct replicated hardware components189 ############################################## 142 archi = Archinfo( name = platform_name, 143 x_size = x_size, 144 y_size = y_size, 145 cores_max = nb_cores, 146 devices_max = devices_max, 147 paddr_width = paddr_width, 148 x_width = x_width, 149 y_width = y_width, 150 irqs_per_core = irqs_per_core, 151 use_ramdisk = (ioc_type == 'RDK'), 152 io_cxy = io_cxy, 153 boot_cxy = boot_cxy, 154 reset_address = rom_base ) 155 156 #################################################### 157 ### construct hardware components for each cluster 158 #################################################### 190 159 191 160 for x in xrange( x_size ): 192 161 for y in xrange( y_size ): 193 cxy = (x << y_width) + y; 194 offset = cxy << (paddr_width - x_width - y_width) 195 162 cxy = (x << y_width) + y; 163 offset = cxy << (paddr_width - x_width - y_width) 164 165 # build devices 196 166 ram = archi.addDevice( ptype = 'RAM' , 197 167 base = ram_base + offset, … … 241 211 archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) 242 212 213 if( cxy == io_cxy ): 214 215 iob = archi.addDevice( ptype = 'IOB', 216 base = iob_base + offset, 217 size = iob_size ) 218 219 ioc = archi.addDevice( ptype = ioc_type, 220 base = ioc_base + offset, 221 size = ioc_size ) 222 223 tty = archi.addDevice( ptype = 'TTY', 224 base = tty_base + offset, 225 size = tty_size, 226 channels = nb_ttys ) 227 228 nic = archi.addDevice( ptype = 'NIC', 229 base = nic_base + offset, 230 size = nic_size, 231 channels = nb_nics ) 232 233 cma = archi.addDevice( ptype = 'CMA', 234 base = cma_base + offset, 235 size = cma_size, 236 channels = nb_cmas ) 237 238 fbf = archi.addDevice( ptype = 'FBF', 239 base = fbf_base + offset, 240 size = fbf_size, 241 arg0 = fbf_width, 242 arg1 = fbf_width ) 243 244 rom = archi.addDevice( ptype = 'ROM', 245 base = rom_base + offset, 246 size = rom_size ) 247 248 pic = archi.addDevice( ptype ='PIC', 249 base = pic_base + offset, 250 size = pic_size, 251 arg0 = 32 ) 252 253 if ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV' 254 elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA' 255 elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC' 256 elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI' 257 else : isr_ioc = 'ISR_DEFAULT' 258 259 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 ) 260 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 ) 261 archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 ) 262 archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 ) 263 archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 0 ) 264 archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 1 ) 265 archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 2 ) 266 archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 3 ) 267 archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc , channel = 0 ) 268 archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 ) 269 archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 ) 270 archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 ) 271 archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 ) 272 archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 ) 273 archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 ) 274 archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 ) 275 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 ) 276 277 # build cores 243 278 for p in xrange ( nb_cores ): 244 archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware identifier 245 (x<<y_width) + y, # cluster identifier 246 p ) # local index 247 248 ################################################# 249 ### construct hardware components in IO cluster 250 ################################################# 251 252 offset = io_cxy << (paddr_width - x_width - y_width) 253 254 iob = archi.addDevice( ptype = 'IOB', 255 base = iob_base + offset, 256 size = iob_size ) 257 258 ioc = archi.addDevice( ptype = ioc_type, 259 base = ioc_base + offset, 260 size = ioc_size ) 261 262 tty = archi.addDevice( ptype = 'TTY', 263 base = tty_base + offset, 264 size = tty_size, 265 channels = nb_ttys ) 266 267 nic = archi.addDevice( ptype = 'NIC', 268 base = nic_base + offset, 269 size = nic_size, 270 channels = nb_nics ) 271 272 cma = archi.addDevice( ptype = 'CMA', 273 base = cma_base + offset, 274 size = cma_size, 275 channels = nb_cmas ) 276 277 fbf = archi.addDevice( ptype = 'FBF', 278 base = fbf_base + offset, 279 size = fbf_size, 280 arg0 = fbf_width, 281 arg1 = fbf_width ) 282 283 rom = archi.addDevice( ptype = 'ROM', 284 base = rom_base + offset, 285 size = rom_size ) 286 287 pic = archi.addDevice( ptype ='PIC', 288 base = pic_base + offset, 289 size = pic_size, 290 arg0 = 32 ) 291 292 if ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV' 293 elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA' 294 elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC' 295 elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI' 296 else : isr_ioc = 'ISR_DEFAULT' 297 298 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 ) 299 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 ) 300 archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 ) 301 archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 ) 302 archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 0 ) 303 archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 1 ) 304 archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 2 ) 305 archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 3 ) 306 archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc , channel = 0 ) 307 archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 ) 308 archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 ) 309 archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 ) 310 archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 ) 311 archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 ) 312 archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 ) 313 archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 ) 314 archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 ) 279 core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p, # hardware identifier 280 (x<<y_width) + y, # cluster identifier 281 p ) # local index 315 282 316 283 return archi
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