Index: /trunk/platforms/tsar_generic_iob/arch_info.py =================================================================== --- /trunk/platforms/tsar_generic_iob/arch_info.py (revision 1044) +++ /trunk/platforms/tsar_generic_iob/arch_info.py (revision 1045) @@ -1,10 +1,9 @@ #!/usr/bin/env python -from math import log, ceil -from genarch import * +from arch_classes import * ######################################################################################### -# file : arch_info.py (for the tsar_generic_iob architecture) -# date : may 2014 +# file : arch_info.py for the tsar_generic_iob architecture) +# date : august 2016 # author : Alain Greiner ######################################################################################### @@ -13,4 +12,7 @@ # and the "arch_info.bin files, used by bthe ALMOS-MK bootloader. # +# The constructor prototype format is imposed by the genarch.py application, +# and should not be modified. +# # The "tsar_generic_iob" architecture includes 7 external peripherals, accessed # through an IOB components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. @@ -19,15 +21,17 @@ # one optional hardware coprocessor connected to a MWMR controller. # -# The following parameters are constructor arguments: +# As the "tsar_generic_iob" architecture is generic, the following parameters +# are defined as constructor arguments and can be redefined in the Makefile when +# a new kernel image is generated : # - x_size : number of clusters in a row (from 1 to 16) # - y_size : number of clusters in a column (from & to 16) # - nb_cores : number of processors per cluster (from 1 to 4) # - nb_ttys : number of TTY channels (can be from 1 to 8) +# - nb_nics : number of NIC channels (from 1 to 2) +# - nb_cmas : number of CMA channels (from 1 to 4) # - fbf_width : frame_buffer width = frame_buffer heigth # - ioc_type : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE' -# - mwr_type : coprocessor type (can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE') -# - nb_nics : number of NIC channels (can be from 1 to 2) -# - nb_cmas : number of CMA channels (can be from 1 to 4) -# - io_cxy : cluster_io identifier +# - mwr_type : can be 'MWR_GCD','MWR_DCT','MWR_CPY','NONE' +# - io_cxy : IO cluster identifier # - boot_cxy : boot cluster identifier # @@ -37,4 +41,5 @@ # - y_width : number of bits for y coordinate # - paddr_width : number of bits for physical address +# - p_width : number of bits for local processor index # - irqs_per_core : number of input IRQs per processor ######################################################################################## @@ -45,9 +50,9 @@ nb_cores = 2, nb_ttys = 1, + nb_nics = 1, + nb_cmas = 2, fbf_width = 128, ioc_type = 'IOC_BDV', mwr_type = 'MWR_CPY', - nb_nics = 1, - nb_cmas = 2, io_cxy = 0, boot_cxy = 0 ): @@ -89,5 +94,4 @@ platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_cores ) - platform_name += '_%d_%d_%s_%s' % ( fbf_width , nb_ttys , ioc_type , mwr_type ) ### define physical segments replicated in all clusters @@ -131,39 +135,4 @@ rom_base = 0x00BFC00000 rom_size = 0x4000 # 16 Kbytes - - ### define bootloader vsegs base addresses and sizes - ### We want to pack these 4 vsegs in 2 big pages - ### => boot cost two BIG pages in cluster[0][0] - - boot_archi_vbase = 0x00000000 # ident - boot_archi_size = 0x00100000 # 1 Mbytes - - boot_code_vbase = 0x00100000 # ident - boot_code_size = 0x00080000 # 512 Kbytes - - boot_stack_vbase = 0x00180000 # ident - boot_stack_size = 0x00080000 # 512 Kbytes - - boot_data_vbase = 0x00200000 # ident - boot_data_size = 0x00200000 # 2 Mbytes - - ### define kernel vsegs base addresses and sizes - ### code, init, ptab, heap & sched vsegs are replicated in all clusters. - ### data & uncdata vsegs are only mapped in cluster[0][0]. - - kernel_code_vbase = 0x80000000 - kernel_code_size = 0x00200000 # 2 Mbytes per cluster - - kernel_data_vbase = 0x90000000 - kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0] - - kernel_ptab_vbase = 0xE0000000 - kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster - - kernel_heap_vbase = 0xD0000000 - kernel_heap_size = 0x00400000 # 4 Mbytes per cluster - - kernel_sched_vbase = 0xA0000000 - kernel_sched_size = 0x00002000*nb_cores # 8 Kbytes per proc per cluster ############################ @@ -171,27 +140,28 @@ ############################ - archi = Root( name = platform_name, - x_size = x_size, - y_size = y_size, - cores_max = nb_cores, - devices_max = devices_max, - paddr_width = paddr_width, - x_width = x_width, - y_width = y_width, - irqs_per_core = irqs_per_core, - use_ramdisk = (ioc_type == 'RDK'), - io_cxy = io_cxy, - boot_cxy = boot_cxy, - reset_address = rom_base ) - - ############################################## - ### construct replicated hardware components - ############################################## + archi = Archinfo( name = platform_name, + x_size = x_size, + y_size = y_size, + cores_max = nb_cores, + devices_max = devices_max, + paddr_width = paddr_width, + x_width = x_width, + y_width = y_width, + irqs_per_core = irqs_per_core, + use_ramdisk = (ioc_type == 'RDK'), + io_cxy = io_cxy, + boot_cxy = boot_cxy, + reset_address = rom_base ) + + #################################################### + ### construct hardware components for each cluster + #################################################### for x in xrange( x_size ): for y in xrange( y_size ): - cxy = (x << y_width) + y; - offset = cxy << (paddr_width - x_width - y_width) - + cxy = (x << y_width) + y; + offset = cxy << (paddr_width - x_width - y_width) + + # build devices ram = archi.addDevice( ptype = 'RAM' , base = ram_base + offset, @@ -241,76 +211,73 @@ archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' ) + if( cxy == io_cxy ): + + iob = archi.addDevice( ptype = 'IOB', + base = iob_base + offset, + size = iob_size ) + + ioc = archi.addDevice( ptype = ioc_type, + base = ioc_base + offset, + size = ioc_size ) + + tty = archi.addDevice( ptype = 'TTY', + base = tty_base + offset, + size = tty_size, + channels = nb_ttys ) + + nic = archi.addDevice( ptype = 'NIC', + base = nic_base + offset, + size = nic_size, + channels = nb_nics ) + + cma = archi.addDevice( ptype = 'CMA', + base = cma_base + offset, + size = cma_size, + channels = nb_cmas ) + + fbf = archi.addDevice( ptype = 'FBF', + base = fbf_base + offset, + size = fbf_size, + arg0 = fbf_width, + arg1 = fbf_width ) + + rom = archi.addDevice( ptype = 'ROM', + base = rom_base + offset, + size = rom_size ) + + pic = archi.addDevice( ptype ='PIC', + base = pic_base + offset, + size = pic_size, + arg0 = 32 ) + + if ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV' + elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA' + elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC' + elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI' + else : isr_ioc = 'ISR_DEFAULT' + + archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 ) + archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 ) + archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 ) + archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 ) + archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 0 ) + archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 1 ) + archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 2 ) + archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA' , channel = 3 ) + archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc , channel = 0 ) + archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 ) + archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 ) + archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 ) + archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 ) + archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 ) + archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 ) + archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 ) + archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 ) + + # build cores for p in xrange ( nb_cores ): - archi.addCore( (x<<(y_width+p_width)) + (y<