- Timestamp:
- Oct 7, 2010, 6:59:10 PM (14 years ago)
- Location:
- trunk/platforms/caba-vdspin-vci_synthetic_initiator
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/caba-vdspin-vci_synthetic_initiator/platform_desc
r103 r105 16 16 cell_size = 4, 17 17 plen_size = 8, 18 addr_size = 40,18 addr_size = 32, 19 19 rerror_size = 1, 20 20 clen_size = 1, 21 21 rflag_size = 1, 22 srcid_size = 8,22 srcid_size = 11, 23 23 pktid_size = 4, 24 24 trdid_size = 4, -
trunk/platforms/caba-vdspin-vci_synthetic_initiator/top.cpp
r103 r105 11 11 #include "alloc_elems.h" 12 12 #include "vci_simple_ram.h" 13 //#include "vci_multi_tty.h"14 13 #include "vci_local_ring_fast.h" 15 14 #include "virtual_dspin_router.h" … … 29 28 #define WEST 3 30 29 #define LOCAL 4 30 // VCI parameters 31 #define cell_width 4 32 #define plen_width 8 33 #define address_width 32 34 #define error_width 1 35 #define clen_width 1 36 #define rflag_width 1 37 #define srcid_width 11 38 #define pktid_width 4 39 #define trdid_width 4 40 #define wrplen_width 1 41 // Adress of targets 42 #define TARGET_ADDR 0x00000000 43 #define TARGET_SIZE 0x400 31 44 32 45 … … 41 54 42 55 // Define VCI parameters 43 typedef soclib::caba::VciParams<4,8,40,1,1,1,8,4,4,1> vci_param; 44 45 46 soclib::common::Loader loader(NULL); 56 typedef soclib::caba::VciParams<cell_width, 57 plen_width, 58 address_width, 59 error_width, 60 clen_width, 61 rflag_width, 62 srcid_width, 63 pktid_width, 64 trdid_width, 65 wrplen_width> vci_param; 66 67 //soclib::common::Loader loader(); 47 68 // Mapping table primary network 48 49 soclib::common::MappingTable maptab 0(40, IntTab(2,10), IntTab(2,3), 0x00C00000);50 soclib::common::MappingTable maptab1(40, IntTab(2,10), IntTab(2,3), 0x00C00000);51 52 53 //maptab0.add(Segment("mc_r0" , MC0_R_BASE , MC0_R_SIZE , IntTab(0,0), false, true, IntTab(0,0)));54 //maptab0.add(Segment("mc_m0" , MC0_M_BASE , MC0_M_SIZE , IntTab(0,0), true ));55 //maptab0.add(Segment("mc_r1" , MC1_R_BASE , MC1_R_SIZE , IntTab(1,0), false, true, IntTab(1,0)));56 //maptab0.add(Segment("mc_m1" , MC1_M_BASE , MC1_M_SIZE , IntTab(1,0), true));57 //maptab0.add(Segment("mc_r2" , MC2_R_BASE , MC2_R_SIZE , IntTab(2,0), false, true, IntTab(2,0)));58 //maptab0.add(Segment("mc_m2" , MC2_M_BASE , MC2_M_SIZE , IntTab(2,0), true ));59 //maptab0.add(Segment("mc_r3" , MC3_R_BASE , MC3_R_SIZE , IntTab(3,0), false, true, IntTab(3,0)));60 //maptab0.add(Segment("mc_m3" , MC3_M_BASE , MC3_M_SIZE , IntTab(3,0), true )); 69 soclib::common::MappingTable maptab0(address_width, IntTab(srcid_width-1 ,1), IntTab(srcid_width-1 ,1), 0xFFC0000); 70 soclib::common::MappingTable maptab1(address_width, IntTab(srcid_width-1 ,1), IntTab(srcid_width-1 ,1), 0xFFC0000); 71 for(int i = 0 ; i < Y_MAX ; i++){ 72 for(int j = 0 ; j < X_MAX ; j++){ 73 std::ostringstream str0; 74 std::ostringstream str1; 75 str0 << "Target_c0_" << (i*X_MAX+j) ; 76 str1 << "Target_c1_" << (i*X_MAX+j) ; 77 maptab0.add(Segment(str0.str(), TARGET_ADDR + ((i*X_MAX+j) << (address_width-srcid_width+1)), TARGET_SIZE, IntTab((i*X_MAX+j),0), false)); 78 maptab1.add(Segment(str1.str(), TARGET_ADDR + ((i*X_MAX+j) << (address_width-srcid_width+1)), TARGET_SIZE, IntTab((i*X_MAX+j),0), false)); 79 } 80 } 81 61 82 62 83 std::cout << maptab0 << std::endl; … … 66 87 sc_signal<bool> signal_resetn("resetn"); 67 88 68 soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c0 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth ", 2, N_CLUSTERS);69 soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c1 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth ", 2, N_CLUSTERS);89 soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c0 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth_c0", 2, N_CLUSTERS); 90 soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c1 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth_c1", 2, N_CLUSTERS); 70 91 /////////////////////////////////////////////////////////////// 71 92 // VDSPIN Signals : one level for in and out, one level for X length in the mesh, … … 83 104 soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c1 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ; 84 105 for(int i = 0 ; i < N_CLUSTERS ; i++){ // ringid, fifo, fifo, nb_init, nb_tgt 85 new(&local_ring_c0[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ("cluster_c0" + i,maptab0, IntTab(i), 2, 18, 1, 1); 86 new(&local_ring_c1[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ("cluster_c1" + i,maptab1, IntTab(i), 2, 18, 1, 1); 106 std::cout << "Passe " << i << " pour instanciation ring" << std::endl; 107 std::ostringstream str0; 108 std::ostringstream str1; 109 str0 << "cluster_c0_" << i ; 110 str1 << "cluster_c1_" << i ; 111 new(&local_ring_c0[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> (str0.str().c_str() ,maptab0, IntTab(i), 2, 18, 1, 1); 112 new(&local_ring_c1[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> (str1.str().c_str() ,maptab1, IntTab(i), 2, 18, 1, 1); 87 113 } 88 114 … … 94 120 routers_cmd[i] = (soclib::caba::VirtualDspinRouter<WIDTH_CMD> * ) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_CMD>) * X_MAX); 95 121 routers_rsp[i] = (soclib::caba::VirtualDspinRouter<WIDTH_RSP> * ) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_RSP>) * X_MAX); 96 for(int j = 0; j < X_MAX; i++){ 97 new(&routers_cmd[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_CMD> ("VDspinRouterCMD" + i + j, j, i, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), 4, 4); 98 new(&routers_rsp[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_RSP> ("VDspinRouterRSP" + i + j, j, i, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), 4, 4); 122 for(int j = 0; j < X_MAX; j++){ 123 std::cout << "Passe " << i << j << " pour instanciation vdspin" << std::endl; 124 new(&routers_cmd[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_CMD> ("VDspinRouterCMD" + i + j, j, i, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), 4, 4); 125 new(&routers_rsp[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_RSP> ("VDspinRouterRSP" + i + j, j, i, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), 4, 4); 99 126 } 100 127 } … … 110 137 for(int i = 0 ; i < Y_MAX; i++) 111 138 for(int j = 0 ; j < X_MAX ; j++){ 112 new(&initiator_c0[X_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> ("Initiator_c0" + (i*X_MAX+j), maptab0, IntTab(i,j), 16, 0.5, 2, X_MAX, Y_MAX ); //, 0, 0, 0, 0, 0); 113 new(&initiator_c1[X_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> ("Initiator_c1" + (i*X_MAX+j), maptab0, IntTab(i,j), 16, 0.5, 2, X_MAX, Y_MAX ); //, 0, 0, 0, 0, 0); 139 std::cout << "Passe " << i << j << " pour instanciation synthetic_init" << std::endl; 140 std::ostringstream str0; 141 std::ostringstream str1; 142 str0 << "Initiator_c0_" << (i*X_MAX+j) ; 143 str1 << "Initiator_c1_" << (i*X_MAX+j) ; 144 new(&initiator_c0[X_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str0.str().c_str() , maptab0, IntTab(i*X_MAX+j,0), 16, 0.5, 2, X_MAX, Y_MAX ); //, 0, 0, 0, 0, 0); 145 new(&initiator_c1[X_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str1.str().c_str() , maptab0, IntTab(i*X_MAX+j,0), 16, 0.5, 2, X_MAX, Y_MAX ); //, 0, 0, 0, 0, 0); 114 146 } 115 147 … … 118 150 for(int i = 0 ; i < Y_MAX ; i++) 119 151 for(int j = 0 ; j < X_MAX ; j++){ 120 new(&ram_c0[X_MAX*i+j]) soclib::caba::VciSimpleRam<vci_param> ("Ram_target_c0" + (i*X_MAX+j), IntTab(i,j), maptab0, loader, 0); 121 new(&ram_c1[X_MAX*i+j]) soclib::caba::VciSimpleRam<vci_param> ("Ram_target_c1" + (i*X_MAX+j), IntTab(i,j), maptab1, loader, 0); 152 std::cout << "Passe " << i << j << " pour instanciation Ram" << std::endl; 153 std::ostringstream str0; 154 std::ostringstream str1; 155 str0 << "Ram_c0_" << (i*X_MAX+j) ; 156 str1 << "Ram_c1_" << (i*X_MAX+j) ; 157 new(&ram_c0[X_MAX*i+j]) soclib::caba::VciSimpleRam<vci_param> (str0.str().c_str() , IntTab(i*X_MAX+j,0), maptab0, soclib::common::Loader(), 0); 158 new(&ram_c1[X_MAX*i+j]) soclib::caba::VciSimpleRam<vci_param> (str1.str().c_str() , IntTab(i*X_MAX+j,0), maptab1, soclib::common::Loader(), 0); 122 159 } 123 160 … … 252 289 int ncycles; 253 290 254 if (argc == 2) {255 ncycles = std::atoi(argv[1]);256 } else {257 std::cerr258 << std::endl259 << "The number of simulation cycles must "260 "be defined in the command line"261 << std::endl;262 exit(1);263 }264 265 291 sc_start(sc_core::sc_time(0, SC_NS)); 266 292 signal_resetn = false; … … 269 295 signal_resetn = true; 270 296 271 for (int i = 0; i < ncycles ; i+=100000) {297 while(1) { 272 298 sc_start(sc_core::sc_time(100000, SC_NS)); 273 274 } 275 276 std::cout << "Hit ENTER to end simulation" << std::endl; 277 char buf[1]; 278 279 std::cin.getline(buf,1); 299 } 300 280 301 return EXIT_SUCCESS; 281 302 }
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