Index: /trunk/modules/sdmmc/caba/source/include/sdmmc.h =================================================================== --- /trunk/modules/sdmmc/caba/source/include/sdmmc.h (revision 1051) +++ /trunk/modules/sdmmc/caba/source/include/sdmmc.h (revision 1052) @@ -55,28 +55,34 @@ // Registers - int spi_fsm; // SPI state register - int spi_shiftreg; // data shift in/out - int spi_bitcount; - int spi_clk; - int spi_mosi_previous; // sampled MOSI value + int spi_fsm; // SPI state register + int spi_shiftreg; // data shift in/out + int spi_bitcount; + int spi_clk; + int spi_mosi_previous; // sampled MOSI value - uint8_t command; + uint8_t command; uint32_t args; - uint8_t cmdcrc; + uint8_t cmdcrc; + int m_fd; // File descriptor uint64_t m_device_size; // Total number of blocks const uint32_t m_latency; // device latency - uint8_t m_databuf[1 /* reponse */ + 1 /* data tocken */ + 512 /* data block */ + 2 /* CRC */ ]; - uint32_t m_datalen_snd; // data size to be sent to host - uint32_t m_datalen_rcv; // data size expected from host + uint8_t m_databuf[1 /* reponse */ + + 1 /* data tocken */ + + 512 /* data block */ + + 2 /* CRC */ ]; + + uint32_t m_datalen_snd; // data size to be sent to host + uint32_t m_datalen_rcv; // data size expected from host uint32_t m_data_idx; - bool m_acmd; // next command will be acmd - int m_sdstate; // sdcard internal state + bool m_acmd; // next command will be acmd + int m_sdstate; // sdcard internal state // sd states - enum { - SD_IDLE = 0, - SD_READY = 1, + enum + { + SD_IDLE = 0, + SD_READY = 1, }; @@ -88,5 +94,6 @@ // Master FSM states - enum { + enum + { S_IDLE = 0, S_RECEIVE_CMD = 1, Index: /trunk/modules/sdmmc/caba/source/src/sdmmc.cpp =================================================================== --- /trunk/modules/sdmmc/caba/source/src/sdmmc.cpp (revision 1051) +++ /trunk/modules/sdmmc/caba/source/src/sdmmc.cpp (revision 1052) @@ -46,379 +46,439 @@ { spi_fsm = S_IDLE; - m_acmd = false; - m_sdstate = SD_IDLE; + m_acmd = false; + m_sdstate = SD_IDLE; return; } - if (p_spi_ss.read()) { - if (spi_fsm != S_IDLE) { - std::cerr << name() << " deselect but not idle, state " - << std::dec << spi_fsm << " last cmd " << (int)command - << " args " << std::hex << args << std::dec - << " bitcount " << (int)spi_bitcount - << " idx " << m_data_idx << " len_snd " << m_datalen_snd - << " len_rcv " << m_datalen_rcv << std::endl; - } - spi_fsm = S_IDLE; - spi_clk = p_spi_clk; - spi_mosi_previous = p_spi_mosi; - return; + + if (p_spi_ss.read()) + { + if (spi_fsm != S_IDLE) + { + std::cerr << name() << " deselect but not idle, state " + << std::dec << spi_fsm << " last cmd " << (int)command + << " args " << std::hex << args << std::dec + << " bitcount " << (int)spi_bitcount + << " idx " << m_data_idx << " len_snd " << m_datalen_snd + << " len_rcv " << m_datalen_rcv << std::endl; + } + spi_fsm = S_IDLE; + spi_clk = p_spi_clk; + spi_mosi_previous = p_spi_mosi; + return; } - switch(spi_fsm) { - case S_IDLE: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - command = (command << 1) | spi_mosi_previous; - spi_bitcount = 6; - spi_fsm = S_RECEIVE_CMD; - } - break; - case S_RECEIVE_CMD: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - command = (command << 1) | spi_mosi_previous; - if (spi_bitcount == 0) { - if ((command & 0x80) == 0) { - spi_fsm = S_RECEIVE_ARGS_START; - } else { + switch(spi_fsm) + { + case S_IDLE: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + command = (command << 1) | spi_mosi_previous; + spi_bitcount = 6; + spi_fsm = S_RECEIVE_CMD; + } + break; + case S_RECEIVE_CMD: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + command = (command << 1) | spi_mosi_previous; + if (spi_bitcount == 0) + { + if ((command & 0x80) == 0) + { + spi_fsm = S_RECEIVE_ARGS_START; + } + else + { #ifdef SOCLIB_MODULE_DEBUG0 std::cout << name() << " S_RECEIVE_CMD " << std::hex << (int)command << std::endl; #endif - spi_fsm = S_IDLE; - } - } else { - spi_bitcount = spi_bitcount - 1; - } - } - break; - case S_RECEIVE_ARGS_START: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - args = (args << 1) | spi_mosi_previous; - spi_bitcount = 30; - spi_fsm = S_RECEIVE_ARGS; - } - break; - case S_RECEIVE_ARGS: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - args = (args << 1) | spi_mosi_previous; - if (spi_bitcount == 0) { - spi_bitcount = 7; - spi_fsm = S_RECEIVE_CRC; - } else { - spi_bitcount = spi_bitcount - 1; - } - } - break; - case S_RECEIVE_CRC: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - cmdcrc = (cmdcrc << 1) | spi_mosi_previous; - if (spi_bitcount == 0) { - handle_sdmmc_cmd(command, args); - spi_bitcount = 0; // SEND_DATA will reset it - spi_fsm = S_SEND_DATA; - m_data_idx = 0; - } else { - spi_bitcount = spi_bitcount - 1; - } - } - break; + spi_fsm = S_IDLE; + } + } + else + { + spi_bitcount = spi_bitcount - 1; + } + } + break; + case S_RECEIVE_ARGS_START: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + args = (args << 1) | spi_mosi_previous; + spi_bitcount = 30; + spi_fsm = S_RECEIVE_ARGS; + } + break; + case S_RECEIVE_ARGS: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + args = (args << 1) | spi_mosi_previous; + if (spi_bitcount == 0) + { + spi_bitcount = 7; + spi_fsm = S_RECEIVE_CRC; + } + else + { + spi_bitcount = spi_bitcount - 1; + } + } + break; + case S_RECEIVE_CRC: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + cmdcrc = (cmdcrc << 1) | spi_mosi_previous; + if (spi_bitcount == 0) + { + handle_sdmmc_cmd(command, args); + spi_bitcount = 0; // SEND_DATA will reset it + spi_fsm = S_SEND_DATA; + m_data_idx = 0; + } + else + { + spi_bitcount = spi_bitcount - 1; + } + } + break; - case S_SEND_DATA: - if (p_spi_clk.read() == 0 && spi_clk == 1) { - // falling edge - if (spi_bitcount == 0) { - if (m_data_idx != m_datalen_snd) { - spi_shiftreg = m_databuf[m_data_idx]; - spi_bitcount = 7; - spi_fsm = S_SEND_DATA; - m_data_idx++; + case S_SEND_DATA: + if (p_spi_clk.read() == 0 && spi_clk == 1) // falling edge + { + if (spi_bitcount == 0) + { + if (m_data_idx != m_datalen_snd) + { + spi_shiftreg = m_databuf[m_data_idx]; + spi_bitcount = 7; + spi_fsm = S_SEND_DATA; + m_data_idx++; #ifdef SOCLIB_MODULE_DEBUG0 std::cout << name() << " S_SEND_DATA " << std::dec << m_datalen_snd << " idx " << m_data_idx << " " << std::hex << (uint32_t)m_databuf[m_data_idx] << std::endl; #endif - } else if (m_datalen_rcv != 0) { - spi_fsm = S_RECEIVE_DATA_WAIT; - spi_bitcount = 7; - m_data_idx = 0; - } else { - spi_fsm = S_IDLE; - } - } else { - spi_bitcount = spi_bitcount - 1; - spi_shiftreg = spi_shiftreg << 1; - } - } - break; - case S_RECEIVE_DATA_WAIT: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - uint8_t s_data; - s_data = (m_databuf[0] << 1) | spi_mosi_previous; - m_databuf[0] = s_data; - if (spi_bitcount == 0) { + } + else if (m_datalen_rcv != 0) + { + spi_fsm = S_RECEIVE_DATA_WAIT; + spi_bitcount = 7; + m_data_idx = 0; + } + else + { + spi_fsm = S_IDLE; + } + } + else + { + spi_bitcount = spi_bitcount - 1; + spi_shiftreg = spi_shiftreg << 1; + } + } + break; + ///////////////////////// + case S_RECEIVE_DATA_WAIT: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + uint8_t s_data; + s_data = (m_databuf[0] << 1) | spi_mosi_previous; + m_databuf[0] = s_data; + if (spi_bitcount == 0) + { #ifdef SOCLIB_MODULE_DEBUG - std::cout << name() << " S_RECEIVE_DATA_WAIT " << std::dec << (int)s_data << std::endl; -#endif - spi_bitcount = 7; - if (s_data == 0xfe) { // data start token - spi_fsm = S_RECEIVE_DATA; - m_data_idx = 1; - } else { +std::cout << name() << " S_RECEIVE_DATA_WAIT " << std::dec << (int)s_data << std::endl; +#endif + spi_bitcount = 7; + if (s_data == 0xfe) // data start token + { + spi_fsm = S_RECEIVE_DATA; + m_data_idx = 1; + } + else + { #ifdef SOCLIB_MODULE_DEBUG - std::cout << name() << " S_RECEIVE_DATA_WAIT " << std::hex << (int)s_data << std::endl; -#endif - spi_fsm = S_RECEIVE_DATA_WAIT; - } - } else { - spi_bitcount = spi_bitcount - 1; - } - } - break; - case S_RECEIVE_DATA: - if (p_spi_clk.read() == 1 && spi_clk == 0) { - // rising edge - m_databuf[m_data_idx] = (m_databuf[m_data_idx] << 1) | spi_mosi_previous; - if (spi_bitcount == 0) { - m_data_idx++; - if (m_data_idx != m_datalen_rcv) { - spi_fsm = S_RECEIVE_DATA; - spi_bitcount = 7; - } else { - handle_sdmmc_write(command, args); - if (m_datalen_snd > 0) { - spi_bitcount = 0; // SEND_DATA will reset it - spi_fsm = S_SEND_DATA; - m_data_idx = 0; - } else { - spi_fsm = S_IDLE; - } - } - } else { - spi_bitcount = spi_bitcount - 1; - } - } +std::cout << name() << " S_RECEIVE_DATA_WAIT " << std::hex << (int)s_data << std::endl; +#endif + spi_fsm = S_RECEIVE_DATA_WAIT; + } + } + else + { + spi_bitcount = spi_bitcount - 1; + } + } + break; + //////////////////// + case S_RECEIVE_DATA: + if (p_spi_clk.read() == 1 && spi_clk == 0) // rising edge + { + m_databuf[m_data_idx] = (m_databuf[m_data_idx] << 1) | spi_mosi_previous; + if (spi_bitcount == 0) + { + m_data_idx++; + if (m_data_idx != m_datalen_rcv) + { + spi_fsm = S_RECEIVE_DATA; + spi_bitcount = 7; + } + else + { + handle_sdmmc_write(command, args); + if (m_datalen_snd > 0) + { + spi_bitcount = 0; // SEND_DATA will reset it + spi_fsm = S_SEND_DATA; + m_data_idx = 0; + } + else + { + spi_fsm = S_IDLE; + } + } + } + else + { + spi_bitcount = spi_bitcount - 1; + } + } + break; + } // end switch spi_fsm + + //// now generate output signal + + switch(spi_fsm) + { + case S_IDLE: + p_spi_miso = !p_spi_ss.read(); + break; + + case S_SEND_DATA: + p_spi_miso = (spi_shiftreg & 0x80) != 0; break; + + default: + p_spi_miso = !p_spi_ss.read(); + break; } -//// now genrate output signal - - switch(spi_fsm) { - case S_IDLE: - p_spi_miso = !p_spi_ss.read(); - break; - case S_SEND_DATA: - p_spi_miso = (spi_shiftreg & 0x80) != 0; - break; - default: - p_spi_miso = !p_spi_ss.read(); - break; - } + //// sample inputs spi_clk = p_spi_clk.read(); spi_mosi_previous = p_spi_mosi; + } // end GenMealy() -////////////////////// +//////////////////////////////////////////////////////// void SdMMC::handle_sdmmc_cmd(uint8_t cmd, uint32_t data) { m_datalen_rcv = 0; - m_databuf[0] = 0x04; // illegal command - m_datalen_snd = 1; + m_databuf[0] = 0x04; // default value : illegal command + m_datalen_snd = 1; // default value : 1 byte if (m_sdstate == SD_IDLE) m_databuf[0] |= 0x01; // idle - if ((cmd & 0x40) == 0) { + if ((cmd & 0x40) == 0) + { //illegal command return; } cmd &= 0x3f; - if (m_acmd) { + + if (m_acmd) + { #ifdef SOCLIB_MODULE_DEBUG0 - std::cout << name() << " new acmd " << std::dec << (int)cmd << " args " << std::hex << data << " crc " << (int)cmdcrc << std::endl; +std::cout << name() << " new acmd " << std::dec << (int)cmd << " args " << std::hex << data << " crc " << (int)cmdcrc << std::endl; #endif m_acmd = false; - switch (cmd) { - case 41: - m_databuf[0] = 0x0; // card ready - m_datalen_snd = 1; - m_sdstate = SD_READY; - break; - case 51: - // send SCR - m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 - m_databuf[ 1] = 0xfe; // data token - m_databuf[ 2] = 0x00; // SCR_STRUCTURE / SD_SPEC - m_databuf[ 3] = 0x05; // DATA_STAT_AFTER_ERASE, SD_SECURITY, SD_BUS_WIDTHS - m_databuf[ 4] = 0; // SD_SPEC3, EX_SECURITY, SD_SPEC4 - m_databuf[ 5] = 0; // CMD_SUPPORT - m_databuf[ 6] = 0; // vendor specific - m_databuf[ 7] = 0; // vendor specific - m_databuf[ 8] = 0; // vendor specific - m_databuf[ 9] = 0; // vendor specific - m_databuf[10] = 0x0; // CRC16 - m_databuf[11] = 0x0; // CRC16 - m_datalen_snd = 12; - break; - default: - std::cout << name() << " unknown acmd " << std::dec - << (int)cmd << std::endl; - break; // return illegal command + switch (cmd) + { + case 41: // ACD41 : Send OP_COND + m_databuf[0] = 0x0; // card ready + m_datalen_snd = 1; + m_sdstate = SD_READY; + break; + case 51: // send SCR + m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[ 1] = 0xfe; // data token + m_databuf[ 2] = 0x00; // SCR_STRUCTURE / SD_SPEC + m_databuf[ 3] = 0x05; // DATA_STAT_AFTER_ERASE, SD_SECURITY, SD_BUS_WIDTHS + m_databuf[ 4] = 0; // SD_SPEC3, EX_SECURITY, SD_SPEC4 + m_databuf[ 5] = 0; // CMD_SUPPORT + m_databuf[ 6] = 0; // vendor specific + m_databuf[ 7] = 0; // vendor specific + m_databuf[ 8] = 0; // vendor specific + m_databuf[ 9] = 0; // vendor specific + m_databuf[10] = 0x0; // CRC16 + m_databuf[11] = 0x0; // CRC16 + m_datalen_snd = 12; + break; + default: + std::cout << name() << " unknown acmd " << std::dec + << (int)cmd << std::endl; + break; // return illegal command } - } else { + } + else + { #ifdef SOCLIB_MODULE_DEBUG0 - std::cout << name() << " new cmd " << std::dec << (int)cmd << " args " << std::hex << data << " crc " << (int)cmdcrc << std::endl; -#endif - switch (cmd) { - case 0: - m_databuf[0] = 0x1; - m_datalen_snd = 1; - m_sdstate = SD_IDLE; - break; - case 8: - // reply with illegal command for now - break; - case 9: - { - // send CSD - // we use a block len of 1024 - uint32_t csize = ((m_device_size + (512 * 1024) - 1) / (512 * 1024)) - 1; - m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 - m_databuf[ 1] = 0xfe; // data token - m_databuf[ 2] = 0x00; // CSD_STRUCTURE - m_databuf[ 3] = 0xe; // TAAC - m_databuf[ 4] = 0; // NSAC - m_databuf[ 5] = 0x32; // TRAN_SPEED - m_databuf[ 6] = 0x5b; // CCC_H - m_databuf[ 7] = 0x5a; // CCC_L + READ_BL_LEN - m_databuf[ 8] = 0x80; // READ_BL_PARTIAL, R/W_BLK_MISALIGN, DSR_IMP - m_databuf[ 8] |= (csize >> 10) & 0x03; // CSIZE[12-11] - m_databuf[ 9] = (csize >> 2) & 0xff; // CSIZE[10-2] - m_databuf[10] = (csize << 6) & 0xc0; // CSIZE[1-0] - m_databuf[10] |= 0; // R_CURR_MIN, R_CURR_MAX - m_databuf[11] = 0x3; // W_CURR_MIN, W_CURR_MAX, CSIZE_MULT[2-1]; - m_databuf[12] = 0xff; // CSIZE_MULT[1], ERASE_BLK_EN, ERASE_SECTOR_SIZE[6-1] - m_databuf[13] = 0x80; // ERASE_SECTOR_SIZE[0]. WP_GRP_SIZE - m_databuf[14] = 0x0a; // WP_GRP_ENABLE, R2W_FACTOR, WRITE_BL_LEN[2-3] - m_databuf[15] = 0x40; // WRITE_BL_LEN[0-1], WR_BL_PARTIAL - m_databuf[16] = 0; // FILE_FORMAT - m_databuf[17] = 0x1; // CRC7 - m_databuf[18] = 0x0; // CRC16 - m_databuf[19] = 0x0; // CRC16 - m_datalen_snd = 20; - break; - } - case 10: - // send CID - m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 - m_databuf[ 1] = 0xfe; // data token - m_databuf[ 2] = 0xda; // MID - m_databuf[ 3] = 'P'; // OID - m_databuf[ 4] = '6'; // OID - m_databuf[ 5] = 's'; // PNM - m_databuf[ 6] = 'o'; // PNM - m_databuf[ 7] = 'c'; // PNM - m_databuf[ 8] = 's'; // PNM - m_databuf[ 9] = 'd'; // PNM - m_databuf[10] = 0x01; // PRV - m_databuf[11] = 0xde; // PSN - m_databuf[12] = 0xad; // PSN - m_databuf[13] = 0xbe; // PSN - m_databuf[14] = 0xef; // PSN - m_databuf[15] = 10; // MDT - m_databuf[16] = 13; // MDT - m_databuf[17] = 0x1; // CRC7 - m_databuf[18] = 0x0; // CRC16 - m_databuf[19] = 0x0; // CRC16 - m_datalen_snd = 20; - break; - case 16: - // set block size - if (m_sdstate != SD_IDLE && data == 512) { - m_databuf[0] = 0x00; - m_datalen_snd = 1; - } // else illegal command - break; - case 17: - { - int ret; - // read data block - if (m_sdstate == SD_IDLE) { - // return illegal command - return; - } - if (data >= m_device_size) { - std::cerr << name() << " read: request " << data - << " past end of file " << m_device_size << std::endl; - m_databuf[0] = 0x00; // R1 OK - m_databuf[1] = 0x08; // error tocken "out of range" - m_datalen_snd = 2; - return; - } - do { - if (lseek(m_fd, data, SEEK_SET) < 0) { - std::cerr << name() << " lseek: " << - strerror(errno) << std::endl; - m_databuf[0] = 0x00; // R1 OK - m_databuf[1] = 0x02; // error tocken "CC err" - m_datalen_snd = 2; - return; - } - ret = read(m_fd, &m_databuf[2], 512); - } while (ret < 0 && errno == EINTR); - if (ret < 0) { - std::cerr << name() << " read: " << - strerror(errno) << std::endl; - m_databuf[0] = 0x00; // R1 OK - m_databuf[1] = 0x04; // error tocken "card ECC failed" - m_datalen_snd = 2; - return; - } - m_databuf[514] = m_databuf[515] = 0; // XXX CRC - m_databuf[0] = 0x0; // R1 - m_databuf[1] = 0xfe; // start block tocken - m_datalen_snd = 516; - break; - } - case 24: - { - // write data block - if (m_sdstate == SD_IDLE) { - // return illegal command - return; - } +std::cout << name() << " new cmd " << std::dec << (int)cmd << " args " << std::hex << data << " crc " << (int)cmdcrc << std::endl; +#endif + switch (cmd) + { + /////// + case 0: // CMD0 + m_databuf[0] = 0x1; + m_datalen_snd = 1; + m_sdstate = SD_IDLE; + break; + /////// + case 8: // CMD8 + // reply with illegal command for now + break; + /////// + case 9: // CMD9 : send CSD + { + // we use a block len of 1024 + uint32_t csize = ((m_device_size + (512 * 1024) - 1) / (512 * 1024)) - 1; + m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[ 1] = 0xfe; // data token + m_databuf[ 2] = 0x00; // CSD_STRUCTURE + m_databuf[ 3] = 0xe; // TAAC + m_databuf[ 4] = 0; // NSAC + m_databuf[ 5] = 0x32; // TRAN_SPEED + m_databuf[ 6] = 0x5b; // CCC_H + m_databuf[ 7] = 0x5a; // CCC_L + READ_BL_LEN + m_databuf[ 8] = 0x80; // READ_BL_PARTIAL, R/W_BLK_MISALIGN, DSR_IMP + m_databuf[ 8] |= (csize >> 10) & 0x03; // CSIZE[12-11] + m_databuf[ 9] = (csize >> 2) & 0xff; // CSIZE[10-2] + m_databuf[10] = (csize << 6) & 0xc0; // CSIZE[1-0] + m_databuf[10] |= 0; // R_CURR_MIN, R_CURR_MAX + m_databuf[11] = 0x3; // W_CURR_MIN, W_CURR_MAX, CSIZE_MULT[2-1]; + m_databuf[12] = 0xff; // CSIZE_MULT[1], ERASE_BLK_EN, ERASE_SECTOR_SIZE[6-1] + m_databuf[13] = 0x80; // ERASE_SECTOR_SIZE[0]. WP_GRP_SIZE + m_databuf[14] = 0x0a; // WP_GRP_ENABLE, R2W_FACTOR, WRITE_BL_LEN[2-3] + m_databuf[15] = 0x40; // WRITE_BL_LEN[0-1], WR_BL_PARTIAL + m_databuf[16] = 0; // FILE_FORMAT + m_databuf[17] = 0x1; // CRC7 + m_databuf[18] = 0x0; // CRC16 + m_databuf[19] = 0x0; // CRC16 + m_datalen_snd = 20; + } + break; + //////// + case 10: // CMD10 : send CID + m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[ 1] = 0xfe; // data token + m_databuf[ 2] = 0xda; // MID + m_databuf[ 3] = 'P'; // OID + m_databuf[ 4] = '6'; // OID + m_databuf[ 5] = 's'; // PNM + m_databuf[ 6] = 'o'; // PNM + m_databuf[ 7] = 'c'; // PNM + m_databuf[ 8] = 's'; // PNM + m_databuf[ 9] = 'd'; // PNM + m_databuf[10] = 0x01; // PRV + m_databuf[11] = 0xde; // PSN + m_databuf[12] = 0xad; // PSN + m_databuf[13] = 0xbe; // PSN + m_databuf[14] = 0xef; // PSN + m_databuf[15] = 10; // MDT + m_databuf[16] = 13; // MDT + m_databuf[17] = 0x1; // CRC7 + m_databuf[18] = 0x0; // CRC16 + m_databuf[19] = 0x0; // CRC16 + m_datalen_snd = 20; + break; + //////// + case 16: // CMD16 : set block size + if (m_sdstate != SD_IDLE && data == 512) + { + m_databuf[0] = 0x00; + m_datalen_snd = 1; + } // else illegal command + break; + //////// + case 17: // CMD17 : read data block + { + int ret; + if (m_sdstate == SD_IDLE) // return illegal command + { + return; + } + if (data >= m_device_size) // return "out of range" + { + std::cerr << name() << " read: request " << data + << " past end of file " << m_device_size << std::endl; + m_databuf[0] = 0x00; // R1 OK + m_databuf[1] = 0x08; // error tocken "out of range" + m_datalen_snd = 2; + return; + } + do + { + if (lseek(m_fd, data, SEEK_SET) < 0) + { + std::cerr << name() << " lseek: " << + strerror(errno) << std::endl; + m_databuf[0] = 0x00; // R1 OK + m_databuf[1] = 0x02; // error tocken "CC err" + m_datalen_snd = 2; + return; + } + ret = read(m_fd, &m_databuf[2], 512); + } while (ret < 0 && errno == EINTR); + if (ret < 0) + { + std::cerr << name() << " read: " << strerror(errno) << std::endl; + m_databuf[0] = 0x00; // R1 OK + m_databuf[1] = 0x04; // error tocken "card ECC failed" + m_datalen_snd = 2; + return; + } + m_databuf[514] = m_databuf[515] = 0; // XXX CRC + m_databuf[0] = 0x0; // R1 + m_databuf[1] = 0xfe; // start block tocken + m_datalen_snd = 516; + } + break; + //////// + case 24: // CMD 24 : write data block + { + if (m_sdstate == SD_IDLE) // return illegal command + { + return; + } #ifdef SOCLIB_MODULE_DEBUG std::cout << name() << " new cmd write " << std::dec << (int)cmd << " args " << std::hex << data << std::endl; #endif - m_databuf[0] = 0x0; // R1 - m_datalen_snd = 1; - m_datalen_rcv = 512 + 2 + 1; // data + tocken + CRC - break; - } - case 55: - // app-specific command follow - m_acmd = true; - m_databuf[0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; - m_datalen_snd = 1; - break; - case 58: - // send OCR - m_databuf[4] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 - m_databuf[3] = 0x80; // power up complete, SDSC - m_databuf[2] = 0xff; // all voltages supported - m_databuf[1] = 0x00; - m_databuf[0] = 0x00; - m_datalen_snd = 5; - break; - default: - std::cout << name() << " unknown cmd " << std::dec - << (int)cmd << std::endl; - break; // return illegal command + m_databuf[0] = 0x0; // R1 + m_datalen_snd = 1; + m_datalen_rcv = 512 + 2 + 1; // data + tocken + CRC + } + break; + //////// + case 55: // CMD55 : app-specific command follow + m_acmd = true; + m_databuf[0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; + m_datalen_snd = 1; + break; + //////// + case 58: // CMD 58 : send OCR + m_databuf[4] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[3] = 0x80; // power up complete, SDSC + m_databuf[2] = 0xff; // all voltages supported + m_databuf[1] = 0x00; + m_databuf[0] = 0x00; + m_datalen_snd = 5; + break; + //////// + default: // return illegal command + std::cout << name() << " unknown cmd " << std::dec << (int)cmd << std::endl; + break; } } -} - +} // end handle_sdmmc_cmd() + +/////////////////////////////////////////////////////////// void SdMMC::handle_sdmmc_write(uint8_t cmd, uint32_t data) { @@ -428,52 +488,56 @@ std::cout << name() << " cmd write " << std::dec << (int)cmd << " args " << std::hex << data << std::endl; #endif - switch(cmd) { - case 24: - { - int ret; - // write data block - assert(m_sdstate != SD_IDLE && "can't write in idle state"); - if (data >= m_device_size) { - std::cerr << name() << " write: request " << data - << " past end of file " << m_device_size << std::endl; - m_databuf[0] = 0xd; // write error - m_datalen_snd = 1; - return; - } - do { - if (lseek(m_fd, data, SEEK_SET) < 0) { - std::cerr << name() << " lseek: " << - strerror(errno) << std::endl; - m_databuf[0] = 0xd; // write error - m_datalen_snd = 1; - return; - } - ret = write(m_fd, &m_databuf[1], 512); - } while (ret < 0 && errno == EINTR); - if (ret < 0) { - std::cerr << name() << " write: " << - strerror(errno) << std::endl; - m_databuf[0] = 0xd; // write error - m_datalen_snd = 1; - return; - } - m_databuf[0] = 0x5; // write complete - m_databuf[1] = 0x0; // busy - m_datalen_snd = 2; + switch(cmd) + { + case 24: // CMD24 : write data block + { + int ret; + assert(m_sdstate != SD_IDLE && "can't write in idle state"); + if (data >= m_device_size) + { + std::cerr << name() << " write: request " << data + << " past end of file " << m_device_size << std::endl; + m_databuf[0] = 0xd; // write error + m_datalen_snd = 1; + return; + } + do + { + if (lseek(m_fd, data, SEEK_SET) < 0) + { + std::cerr << name() << " lseek: " << strerror(errno) << std::endl; + m_databuf[0] = 0xd; // write error + m_datalen_snd = 1; + return; + } + ret = write(m_fd, &m_databuf[1], 512); + } + while (ret < 0 && errno == EINTR); + if (ret < 0) + { + std::cerr << name() << " write: " << strerror(errno) << std::endl; + m_databuf[0] = 0xd; // write error + m_datalen_snd = 1; + return; + } + m_databuf[0] = 0x5; // write complete + m_databuf[1] = 0x0; // busy + m_datalen_snd = 2; + } break; - } default: - std::cerr << name() << " unkown write cmd " << std::dec << - (int)cmd << std::endl; - m_databuf[0] = 0xd; // write error; - m_datalen_snd = 1; + { + std::cerr << name() << " unkown write cmd " << std::dec << (int)cmd << std::endl; + m_databuf[0] = 0xd; // write error; + m_datalen_snd = 1; + } } return; } -////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// SdMMC::SdMMC( sc_core::sc_module_name name, - const std::string &filename, - const uint32_t latency) + const std::string &filename, + const uint32_t latency) : caba::BaseModule(name), @@ -516,13 +580,13 @@ const char* spi_str[] = { - "S_IDLE", - "S_RECEIVE_CMD", - "S_RECEIVE_ARGS_START", - "S_RECEIVE_ARGS", - "S_RECEIVE_CRC", - "S_RECEIVE_DATA_START", - "S_RECEIVE_DATA", - "S_SEND_DATA", - "S_NOP", + "S_IDLE", + "S_RECEIVE_CMD", + "S_RECEIVE_ARGS_START", + "S_RECEIVE_ARGS", + "S_RECEIVE_CRC", + "S_RECEIVE_DATA_START", + "S_RECEIVE_DATA", + "S_SEND_DATA", + "S_NOP", }; if (spi_clk != p_spi_clk.read()) { Index: /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp =================================================================== --- /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp (revision 1051) +++ /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp (revision 1052) @@ -875,21 +875,21 @@ const char* target_str[] = { - "TGT_IDLE", - "TGT_WRITE_BUFFER", - "TGT_READ_BUFFER", - "TGT_WRITE_BUFFER_EXT", - "TGT_READ_BUFFER_EXT", - "TGT_WRITE_COUNT", - "TGT_READ_COUNT", - "TGT_WRITE_LBA", - "TGT_READ_LBA", - "TGT_WRITE_OP", - "TGT_READ_STATUS", - "TGT_WRITE_IRQEN", - "TGT_READ_IRQEN", - "TGT_READ_SIZE", - "TGT_READ_BLOCK", - "TGT_READ_ERROR", - "TGT_WRITE_ERROR ", + "TGT_IDLE", // 0 + "TGT_WRITE_BUFFER", // 1 + "TGT_READ_BUFFER", // 2 + "TGT_WRITE_BUFFER_EXT", // 3 + "TGT_READ_BUFFER_EXT", // 4 + "TGT_WRITE_COUNT", // 5 + "TGT_READ_COUNT", // 6 + "TGT_WRITE_LBA", // 7 + "TGT_READ_LBA", // 8 + "TGT_WRITE_STATUS", // 9 + "TGT_READ_STATUS", // 10 + "TGT_WRITE_IRQEN", // 11 + "TGT_READ_IRQEN", // 12 + "TGT_WRITE_OP", // 13 + "TGT_READ_SIZE", // 14 + "TGT_READ_BLOCK", // 15 + "TGT_ERROR", // 16 }; Index: /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 1051) +++ /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 1052) @@ -4761,6 +4761,7 @@ { std::cout << " " - << " Select a victim slot: " - << " way = " << std::dec << way + << " Select a victim line: " << std::hex + << " paddr = " << (r_xram_rsp_victim_nline.read() * m_words * 4) + << " / way = " << std::dec << way << " / set = " << set << " / inval_required = " << inval << std::endl; Index: /trunk/modules/vci_mem_cache/include/soclib/mem_cache.h =================================================================== --- /trunk/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 1051) +++ /trunk/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 1052) @@ -178,9 +178,9 @@ enum SoclibMemCacheRerrorRegs { - MEMC_RERROR_ADDR_LO = 0, - MEMC_RERROR_ADDR_HI, - MEMC_RERROR_SRCID, - MEMC_RERROR_IRQ_RESET, - MEMC_RERROR_IRQ_ENABLE + MEMC_RERROR_ADDR_LO = 0, + MEMC_RERROR_ADDR_HI = 1, + MEMC_RERROR_SRCID = 2, + MEMC_RERROR_IRQ_RESET = 3, + MEMC_RERROR_IRQ_ENABLE = 4, }; Index: /trunk/modules/vci_spi/caba/source/include/vci_spi.h =================================================================== --- /trunk/modules/vci_spi/caba/source/include/vci_spi.h (revision 1051) +++ /trunk/modules/vci_spi/caba/source/include/vci_spi.h (revision 1052) @@ -68,25 +68,25 @@ // Registers - sc_signal r_target_fsm; // target fsm state register - sc_signal r_initiator_fsm; // initiator fsm state register - sc_signal r_spi_fsm; // spi engine state - sc_signal r_txrx[2]; // data in/out - sc_signal r_divider; // SPI clk divider - sc_signal r_ss; // SPI slave select - sc_signal r_ctrl_cpol; // clock polarity - sc_signal r_ctrl_cpha; // clock phase - sc_signal r_ctrl_ie; // interrupt enable - sc_signal r_ctrl_char_len; // number of bits in xfer - sc_signal r_buf_address; // memory buffer address - sc_signal r_dma_count; // DMA burst count - sc_signal r_read; // DMA read/write - - sc_signal r_burst_word; // DMA burst word count - sc_signal r_dma_error; // DMA error - - sc_signal r_spi_bsy; // SPI shifter busy - sc_signal r_spi_bit_count; - sc_signal r_spi_word_count; - sc_signal r_spi_clk_counter; + sc_signal r_target_fsm; // target fsm state register + sc_signal r_initiator_fsm; // initiator fsm state register + sc_signal r_spi_fsm; // spi engine state + sc_signal r_txrx[2]; // data in/out + sc_signal r_divider; // SPI clk divider + sc_signal r_ss; // SPI slave select + sc_signal r_ctrl_cpol; // clock polarity + sc_signal r_ctrl_cpha; // clock phase + sc_signal r_ctrl_ie; // interrupt enable + sc_signal r_ctrl_char_len; // number of bits in xfer + sc_signal r_buf_address; // memory buffer address + sc_signal r_dma_count; // DMA burst count + sc_signal r_read; // DMA read/write + + sc_signal r_burst_word; // DMA burst word count + sc_signal r_dma_error; // DMA error + + sc_signal r_spi_bsy; // SPI shifter busy + sc_signal r_spi_bit_count; + sc_signal r_spi_word_count; + sc_signal r_spi_clk_counter; sc_signal r_spi_clk; sc_signal r_spi_clk_previous; @@ -189,4 +189,5 @@ soclib::caba::VciInitiator p_vci_initiator; soclib::caba::VciTarget p_vci_target; + sc_out p_spi_ss; sc_out p_spi_clk; Index: /trunk/modules/vci_spi/caba/source/src/vci_spi.cpp =================================================================== --- /trunk/modules/vci_spi/caba/source/src/vci_spi.cpp (revision 1051) +++ /trunk/modules/vci_spi/caba/source/src/vci_spi.cpp (revision 1052) @@ -46,34 +46,34 @@ bool s_dma_bsy = (r_initiator_fsm != M_IDLE); + if(p_resetn.read() == false) { - r_initiator_fsm = M_IDLE; - r_target_fsm = T_IDLE; - r_spi_fsm = S_IDLE; - r_ss = 0; - r_divider = 0xffff; - r_ctrl_char_len = 0; - r_ctrl_ie = false; - r_ctrl_cpol = false; - r_ctrl_cpha = false; - r_spi_bsy = false; - r_dma_count = 0; - r_dma_error = false; - r_spi_clk_counter = 0xffff; - r_spi_clk = 0; - r_spi_done = false; - - r_irq = false; - r_read = false; - - r_dma_fifo_read.init(); - r_dma_fifo_write.init(); - - return; + r_initiator_fsm = M_IDLE; + r_target_fsm = T_IDLE; + r_spi_fsm = S_IDLE; + r_ss = 0; + r_divider = 0xffff; + r_ctrl_char_len = 0; + r_ctrl_ie = false; + r_ctrl_cpol = false; + r_ctrl_cpha = false; + r_spi_bsy = false; + r_dma_count = 0; + r_dma_error = false; + r_spi_clk_counter = 0xffff; + r_spi_clk = 0; + r_spi_done = false; + + r_irq = false; + r_read = false; + + r_dma_fifo_read.init(); + r_dma_fifo_write.init(); + + return; } ////////////////////////////////////////////////////////////////////////////// - // The Target FSM controls the following registers: - // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read + // The Target FSM handles the software access to addressable registers ////////////////////////////////////////////////////////////////////////////// @@ -81,96 +81,101 @@ r_spi_bsy = false; - switch(r_target_fsm) { + switch(r_target_fsm) + { //////////// case T_IDLE: { - if ( p_vci_target.cmdval.read() ) - { - r_srcid = p_vci_target.srcid.read(); - r_trdid = p_vci_target.trdid.read(); - r_pktid = p_vci_target.pktid.read(); - uint32_t wdata = p_vci_target.wdata.read(); - sc_dt::sc_uint address = p_vci_target.address.read(); - - bool found = false; - std::list::iterator seg; - for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) - { - if ( seg->contains(address) ) found = true; - } + if ( p_vci_target.cmdval.read() ) + { + r_srcid = p_vci_target.srcid.read(); + r_trdid = p_vci_target.trdid.read(); + r_pktid = p_vci_target.pktid.read(); + uint32_t wdata = p_vci_target.wdata.read(); + sc_dt::sc_uint address = p_vci_target.address.read(); + + bool found = false; + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + if ( seg->contains(address) ) found = true; + } - - if (not found) { - if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) - r_target_fsm = T_ERROR_WRITE; - else + if (not found) + { + if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) + r_target_fsm = T_ERROR_WRITE; + else + r_target_fsm = T_ERROR_READ; + } + else if (p_vci_target.cmd.read() != vci_param::CMD_READ && + p_vci_target.cmd.read() != vci_param::CMD_WRITE) + { r_target_fsm = T_ERROR_READ; - } else if (p_vci_target.cmd.read() != vci_param::CMD_READ && - p_vci_target.cmd.read() != vci_param::CMD_WRITE) { - r_target_fsm = T_ERROR_READ; - } else { - bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) & !r_spi_bsy &!s_dma_bsy; - uint32_t cell = (uint32_t)((address & 0x3F)>>2); - switch(cell) { - case SPI_DATA_TXRX0: - r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; - if (write) { - r_txrx[0] = - (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | - ((uint64_t)wdata); - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_DATA_TXRX1: - r_rdata = r_txrx[0] >> 32; - if (write) { - r_txrx[0] = - (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | - ((uint64_t)wdata << 32); - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_DATA_TXRX2: - r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; - if (write) { - r_txrx[1] = - (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | - ((uint64_t)wdata); - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_DATA_TXRX3: - r_rdata = r_txrx[1] >> 32; - if (write) { - r_txrx[1] = - (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | - ((uint64_t)wdata << 32); - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_CTRL: - { - uint32_t data = 0; - if (r_ctrl_cpol.read()) - data |= SPI_CTRL_CPOL; - if (r_ctrl_cpha.read()) - data |= SPI_CTRL_CPHA; - if (r_ctrl_ie.read()) - data |= SPI_CTRL_IE_EN; - if (r_spi_bsy.read()) - data |= SPI_CTRL_GO_BSY; - if (s_dma_bsy) - data |= SPI_CTRL_DMA_BSY; - if (r_dma_error) - data |= SPI_CTRL_DMA_ERR; - data |= (uint32_t)r_ctrl_char_len.read(); - r_rdata = data; - if (write) { - r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); - r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); - r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); - if (wdata & SPI_CTRL_GO_BSY) - r_spi_bsy = true; - r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); + } + else + { + bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) + & !r_spi_bsy & !s_dma_bsy; + uint32_t cell = (uint32_t)((address & 0x3F)>>2); + switch(cell) + { + case SPI_DATA_TXRX0: + r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; + if (write) + { + r_txrx[0] = (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | + ((uint64_t)wdata); + } + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX1: + r_rdata = r_txrx[0] >> 32; + if (write) + { + r_txrx[0] = (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | + ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX2: + r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; + if (write) + { + r_txrx[1] = (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | + ((uint64_t)wdata); + } + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX3: + r_rdata = r_txrx[1] >> 32; + if (write) + { + r_txrx[1] = (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | + ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_CTRL: + uint32_t data = 0; + if (r_ctrl_cpol.read()) data |= SPI_CTRL_CPOL; + if (r_ctrl_cpha.read()) data |= SPI_CTRL_CPHA; + if (r_ctrl_ie.read()) data |= SPI_CTRL_IE_EN; + if (r_spi_bsy.read()) data |= SPI_CTRL_GO_BSY; + if (s_dma_bsy) data |= SPI_CTRL_DMA_BSY; + if (r_dma_error) data |= SPI_CTRL_DMA_ERR; + data |= (uint32_t)r_ctrl_char_len.read(); + r_rdata = data; + if (write) + { + r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); + r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); + r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); + if (wdata & SPI_CTRL_GO_BSY) r_spi_bsy = true; + r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); + #ifdef SOCLIB_MODULE_DEBUG if ((wdata & SPI_CTRL_GO_BSY) != 0) { @@ -178,58 +183,61 @@ } #endif - } else { - r_irq = false; - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - } - case SPI_DIVIDER: - r_rdata = r_divider.read(); - if (write) { + } + else + { + r_irq = false; + } + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DIVIDER: + r_rdata = r_divider.read(); + if (write) r_divider = wdata; + #ifdef SOCLIB_MODULE_DEBUG std::cout << name() << " divider set to " << std::dec << wdata << std::endl; #endif - r_divider = wdata; - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_SS: - r_rdata = r_ss.read(); - if (write) { - r_ss = wdata; - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_DMA_BASE: - r_rdata = r_buf_address.read(); - if (write) { - r_buf_address = (r_buf_address & (uint64_t)0xffffffff00000000) | wdata; - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_DMA_BASEH: - r_rdata = r_buf_address >> 32; - if (write) { - r_buf_address = (r_buf_address & (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32); - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - case SPI_DMA_COUNT: - r_rdata = (r_dma_count.read() << m_byte2burst_shift) | - r_read; - if (write) { - r_read = (wdata & 0x1); - r_dma_count = wdata >> m_byte2burst_shift; - r_ctrl_char_len = vci_param::B * 8; - } - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; - break; - default: - r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; - break; - } - } - } - break; + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_SS: + r_rdata = r_ss.read(); + if (write) r_ss = wdata; + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DMA_BASE: + r_rdata = r_buf_address.read(); + if (write) r_buf_address = (r_buf_address.read & + (uint64_t)0xffffffff00000000) | wdata; + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DMA_BASEH: + r_rdata = r_buf_address >> 32; + if (write) r_buf_address = (r_buf_address & + (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32); + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DMA_COUNT: + r_rdata = (r_dma_count.read() << m_byte2burst_shift) | r_read; + if (write) + { + r_read = (wdata & 0x1); + r_dma_count = wdata >> m_byte2burst_shift; + r_ctrl_char_len = vci_param::B * 8; + } + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + default: + r_target_fsm = (p_vci_target.cmd.read() + == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; + break; + } + } + } + break; } //////////////////// @@ -238,8 +246,8 @@ case T_ERROR_READ: case T_ERROR_WRITE: - if (p_vci_target.rspack.read() ) { - r_target_fsm = T_IDLE; - } - break; + { + if (p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + break; + } } // end switch target fsm @@ -252,116 +260,151 @@ if (r_spi_bsy == false) r_spi_done = false; - switch (r_spi_fsm) { - case S_IDLE: - r_spi_clk_counter = r_divider.read(); - r_spi_clk = 0; - r_spi_clk_previous = r_ctrl_cpha; - r_spi_clk_ignore = r_ctrl_cpha; - r_spi_bit_count = r_ctrl_char_len; - if (r_dma_count != 0) { - if (r_read.read()) - r_spi_fsm = S_DMA_SEND_START; - else - r_spi_fsm = S_DMA_RECEIVE; - } else if (r_spi_bsy.read() && !r_spi_done.read()) { + + switch (r_spi_fsm) + { + //////////// + case S_IDLE: // polling the (r_dma_count/r_read) registers for dma request + // polling the r_spi_bsy register for config request + { + r_spi_clk_counter = r_divider.read(); + r_spi_clk = 0; + r_spi_clk_previous = r_ctrl_cpha; + r_spi_clk_ignore = r_ctrl_cpha; + r_spi_bit_count = r_ctrl_char_len; + if (r_dma_count != 0) + { + if (r_read.read()) r_spi_fsm = S_DMA_SEND_START; + else r_spi_fsm = S_DMA_RECEIVE; + } + else if (r_spi_bsy.read() && !r_spi_done.read()) + { + r_spi_fsm = S_XMIT; + r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) + & (uint64_t)0x0000000000000001ULL; + } + break; + } + /////////////////// + case S_DMA_RECEIVE: // copy one word from fifo_write to shift register + { + r_spi_clk_counter = r_divider.read(); + r_spi_clk = 0; + r_spi_clk_previous = r_ctrl_cpha; + r_spi_clk_ignore = r_ctrl_cpha; + r_spi_bit_count = r_ctrl_char_len; + if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) + { + if (r_dma_fifo_write.rok()) + { + typename vci_param::data_t v = r_dma_fifo_write.read(); + r_dma_fifo_write.simple_get(); + r_txrx[0] = v; + r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1; + r_spi_fsm = S_XMIT; + } + else if (r_initiator_fsm == M_WRITE_END) + { + r_spi_fsm = S_IDLE; + } + } + break; + } + ////////////////////// + case S_DMA_SEND_START: + { + r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1; + r_spi_out = 1; + r_txrx[0] = 0xffffffff; r_spi_fsm = S_XMIT; - r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; - } - break; - case S_DMA_RECEIVE: - { - r_spi_clk_counter = r_divider.read(); - r_spi_clk = 0; - r_spi_clk_previous = r_ctrl_cpha; - r_spi_clk_ignore = r_ctrl_cpha; - r_spi_bit_count = r_ctrl_char_len; - if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) { - if (r_dma_fifo_write.rok()) { - typename vci_param::data_t v = r_dma_fifo_write.read(); - r_dma_fifo_write.simple_get(); - r_txrx[0] = v; - r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1; - r_spi_fsm = S_XMIT; - } else if (r_initiator_fsm == M_WRITE_END) { - r_spi_fsm = S_IDLE; - } - } - break; - } - case S_DMA_SEND_START: - r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1; - r_spi_out = 1; - r_txrx[0] = 0xffffffff; - r_spi_fsm = S_XMIT; - break; + break; + } + //////////////// case S_DMA_SEND: - r_spi_out = 1; - r_spi_clk_counter = r_divider.read(); - r_spi_clk = 0; - r_spi_clk_previous = r_ctrl_cpha; - r_spi_clk_ignore = r_ctrl_cpha; - r_spi_bit_count = r_ctrl_char_len; - if (r_initiator_fsm != M_READ_CMD) { - if (r_dma_fifo_read.wok()) { - r_dma_fifo_read.simple_put( - (typename vci_param::data_t)r_txrx[0]); - r_spi_word_count = r_spi_word_count - 1; - r_txrx[0] = 0xffffffff; - if ( r_spi_word_count == 0 ) { - r_spi_fsm = S_DMA_SEND_END; - } else { - r_spi_fsm = S_XMIT; - } - } - } - break; - case S_DMA_SEND_END: - if (r_initiator_fsm == M_IDLE) - r_spi_fsm = S_IDLE; - break; - case S_XMIT: - { - bool s_clk_sample; - // on clock transition, sample input line, and shift data - s_clk_sample = r_spi_clk ^ r_ctrl_cpha; - if (!r_spi_clk_ignore) { - if (r_spi_clk_previous == 0 && s_clk_sample == 1) { - // low to high transition: shift and sample - r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); - r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; - r_spi_bit_count = r_spi_bit_count - 1; - } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) { - // high to low transition: change output, or stop - if (r_spi_bit_count == 0) { - if (r_initiator_fsm != M_IDLE) { - if (r_read) - r_spi_fsm = S_DMA_SEND; - else - r_spi_fsm = S_DMA_RECEIVE; - } else { - r_spi_fsm = S_IDLE; - r_irq = r_ctrl_ie; - r_spi_done = true; - } + { + r_spi_out = 1; + r_spi_clk_counter = r_divider.read(); + r_spi_clk = 0; + r_spi_clk_previous = r_ctrl_cpha; + r_spi_clk_ignore = r_ctrl_cpha; + r_spi_bit_count = r_ctrl_char_len; + if (r_initiator_fsm != M_READ_CMD) + { + if (r_dma_fifo_read.wok()) + { + r_dma_fifo_read.simple_put( (typename vci_param::data_t)r_txrx[0] ); + r_spi_word_count = r_spi_word_count - 1; + r_txrx[0] = 0xffffffff; + if ( r_spi_word_count == 0 ) r_spi_fsm = S_DMA_SEND_END; + else r_spi_fsm = S_XMIT; + } + } + break; + } + //////////////////// + case S_DMA_SEND_END: + { + if (r_initiator_fsm == M_IDLE) r_spi_fsm = S_IDLE; + break; + } + //////////// + case S_XMIT: // on SPI clock transitions, sample input line, and shift data + { + bool s_clk_sample; + // on clock transition, sample input line, and shift data + s_clk_sample = r_spi_clk ^ r_ctrl_cpha; + + if ( !r_spi_clk_ignore ) + { + if (r_spi_clk_previous == 0 && s_clk_sample == 1) + { + // low to high transition: shift and sample + r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); + r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; + r_spi_bit_count = r_spi_bit_count - 1; + } + else if (r_spi_clk_previous == 1 && s_clk_sample == 0) + { + // high to low transition: change output, or stop + if (r_spi_bit_count == 0) + { + if (r_initiator_fsm != M_IDLE) + { + if (r_read) r_spi_fsm = S_DMA_SEND; + else r_spi_fsm = S_DMA_RECEIVE; + } + else + { + r_spi_fsm = S_IDLE; + r_irq = r_ctrl_ie; + r_spi_done = true; + } #ifdef SOCLIB_MODULE_DEBUG0 std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; #endif - } else { - r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; - } - } - } - r_spi_clk_previous = s_clk_sample; - // generate the SPI clock - if (r_spi_clk_counter.read() == 0) { - r_spi_clk_counter = r_divider.read(); - r_spi_clk = !r_spi_clk.read(); - r_spi_clk_ignore = false; - } else { - r_spi_clk_counter = r_spi_clk_counter.read() - 1; - } - break; - } - } + } + else + { + r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) + & (uint64_t)0x0000000000000001ULL; + } + } + } + r_spi_clk_previous = s_clk_sample; + + // generate the SPI clock + if (r_spi_clk_counter.read() == 0) + { + r_spi_clk_counter = r_divider.read(); + r_spi_clk = !r_spi_clk.read(); + r_spi_clk_ignore = false; + } + else + { + r_spi_clk_counter = r_spi_clk_counter.read() - 1; + } + break; + } + } // end r_spi_fsm + ////////////////////////////////////////////////////////////////////////////// // The initiator FSM executes a loop, transfering one burst per iteration. @@ -370,141 +413,155 @@ ////////////////////////////////////////////////////////////////////////////// - switch( r_initiator_fsm.read() ) { + switch( r_initiator_fsm.read() ) + { //////////// - case M_IDLE: // check buffer alignment to compute the number of bursts - { - if ( r_dma_count != 0 ) - { - // start transfer - if ( r_read.read() ) r_initiator_fsm = M_READ_WAIT; - else r_initiator_fsm = M_WRITE_WAIT; - } - break; - } + case M_IDLE: // poll the r_dma_count and r_read registers + { + if ( r_dma_count != 0 ) + { + // start transfer + if ( r_read.read() ) r_initiator_fsm = M_READ_WAIT; + else r_initiator_fsm = M_WRITE_WAIT; + } + break; + } + ///////////////// case M_READ_WAIT: // wait for the FIFO to be full - if (!r_dma_fifo_read.wok()) { - r_burst_word = m_words_per_burst - 1; - r_initiator_fsm = M_READ_CMD; - } - break; + { + if (!r_dma_fifo_read.wok()) + { + r_burst_word = m_words_per_burst - 1; + r_initiator_fsm = M_READ_CMD; + } + break; + } //////////////// - case M_READ_CMD: // Send a multi-flits VCI WRITE command - { - if ( p_vci_initiator.cmdack.read() ) - { - if ( r_burst_word == 0 ) // last flit + case M_READ_CMD: // multi-flits VCI WRITE command for one burst + { + if ( p_vci_initiator.cmdack.read() ) { - r_initiator_fsm = M_READ_RSP; - } - else // not the last flit - { - r_burst_word = r_burst_word.read() - 1; - } - - r_dma_fifo_read.simple_get(); // consume one fifo word - // compute next word address - r_buf_address = r_buf_address.read() + vci_param::B; - } - break; + if ( r_burst_word == 0 ) // last flit + { + r_initiator_fsm = M_READ_RSP; + } + else // not the last flit + { + r_burst_word = r_burst_word.read() - 1; + } + + r_dma_fifo_read.simple_get(); // consume one fifo word + // compute next word address + r_buf_address = r_buf_address.read() + vci_param::B; + } + break; } //////////////// case M_READ_RSP: // Wait a single flit VCI WRITE response { - if ( p_vci_initiator.rspval.read() ) - { - if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) + if ( p_vci_initiator.rspval.read() ) { - r_burst_word = 0; - r_dma_count = 0; - r_dma_error = true; - r_initiator_fsm = M_INTR; + if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_burst_word = 0; + r_dma_count = 0; + r_dma_error = true; + r_initiator_fsm = M_INTR; + #ifdef SOCLIB_MODULE_DEBUG std::cout << "vci_bd M_READ_ERROR" << std::endl; #endif - } - else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst - { - r_dma_count = 0; - r_initiator_fsm = M_INTR; - r_dma_error = false; + + } + else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst + { + r_dma_count = 0; + r_initiator_fsm = M_INTR; + r_dma_error = false; + #ifdef SOCLIB_MODULE_DEBUG std::cout << "vci_bd M_READ_SUCCESS" << std::endl; #endif - } - else // keep on reading - { - r_dma_count = r_dma_count - 1; - r_initiator_fsm = M_READ_WAIT; - } - } - break; + + } + else // keep on reading + { + r_dma_count = r_dma_count - 1; + r_initiator_fsm = M_READ_WAIT; + } + } + break; } /////////////////// case M_INTR: - r_initiator_fsm = M_IDLE; - r_irq = true; - break; + { + r_initiator_fsm = M_IDLE; + r_irq = true; + break; + } /////////////////// case M_WRITE_WAIT: // wait for the FIFO to be empty - if (!r_dma_fifo_write.rok()) { - r_burst_word = m_words_per_burst - 1; - r_dma_count = r_dma_count - 1; - r_initiator_fsm = M_WRITE_CMD; - } - break; + { + if (!r_dma_fifo_write.rok()) + { + r_burst_word = m_words_per_burst - 1; + r_dma_count = r_dma_count - 1; + r_initiator_fsm = M_WRITE_CMD; + } + break; + } ///////////////// - case M_WRITE_CMD: // This is actually a single flit VCI READ command - { - if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; - break; + case M_WRITE_CMD: // single flit VCI READ command for one burst + { + if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; + break; } ///////////////// - case M_WRITE_RSP: // This is actually a multi-words VCI READ response - { - if ( p_vci_initiator.rspval.read() ) - { - typename vci_param::data_t v = p_vci_initiator.rdata.read(); - typename vci_param::data_t f = 0; - // byte-swap - for (int i = 0; i < (vci_param::B * 8); i += 8) { - f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); - } - r_dma_fifo_write.simple_put(f); - r_burst_word = r_burst_word.read() - 1; - if ( p_vci_initiator.reop.read() ) // last flit of the burst + case M_WRITE_RSP: // wait multi-words VCI READ response + { + if ( p_vci_initiator.rspval.read() ) { - r_buf_address = r_buf_address.read() + m_burst_size; - - if( (p_vci_initiator.rerror.read()&0x1) != 0 ) - { - r_dma_count = 0; - r_dma_error = 1; - r_initiator_fsm = M_WRITE_END; + typename vci_param::data_t v = p_vci_initiator.rdata.read(); + typename vci_param::data_t f = 0; + // byte-swap + for (int i = 0; i < (vci_param::B * 8); i += 8) + { + f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); + } + r_dma_fifo_write.simple_put(f); + r_burst_word = r_burst_word.read() - 1; + if ( p_vci_initiator.reop.read() ) // last flit of the burst + { + r_buf_address = r_buf_address.read() + m_burst_size; + + if( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_dma_count = 0; + r_dma_error = 1; + r_initiator_fsm = M_WRITE_END; + #ifdef SOCLIB_MODULE_DEBUG - std::cout << "vci_bd M_WRITE_ERROR" << std::endl; + std::cout << "vci_spi M_WRITE_ERROR" << std::endl; #endif - } - else if ( r_dma_count.read() == 0) // last burst - { - r_dma_error = 0; - r_initiator_fsm = M_WRITE_END; - } - else // not the last burst - { - r_initiator_fsm = M_WRITE_WAIT; - } - } - } - break; + } + else if ( r_dma_count.read() == 0) // last burst + { + r_dma_error = 0; + r_initiator_fsm = M_WRITE_END; + } + else // not the last burst + { + r_initiator_fsm = M_WRITE_WAIT; + } + } + } + break; } ///////////////// - case M_WRITE_END: // wait for the write to be complete - { - if (r_spi_fsm == S_IDLE) { // write complete - r_initiator_fsm = M_INTR; - } - break; - } - } // end switch r_initiator_fsm + case M_WRITE_END: // wait for the write to be completed by SPI FSM + { + if (r_spi_fsm == S_IDLE) r_initiator_fsm = M_INTR; + break; + } + } // end switch r_initiator_fsm } // end transition @@ -609,26 +666,31 @@ } - // SPI signals + ////////////// SPI signals p_spi_ss = ((r_ss & 0x1) == 0); - switch(r_spi_fsm) { + + switch(r_spi_fsm) + { default: - p_spi_mosi = r_spi_out; - p_spi_clk = 0; - break; + p_spi_mosi = r_spi_out; + p_spi_clk = 0; + break; case S_XMIT: - { - bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha; - p_spi_clk = r_spi_clk ^ r_ctrl_cpol; - if (s_clk_sample == 0) { - // clock low: get data directly from shift register - // as r_spi_out may be delayed by one clock cycle - p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; - } else { - // clock high: get data from saved value, as the shift register - // may have changed - p_spi_mosi = r_spi_out; - } - break; - } + { + bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha; + p_spi_clk = r_spi_clk ^ r_ctrl_cpol; + if (s_clk_sample == 0) + { + // clock low: get data directly from shift register + // as r_spi_out may be delayed by one clock cycle + p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; + } + else + { + // clock high: get data from saved value, as the shift register + // may have changed + p_spi_mosi = r_spi_out; + } + break; + } } @@ -638,9 +700,9 @@ ////////////////////////////////////////////////////////////////////////////// -tmpl(/**/)::VciSpi( sc_core::sc_module_name name, +tmpl(/**/)::VciSpi( sc_core::sc_module_name name, const soclib::common::MappingTable &mt, - const soclib::common::IntTab &srcid, - const soclib::common::IntTab &tgtid, - const uint32_t burst_size) + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const uint32_t burst_size) : caba::BaseModule(name),