Index: trunk/modules/vci_spi/caba/source/src/vci_spi.cpp
===================================================================
--- trunk/modules/vci_spi/caba/source/src/vci_spi.cpp	(revision 595)
+++ trunk/modules/vci_spi/caba/source/src/vci_spi.cpp	(revision 1052)
@@ -46,34 +46,34 @@
 
     bool s_dma_bsy = (r_initiator_fsm != M_IDLE);
+
     if(p_resetn.read() == false) 
     {
-	r_initiator_fsm   = M_IDLE;
-	r_target_fsm      = T_IDLE;
-	r_spi_fsm	  = S_IDLE;
-	r_ss	          = 0;
-	r_divider	  = 0xffff;
-	r_ctrl_char_len   = 0;
-	r_ctrl_ie	  = false;
-	r_ctrl_cpol       = false;
-	r_ctrl_cpha       = false;
-	r_spi_bsy         = false;
-	r_dma_count       = 0;
-	r_dma_error       = false;
-	r_spi_clk_counter = 0xffff;
-	r_spi_clk	  = 0;
-	r_spi_done        = false;
-
-	r_irq		  = false;
-	r_read		  = false;
-
-	r_dma_fifo_read.init();
-	r_dma_fifo_write.init();
-
-	return;
+	    r_initiator_fsm   = M_IDLE;
+	    r_target_fsm      = T_IDLE;
+	    r_spi_fsm         = S_IDLE;
+	    r_ss	          = 0;
+	    r_divider         = 0xffff;
+	    r_ctrl_char_len   = 0;
+	    r_ctrl_ie         = false;
+	    r_ctrl_cpol       = false;
+	    r_ctrl_cpha       = false;
+	    r_spi_bsy         = false;
+	    r_dma_count       = 0;
+	    r_dma_error       = false;
+	    r_spi_clk_counter = 0xffff;
+	    r_spi_clk         = 0;
+	    r_spi_done        = false;
+
+	    r_irq		      = false;
+	    r_read		      = false;
+
+	    r_dma_fifo_read.init();
+	    r_dma_fifo_write.init();
+
+	    return;
     } 
 
     //////////////////////////////////////////////////////////////////////////////
-    // The Target FSM controls the following registers:
-    // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read
+    // The Target FSM handles the software access to addressable registers
     //////////////////////////////////////////////////////////////////////////////
 
@@ -81,96 +81,101 @@
 	r_spi_bsy = false;
 
-    switch(r_target_fsm) {
+    switch(r_target_fsm)
+    {
     ////////////
     case T_IDLE:
     {
-	if ( p_vci_target.cmdval.read() ) 
-	{ 
-	    r_srcid = p_vci_target.srcid.read();
-	    r_trdid = p_vci_target.trdid.read();
-	    r_pktid = p_vci_target.pktid.read();
-	    uint32_t wdata = p_vci_target.wdata.read();
-	    sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read();
-
-	    bool found = false;
-	    std::list<soclib::common::Segment>::iterator seg;
-	    for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 
-	    {
-		if ( seg->contains(address) ) found = true;
-	    }
+        if ( p_vci_target.cmdval.read() ) 
+        { 
+	        r_srcid = p_vci_target.srcid.read();
+	        r_trdid = p_vci_target.trdid.read();
+	        r_pktid = p_vci_target.pktid.read();
+	        uint32_t wdata = p_vci_target.wdata.read();
+	        sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read();
+
+	        bool found = false;
+	        std::list<soclib::common::Segment>::iterator seg;
+	        for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 
+	        {
+		        if ( seg->contains(address) ) found = true;
+	        }
  
-
-	    if (not found) {
-		if (p_vci_target.cmd.read() == vci_param::CMD_WRITE)
-	    	    r_target_fsm = T_ERROR_WRITE;
-		else
+	        if (not found) 
+            {
+		        if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) 
+                    r_target_fsm = T_ERROR_WRITE;
+		        else
+	    	        r_target_fsm = T_ERROR_READ;
+	        } 
+            else if (p_vci_target.cmd.read() != vci_param::CMD_READ &&
+		             p_vci_target.cmd.read() != vci_param::CMD_WRITE) 
+            {
 	    	    r_target_fsm = T_ERROR_READ;
-	    } else if (p_vci_target.cmd.read() != vci_param::CMD_READ &&
-		       p_vci_target.cmd.read() != vci_param::CMD_WRITE) {
-	    	r_target_fsm = T_ERROR_READ;
-	    } else {
-		bool     write  = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) & !r_spi_bsy &!s_dma_bsy;
-		uint32_t cell   = (uint32_t)((address & 0x3F)>>2);
-		switch(cell) {
-		case SPI_DATA_TXRX0:
-		    r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL;
-		    if (write) {
-			r_txrx[0] =
-			   (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) |
-			   ((uint64_t)wdata);
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_DATA_TXRX1:
-		    r_rdata = r_txrx[0] >> 32;
-		    if (write) {
-			r_txrx[0] =
-			    (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) |
-			    ((uint64_t)wdata << 32);
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_DATA_TXRX2:
-		    r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL;
-		    if (write) {
-			r_txrx[1] =
-			   (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) |
-			   ((uint64_t)wdata);
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_DATA_TXRX3:
-		    r_rdata = r_txrx[1] >> 32;
-		    if (write) {
-		        r_txrx[1] =
-			    (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) |
-			    ((uint64_t)wdata << 32);
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_CTRL:
-		{
-		    uint32_t data = 0;
-		    if (r_ctrl_cpol.read()) 
-			data |= SPI_CTRL_CPOL;
-		    if (r_ctrl_cpha.read()) 
-			data |= SPI_CTRL_CPHA;
-		    if (r_ctrl_ie.read()) 
-			data |= SPI_CTRL_IE_EN;
-		    if (r_spi_bsy.read()) 
-			data |= SPI_CTRL_GO_BSY;
-		    if (s_dma_bsy) 
-			data |= SPI_CTRL_DMA_BSY;
-		    if (r_dma_error) 
-			data |= SPI_CTRL_DMA_ERR;
-		    data |= (uint32_t)r_ctrl_char_len.read();
-		    r_rdata = data;
-		    if (write) {
-			r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0);
-			r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0);
-			r_ctrl_ie  = ((wdata & SPI_CTRL_IE_EN) != 0);
-			if (wdata & SPI_CTRL_GO_BSY) 
-				r_spi_bsy = true;
-			r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK);
+	        } 
+            else 
+            {
+		        bool     write  = (p_vci_target.cmd.read() == vci_param::CMD_WRITE)
+                                   & !r_spi_bsy & !s_dma_bsy;
+                uint32_t cell   = (uint32_t)((address & 0x3F)>>2);
+		        switch(cell) 
+                {
+		            case SPI_DATA_TXRX0:
+		            r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL;
+		            if (write) 
+                    {
+			            r_txrx[0] = (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) |
+			                        ((uint64_t)wdata);
+		            }
+		            r_target_fsm = (p_vci_target.cmd.read() 
+                                     == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_DATA_TXRX1:
+		            r_rdata = r_txrx[0] >> 32;
+		            if (write) 
+                    {
+			            r_txrx[0] = (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) |
+			                        ((uint64_t)wdata << 32);
+		            }
+		            r_target_fsm = (p_vci_target.cmd.read()
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_DATA_TXRX2:
+		            r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL;
+		            if (write) 
+                    {
+			            r_txrx[1] = (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) |
+			                        ((uint64_t)wdata);
+		            }
+		            r_target_fsm = (p_vci_target.cmd.read()
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_DATA_TXRX3:
+		            r_rdata = r_txrx[1] >> 32;
+		            if (write) 
+                    {
+		                r_txrx[1] = (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) |
+			                        ((uint64_t)wdata << 32);
+		            }
+		            r_target_fsm = (p_vci_target.cmd.read()
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_CTRL:
+		            uint32_t data = 0;
+		            if (r_ctrl_cpol.read()) data |= SPI_CTRL_CPOL;
+		            if (r_ctrl_cpha.read()) data |= SPI_CTRL_CPHA;
+		            if (r_ctrl_ie.read())   data |= SPI_CTRL_IE_EN;
+		            if (r_spi_bsy.read())   data |= SPI_CTRL_GO_BSY;
+		            if (s_dma_bsy)          data |= SPI_CTRL_DMA_BSY;
+		            if (r_dma_error)        data |= SPI_CTRL_DMA_ERR;
+		            data |= (uint32_t)r_ctrl_char_len.read();
+		            r_rdata = data;
+		            if (write) 
+                    {
+                        r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0);
+                        r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0);
+                        r_ctrl_ie  = ((wdata & SPI_CTRL_IE_EN) != 0);
+                        if (wdata & SPI_CTRL_GO_BSY) r_spi_bsy = true;
+			            r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK);
+
 #ifdef SOCLIB_MODULE_DEBUG
 			if ((wdata & SPI_CTRL_GO_BSY) != 0) {
@@ -178,58 +183,61 @@
 			}
 #endif
-		    } else {
-			r_irq = false;
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		}
-		case SPI_DIVIDER:
-		    r_rdata = r_divider.read();
-		    if (write) {
+                    } 
+                    else 
+                    {
+			            r_irq = false;
+		            }
+		            r_target_fsm = (p_vci_target.cmd.read() 
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_DIVIDER:
+		            r_rdata = r_divider.read();
+		            if (write) r_divider = wdata;
+
 #ifdef SOCLIB_MODULE_DEBUG
 		        std::cout << name() << " divider set to " << std::dec << wdata << std::endl;
 #endif
-			r_divider = wdata;
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_SS:
-		    r_rdata = r_ss.read();
-		    if (write) {
-			r_ss = wdata;
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_DMA_BASE:
-		    r_rdata = r_buf_address.read();
-		    if (write) {
-			r_buf_address = (r_buf_address & (uint64_t)0xffffffff00000000) | wdata;
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_DMA_BASEH:
-		    r_rdata = r_buf_address >> 32;
-		    if (write) {
-			r_buf_address = (r_buf_address & (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32);
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		case SPI_DMA_COUNT:
-		    r_rdata = (r_dma_count.read() << m_byte2burst_shift) |
-			r_read;
-		    if (write) {
-			r_read = (wdata & 0x1);
-			r_dma_count = wdata >> m_byte2burst_shift;
-			r_ctrl_char_len = vci_param::B * 8;
-		    }
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
-		    break;
-		default:
-		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ;
-		    break;
-		}
-	    }
-	}
-	break;
+		            r_target_fsm = (p_vci_target.cmd.read() 
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_SS:
+		            r_rdata = r_ss.read();
+		            if (write) r_ss = wdata;
+		            r_target_fsm = (p_vci_target.cmd.read()
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_DMA_BASE:
+		            r_rdata = r_buf_address.read();
+		            if (write) r_buf_address = (r_buf_address.read & 
+                                    (uint64_t)0xffffffff00000000) | wdata;
+		            r_target_fsm = (p_vci_target.cmd.read() 
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+                    case SPI_DMA_BASEH:
+		            r_rdata = r_buf_address >> 32;
+		            if (write) r_buf_address = (r_buf_address & 
+                                    (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32);
+		            r_target_fsm = (p_vci_target.cmd.read()
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            case SPI_DMA_COUNT:
+		            r_rdata = (r_dma_count.read() << m_byte2burst_shift) | r_read;
+		            if (write) 
+                    {
+			            r_read = (wdata & 0x1);
+                        r_dma_count = wdata >> m_byte2burst_shift;
+			            r_ctrl_char_len = vci_param::B * 8;
+		            }
+		            r_target_fsm = (p_vci_target.cmd.read()
+                                    == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
+		            break;
+		            default:
+		            r_target_fsm = (p_vci_target.cmd.read() 
+                                   == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ;
+		            break;
+		        }
+	        }
+	    }
+	    break;
     }
     ////////////////////
@@ -238,8 +246,8 @@
     case T_ERROR_READ:
     case T_ERROR_WRITE:
-	if (p_vci_target.rspack.read() ) {
-	    r_target_fsm  = T_IDLE;
-	}
-	break;
+    {
+	    if (p_vci_target.rspack.read() ) r_target_fsm  = T_IDLE;
+	    break;
+    }
     } // end switch target fsm
 
@@ -252,116 +260,151 @@
     if (r_spi_bsy == false)
 	r_spi_done = false;
-    switch (r_spi_fsm) {
-    case S_IDLE:
-	r_spi_clk_counter = r_divider.read();
-	r_spi_clk = 0;
-	r_spi_clk_previous = r_ctrl_cpha;
-	r_spi_clk_ignore = r_ctrl_cpha;
-	r_spi_bit_count = r_ctrl_char_len;
-	if (r_dma_count != 0) {
-		if (r_read.read())
-			r_spi_fsm = S_DMA_SEND_START;
-		else
-			r_spi_fsm = S_DMA_RECEIVE;
-	} else if (r_spi_bsy.read() && !r_spi_done.read()) {
+ 
+    switch (r_spi_fsm) 
+    {
+    ////////////
+    case S_IDLE:   // polling the (r_dma_count/r_read) registers for dma request
+                   // polling the r_spi_bsy register for config request
+    {
+        r_spi_clk_counter = r_divider.read();
+        r_spi_clk = 0;
+        r_spi_clk_previous = r_ctrl_cpha;
+        r_spi_clk_ignore = r_ctrl_cpha;
+	    r_spi_bit_count = r_ctrl_char_len;
+        if (r_dma_count != 0) 
+        {
+		    if (r_read.read()) r_spi_fsm = S_DMA_SEND_START;
+		    else               r_spi_fsm = S_DMA_RECEIVE;
+	    } 
+        else if (r_spi_bsy.read() && !r_spi_done.read()) 
+        {
+	        r_spi_fsm = S_XMIT;
+	        r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64))
+                          & (uint64_t)0x0000000000000001ULL;
+	    }
+	    break;
+    }
+    ///////////////////
+    case S_DMA_RECEIVE:  // copy one word from fifo_write to shift register
+    {
+	    r_spi_clk_counter = r_divider.read();
+	    r_spi_clk = 0;
+	    r_spi_clk_previous = r_ctrl_cpha;
+	    r_spi_clk_ignore = r_ctrl_cpha;
+	    r_spi_bit_count = r_ctrl_char_len;
+	    if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) 
+        {
+	        if (r_dma_fifo_write.rok()) 
+            {
+	            typename vci_param::data_t v = r_dma_fifo_write.read();
+	            r_dma_fifo_write.simple_get();
+	            r_txrx[0] = v;
+	            r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1;
+	            r_spi_fsm = S_XMIT;
+	        }
+            else if (r_initiator_fsm == M_WRITE_END) 
+            {
+	            r_spi_fsm = S_IDLE;
+	        }
+	    }
+	    break;
+    }
+    //////////////////////
+    case S_DMA_SEND_START:
+    {
+	    r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1;
+	    r_spi_out = 1;
+	    r_txrx[0] = 0xffffffff;
 	    r_spi_fsm = S_XMIT;
-	    r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL;
-	}
-	break;
-    case S_DMA_RECEIVE:
-    {
-	r_spi_clk_counter = r_divider.read();
-	r_spi_clk = 0;
-	r_spi_clk_previous = r_ctrl_cpha;
-	r_spi_clk_ignore = r_ctrl_cpha;
-	r_spi_bit_count = r_ctrl_char_len;
-	if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) {
-	    if (r_dma_fifo_write.rok()) {
-	        typename vci_param::data_t v = r_dma_fifo_write.read();
-	        r_dma_fifo_write.simple_get();
-	        r_txrx[0] = v;
-	        r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1;
-	        r_spi_fsm = S_XMIT;
-	    } else if (r_initiator_fsm == M_WRITE_END) {
-	        r_spi_fsm = S_IDLE;
-	    }
-	}
-	break;
-    }
-    case S_DMA_SEND_START:
-	r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1;
-	r_spi_out = 1;
-	r_txrx[0] = 0xffffffff;
-	r_spi_fsm = S_XMIT;
-	break;
+	    break;
+    }
+    ////////////////
     case S_DMA_SEND:
-	r_spi_out = 1;
-	r_spi_clk_counter = r_divider.read();
-	r_spi_clk = 0;
-	r_spi_clk_previous = r_ctrl_cpha;
-	r_spi_clk_ignore = r_ctrl_cpha;
-	r_spi_bit_count = r_ctrl_char_len;
-	if (r_initiator_fsm != M_READ_CMD) {
-	    if (r_dma_fifo_read.wok()) {
-	        r_dma_fifo_read.simple_put(
-		    (typename vci_param::data_t)r_txrx[0]);
-	        r_spi_word_count = r_spi_word_count - 1;
-		r_txrx[0] = 0xffffffff;
-	        if ( r_spi_word_count == 0 ) {
-		    r_spi_fsm = S_DMA_SEND_END;
-	        } else {
-		    r_spi_fsm = S_XMIT;
-	        }
-	    }
-	}
-	break;
-    case S_DMA_SEND_END:
-	if (r_initiator_fsm == M_IDLE)
-		r_spi_fsm = S_IDLE;
-	break;
-    case S_XMIT:
-      {
-	bool s_clk_sample;
-	// on clock transition, sample input line, and shift data
-	s_clk_sample = r_spi_clk ^ r_ctrl_cpha;
-	if (!r_spi_clk_ignore) {
-	    if (r_spi_clk_previous == 0 && s_clk_sample == 1) {
-		// low to high transition: shift and sample
-		r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63);
-		r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso;
-		r_spi_bit_count = r_spi_bit_count - 1;
-	    } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) {
-		// high to low transition: change output, or stop
-		if (r_spi_bit_count == 0) {
-		    if (r_initiator_fsm != M_IDLE) {
-			if (r_read)
-			    r_spi_fsm = S_DMA_SEND;
-			else
-			    r_spi_fsm = S_DMA_RECEIVE;
-		    } else {
-		        r_spi_fsm = S_IDLE;
-		        r_irq = r_ctrl_ie;
-		        r_spi_done = true;
-		    }
+	{
+        r_spi_out = 1;
+	    r_spi_clk_counter = r_divider.read();
+	    r_spi_clk = 0;
+	    r_spi_clk_previous = r_ctrl_cpha;
+	    r_spi_clk_ignore = r_ctrl_cpha;
+	    r_spi_bit_count = r_ctrl_char_len;
+	    if (r_initiator_fsm != M_READ_CMD) 
+        {
+	        if (r_dma_fifo_read.wok()) 
+            {
+	            r_dma_fifo_read.simple_put( (typename vci_param::data_t)r_txrx[0] );
+	            r_spi_word_count = r_spi_word_count - 1;
+		        r_txrx[0] = 0xffffffff;
+	            if ( r_spi_word_count == 0 ) r_spi_fsm = S_DMA_SEND_END;
+                else                         r_spi_fsm = S_XMIT;
+	        }
+	    }
+	    break;
+    }
+    ////////////////////
+    case S_DMA_SEND_END: 
+    {
+	    if (r_initiator_fsm == M_IDLE) r_spi_fsm = S_IDLE;
+	    break;
+    }
+    ////////////
+    case S_XMIT:   // on SPI clock transitions, sample input line, and shift data
+    {
+        bool s_clk_sample;
+	    // on clock transition, sample input line, and shift data
+	    s_clk_sample = r_spi_clk ^ r_ctrl_cpha;
+
+	    if ( !r_spi_clk_ignore ) 
+        {
+	        if (r_spi_clk_previous == 0 && s_clk_sample == 1) 
+            {
+		        // low to high transition: shift and sample
+		        r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63);
+		        r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso;
+		        r_spi_bit_count = r_spi_bit_count - 1;
+	        } 
+            else if (r_spi_clk_previous == 1 && s_clk_sample == 0) 
+            {
+		        // high to low transition: change output, or stop
+		        if (r_spi_bit_count == 0) 
+                {
+		            if (r_initiator_fsm != M_IDLE) 
+                    {
+			            if (r_read) r_spi_fsm = S_DMA_SEND;
+			            else        r_spi_fsm = S_DMA_RECEIVE;
+		            }
+                    else 
+                    {
+		                r_spi_fsm = S_IDLE;
+		                r_irq = r_ctrl_ie;
+		                r_spi_done = true;
+		            }
 #ifdef SOCLIB_MODULE_DEBUG0
 		    std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl;
 #endif
-		} else {
-		    r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL;
-		}
-	    }
-	}
-	r_spi_clk_previous = s_clk_sample;
-	// generate the SPI clock
-	if (r_spi_clk_counter.read() == 0) {
-	    r_spi_clk_counter = r_divider.read();
-	    r_spi_clk = !r_spi_clk.read();
-	    r_spi_clk_ignore = false;
-	} else {
-	    r_spi_clk_counter = r_spi_clk_counter.read() - 1;
-	}
-	break;
-      }
-    }
+		        } 
+                else 
+                {
+		            r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64))
+                                 & (uint64_t)0x0000000000000001ULL;
+		        }
+	        }
+	    }
+	    r_spi_clk_previous = s_clk_sample;
+
+	    // generate the SPI clock
+        if (r_spi_clk_counter.read() == 0) 
+        {
+	        r_spi_clk_counter = r_divider.read();
+	        r_spi_clk = !r_spi_clk.read();
+	        r_spi_clk_ignore = false;
+	    } 
+        else 
+        {
+	        r_spi_clk_counter = r_spi_clk_counter.read() - 1;
+        }
+	    break;
+    }
+    }  // end r_spi_fsm
+
     //////////////////////////////////////////////////////////////////////////////
     // The initiator FSM executes a loop, transfering one burst per iteration.
@@ -370,141 +413,155 @@
     //////////////////////////////////////////////////////////////////////////////
 
-    switch( r_initiator_fsm.read() ) {
+    switch( r_initiator_fsm.read() ) 
+    {
     ////////////
-    case M_IDLE: 	// check buffer alignment to compute the number of bursts
-    {
-	if ( r_dma_count != 0 )
-	{
-	    // start transfer
-	    if ( r_read.read() )    r_initiator_fsm = M_READ_WAIT;
-	    else		    r_initiator_fsm = M_WRITE_WAIT;
-	}
-	break;
-    }
+    case M_IDLE: 	// poll the r_dma_count and r_read registers 
+    {
+	    if ( r_dma_count != 0 )
+	    {
+	        // start transfer
+	        if ( r_read.read() )    r_initiator_fsm = M_READ_WAIT;
+	        else		            r_initiator_fsm = M_WRITE_WAIT;
+	    }
+	    break;
+    }
+    /////////////////
     case M_READ_WAIT:  // wait for the FIFO to be full
-	if (!r_dma_fifo_read.wok()) {
-		r_burst_word = m_words_per_burst - 1;
-		r_initiator_fsm = M_READ_CMD;
-	}
-	break;
+    {
+	    if (!r_dma_fifo_read.wok()) 
+        {
+		    r_burst_word = m_words_per_burst - 1;
+		    r_initiator_fsm = M_READ_CMD;
+	    }
+	    break;
+    }
     ////////////////
-    case M_READ_CMD:	// Send a multi-flits VCI WRITE command
-    {
-	if ( p_vci_initiator.cmdack.read() )
-	{
-	    if ( r_burst_word == 0 )      // last flit
+    case M_READ_CMD:	// multi-flits VCI WRITE command for one burst
+    {
+	    if ( p_vci_initiator.cmdack.read() )
 	    {
-		r_initiator_fsm = M_READ_RSP;
-	    }
-	    else		    // not the last flit
-	    {
-		r_burst_word = r_burst_word.read() - 1;
-	    }
-
-	    r_dma_fifo_read.simple_get(); // consume one fifo word
-	    // compute next word address
-	    r_buf_address = r_buf_address.read() + vci_param::B;
-	}
-	break;
+	        if ( r_burst_word == 0 )      // last flit
+	        {
+		        r_initiator_fsm = M_READ_RSP;
+	        }
+	        else		    // not the last flit
+	        {
+		        r_burst_word = r_burst_word.read() - 1;
+	        }
+
+	        r_dma_fifo_read.simple_get(); // consume one fifo word
+	        // compute next word address
+	        r_buf_address = r_buf_address.read() + vci_param::B;
+	    }
+	    break;
     }
     ////////////////
     case M_READ_RSP: 	// Wait a single flit VCI WRITE response
     {
-	if ( p_vci_initiator.rspval.read() )
-	{
-	    if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
+	    if ( p_vci_initiator.rspval.read() )
 	    {
-	        r_burst_word = 0;
-		r_dma_count = 0;
-		r_dma_error = true;
-	        r_initiator_fsm = M_INTR;
+	        if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
+	        {
+	            r_burst_word = 0;
+                r_dma_count = 0;
+                r_dma_error = true;
+	            r_initiator_fsm = M_INTR;
+
 #ifdef SOCLIB_MODULE_DEBUG
 		std::cout << "vci_bd M_READ_ERROR" << std::endl;
 #endif
-	    }
-	    else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst
-	    {
-		r_dma_count = 0;
-		r_initiator_fsm = M_INTR;
-		r_dma_error = false;
+
+	        }
+	        else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst
+	        {
+                r_dma_count = 0;
+                r_initiator_fsm = M_INTR;
+	            r_dma_error = false;
+
 #ifdef SOCLIB_MODULE_DEBUG
 		std::cout << "vci_bd M_READ_SUCCESS" << std::endl;
 #endif
-	    }
-	    else // keep on reading
-	    {
-		r_dma_count = r_dma_count - 1;
-		r_initiator_fsm  = M_READ_WAIT;
-	    }
-	}
-	break;
+
+	        }
+	        else // keep on reading
+	        {
+                r_dma_count = r_dma_count - 1;
+		        r_initiator_fsm  = M_READ_WAIT;
+	        }
+	    }
+	    break;
     }
     ///////////////////
     case M_INTR: 
-	r_initiator_fsm = M_IDLE;
-	r_irq = true;
-	break;
+    {
+	    r_initiator_fsm = M_IDLE;
+	    r_irq = true;
+	    break;
+    }
     ///////////////////
     case M_WRITE_WAIT:  // wait for the FIFO to be empty
-	if (!r_dma_fifo_write.rok()) {
-	    r_burst_word = m_words_per_burst - 1;
-	    r_dma_count = r_dma_count - 1;
-	    r_initiator_fsm = M_WRITE_CMD;
-	}
-	break;
+	{
+        if (!r_dma_fifo_write.rok()) 
+        {
+	        r_burst_word = m_words_per_burst - 1;
+	        r_dma_count = r_dma_count - 1;
+	        r_initiator_fsm = M_WRITE_CMD;
+	    }
+	    break;
+    }
     /////////////////
-    case M_WRITE_CMD:	// This is actually a single flit VCI READ command
-    {
-	if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP;
-	break;
+    case M_WRITE_CMD:	// single flit VCI READ command for one burst
+    {
+	    if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP;
+	    break;
     }
     /////////////////
-    case M_WRITE_RSP:	// This is actually a multi-words VCI READ response
-    {
-	if ( p_vci_initiator.rspval.read() )
-	{
-	    typename vci_param::data_t v = p_vci_initiator.rdata.read();
-	    typename vci_param::data_t f = 0;
-	    // byte-swap
-	    for (int i = 0; i < (vci_param::B * 8); i += 8) {
-		f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i);
-	    }
-	    r_dma_fifo_write.simple_put(f);
-	    r_burst_word = r_burst_word.read() - 1;
-	    if ( p_vci_initiator.reop.read() )  // last flit of the burst
+    case M_WRITE_RSP:	// wait multi-words VCI READ response
+    {
+	    if ( p_vci_initiator.rspval.read() )
 	    {
-		r_buf_address = r_buf_address.read() + m_burst_size;
-
-		if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
-		{
-		    r_dma_count = 0;
-		    r_dma_error = 1;
-		    r_initiator_fsm = M_WRITE_END;
+	        typename vci_param::data_t v = p_vci_initiator.rdata.read();
+	        typename vci_param::data_t f = 0;
+	        // byte-swap
+	        for (int i = 0; i < (vci_param::B * 8); i += 8) 
+            {
+		        f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i);
+	        }
+	        r_dma_fifo_write.simple_put(f);
+	        r_burst_word = r_burst_word.read() - 1;
+	        if ( p_vci_initiator.reop.read() )  // last flit of the burst
+	        {
+		        r_buf_address = r_buf_address.read() + m_burst_size;
+
+		        if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
+		        {
+		            r_dma_count = 0;
+		            r_dma_error = 1;
+		            r_initiator_fsm = M_WRITE_END;
+
 #ifdef SOCLIB_MODULE_DEBUG
-		    std::cout << "vci_bd M_WRITE_ERROR" << std::endl;
+		    std::cout << "vci_spi M_WRITE_ERROR" << std::endl;
 #endif
-		}
-		else if ( r_dma_count.read() == 0) // last burst
-		{
-		    r_dma_error = 0;
-		    r_initiator_fsm  = M_WRITE_END;
-		}
-		else					  // not the last burst
-		{
-		    r_initiator_fsm = M_WRITE_WAIT;
-		}
-	    }
-	}
-	break;
+                }
+		        else if ( r_dma_count.read() == 0) // last burst
+                {
+		            r_dma_error = 0;
+		            r_initiator_fsm  = M_WRITE_END;
+		        }
+                else					  // not the last burst
+                {
+		            r_initiator_fsm = M_WRITE_WAIT;
+		        }
+	        }
+	    }
+	    break;
     }
     /////////////////
-    case M_WRITE_END:	// wait for the write to be complete
-    {
-	if (r_spi_fsm == S_IDLE) { // write complete
-	    r_initiator_fsm  = M_INTR;
-	}
-	break;
-    }
-  } // end switch r_initiator_fsm
+    case M_WRITE_END:	// wait for the write to be completed by SPI FSM
+    {
+	    if (r_spi_fsm == S_IDLE)  r_initiator_fsm  = M_INTR;
+	    break;
+    }
+    } // end switch r_initiator_fsm
 }  // end transition
 
@@ -609,26 +666,31 @@
     }
 
-    // SPI signals
+    ////////////// SPI signals
     p_spi_ss = ((r_ss & 0x1) == 0);
-    switch(r_spi_fsm) {
+
+    switch(r_spi_fsm) 
+    {
     default:
-	p_spi_mosi = r_spi_out;
-	p_spi_clk = 0;
-	break;
+	    p_spi_mosi = r_spi_out;
+	    p_spi_clk = 0;
+	    break;
     case S_XMIT:
-      {
-	bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha;
-	p_spi_clk = r_spi_clk ^ r_ctrl_cpol;
-	if (s_clk_sample == 0) {
-	    // clock low: get data directly from shift register
-	    // as r_spi_out may be delayed by one clock cycle
-	    p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL;
-	} else {
-	    // clock high: get data from saved value, as the shift register
-	    // may have changed
-	    p_spi_mosi = r_spi_out;
-	}
-	break;
-      }
+    {
+	    bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha;
+	    p_spi_clk = r_spi_clk ^ r_ctrl_cpol;
+	    if (s_clk_sample == 0) 
+        {
+	        // clock low: get data directly from shift register
+	        // as r_spi_out may be delayed by one clock cycle
+	        p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL;
+	    } 
+        else 
+        {
+	        // clock high: get data from saved value, as the shift register
+	        // may have changed
+	        p_spi_mosi = r_spi_out;
+	    }
+	    break;
+    }
     }
 
@@ -638,9 +700,9 @@
 
 //////////////////////////////////////////////////////////////////////////////
-tmpl(/**/)::VciSpi( sc_core::sc_module_name	      name, 
+tmpl(/**/)::VciSpi( sc_core::sc_module_name	         name, 
 				const soclib::common::MappingTable   &mt,
-				const soclib::common::IntTab	 &srcid,
-				const soclib::common::IntTab	 &tgtid,
-				const uint32_t		       burst_size)
+				const soclib::common::IntTab         &srcid,
+				const soclib::common::IntTab         &tgtid,
+				const uint32_t		                 burst_size)
 
 : caba::BaseModule(name),
