Changeset 1055 for trunk/platforms
- Timestamp:
- Dec 20, 2017, 4:55:09 PM (7 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/arch_info.py
r1053 r1055 222 222 size = rom_size ) 223 223 224 # we describe the largest config : (nb_nics = 4) & (nb_ttys = 8) 224 225 archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, channel = 0 , is_rx = True ) 225 226 archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, channel = 1 , is_rx = True ) -
trunk/platforms/tsar_generic_iob/top.cpp
r1053 r1055 1658 1658 // clusters[0][0]->proc[0]->cache_monitor( 0x00032D74ULL ); 1659 1659 1660 // Monitor a specific address for oneL2 cache (single word if second argument true)1661 // clusters[0][0]->memc->cache_monitor( 0x 00032D74ULL, false);1660 // Monitor a specific address for L2 cache (single word if second argument true) 1661 // clusters[0][0]->memc->cache_monitor( 0xdc000ULL ); 1662 1662 1663 1663 // Monitor a specific address for one XRAM … … 1668 1668 std::cout << "****************** cycle " << std::dec << n ; 1669 1669 std::cout << " ************************************************" << std::endl; 1670 1671 1670 // trace proc[debug_proc_id] 1672 1671 if ( debug_proc_id != 0xFFFFFFFF ) 1673 1672 { 1673 // processor debug modes 1674 // 0x01 : write buffer trace 1675 // 0x02 : dump processor registers 1676 // 0x04 : dcache trace 1677 // 0x08 : icache trace 1678 // 0x10 : dtlb trace 1679 // 0x20 : itlb trace 1680 // 0x40 : SR 1674 1681 size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; 1675 1682 size_t cluster_xy = debug_proc_id >> P_WIDTH ; … … 1684 1691 { 1685 1692 */ 1686 clusters[x][y]->proc[l]->print_trace(0x 1);1693 clusters[x][y]->proc[l]->print_trace(0x42); 1687 1694 std::ostringstream proc_signame; 1688 1695 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
Note: See TracChangeset
for help on using the changeset viewer.