Changeset 1058

Timestamp:

Jun 19, 2018, 5:01:20 PM (7 years ago)

Author:

alain

Message:

bloup

File:

• trunk/platforms/tsar_generic_leti/arch_info.py (modified) (3 diffs)

trunk/platforms/tsar_generic_leti/arch_info.py

@@ -17 +17 @@
 #  The constructor prototype format is imposed by the genarch.py application,
 #  and should not be modified. 
-#  The default argument values are for the TSARLET prototype.
-#
-#  The "tsar_generic_leti" architecture  includes 6 external peripherals located 
-#  in cluster[x_size-1][y_size-1]: TTY, IOC, FBF, NIC, CMA, PIC.
-#  It does not use the IOB component.
+#  The default argument values are for the TSARLET 16 cores prototype.
+#
+#  The "tsar_generic_leti" architecture  includes 5 external peripherals located 
+#  in cluster[x_size-1][y_size-1]: TTY, IOC, FBF, NIC, PIC.
+#  The upper row (y = y_size-1) does not contain processors or memory.
+#  The "tsar_generic_leti" does not use the IOB component.
 #  It does not use an external ROM, as the preloader code is (pre)loaded
 #  at address 0x0, in the physical memory of cluster[0][0].
 #
-#  The upper row (y = y_size-1) does not contain processors or memory.
+#  Two backup peripherals one (one TXT_TTY and one IOC_BDV) are connected
+#  on local interconnect in cluster 0.
 #
 #  The "constructor" parameters (defined in Makefile) are:
@@ -170 +172 @@
                               srcdev = mmc )
 
-                ### TTY backup
+                ### TTY and IOC backup
                 if ( x==0 ) and ( y==0 ):
                     tty_bak = archi.addDevice( ptype    = 'TXT_TTY',
@@ -178 +180 @@
 
                     archi.addIrq( dstdev  = xcu, 
-                                  port    = 10, 
+                                  port    = TODO 
                                   srcdev  = tty_bak,
                                   channel = 0,
                                   is_rx   = False )
+
+                    ioc_bak = archi.addDevice( ptype    = 'IOC_BDV',
+                                               base     = ioc_base + offset,
+                                               size     = ioc_size )
+
+                    archi.addIrq( dstdev  = xcu, 
+                                  port    = TODO 
+                                  srcdev  = ioc_bak )
 
                 for p in xrange ( nb_cores ):