Ignore:
Timestamp:
Oct 10, 2019, 11:35:53 AM (5 years ago)
Author:
alain
Message:

Fix a bug in the LLSC reservation FSM: the r_llsc_count (lifetime counter)
was not properly updated, resulting in an unexpected reservation invalidation.
This caused an abnormal failure in the NON BLOCKING hal_remote_atomic_cas()
function in ALMOS-MKH.

Location:
trunk/modules/vci_cc_vcache_wrapper/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r1047 r1061  
    4747#include "iss2.h"
    4848
    49 #define LLSC_TIMEOUT    10000
     49#define LLSC_TIMEOUT   1000000
    5050
    5151namespace soclib {
    … …  
    343343    bool                                m_debug_cmd_fsm;
    344344    uint32_t                            m_previous_status;
     345    uint32_t                            m_debug_previous_mmu;
    345346
    346347
    … …  
    587588    //////////////////////////////////////////////////////////////////
    588589
    589     sc_signal<paddr_t>                     r_dcache_llsc_paddr;
    590     sc_signal<uint32_t>                    r_dcache_llsc_key;
    591     sc_signal<uint32_t>                    r_dcache_llsc_count;
    592     sc_signal<bool>                        r_dcache_llsc_valid;
     590    sc_signal<paddr_t>                     r_llsc_paddr;
     591    sc_signal<uint32_t>                    r_llsc_key;
     592    sc_signal<uint32_t>                    r_llsc_count;
    593593
    594594    ////////////////////////////////
    … …  
    754754    void print_frozen_stats();
    755755    void print_trace(size_t mode = 0);
     756    void mmu_monitor();
    756757    void cache_monitor(paddr_t addr);
    757758    void start_monitor(paddr_t,paddr_t);

  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r1047 r1061  
    497497              << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
    498498              << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
    499               << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
    500               << " | MMU = " << r_mmu_mode.read();
    501 
     499              << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] << std::endl;
     500
     501    std::cout << std::hex
     502              << "  MMU_MODE = " << r_mmu_mode.read()
     503              << " | MMU_PTPR = " << r_mmu_ptpr.read()
     504              << " | LLSC_COUNT = " << r_llsc_count.read()
     505              << " | LLSC_PADDR = " << r_llsc_paddr.read()
     506              << " | LLSC_KEY = " << r_llsc_key.read();
    502507    if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT";
    503508    if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF";
    … …  
    547552}
    548553
     554///////////////////////////
     555tmpl(void)::mmu_monitor()
     556///////////////////////////
     557{
     558    if( r_mmu_mode.read() != m_debug_previous_mmu )
     559    {
     560        std::cout << "   !!!  MMU_MODE change in " << name() << " : "
     561                  << std::hex << m_debug_previous_mmu << " -> " << r_mmu_mode.read()
     562                  << " at cycle " << std::dec << m_cpt_total_cycles << std::endl;
     563
     564        m_debug_previous_mmu = r_mmu_mode.read();
     565    }
     566}
     567 
    549568//////////////////////////////////////////
    550569tmpl(void)::cache_monitor(paddr_t addr)
    … …  
    565584    if (cache_hit != m_debug_previous_d_hit)
    566585    {
    567         std::cout << "Monitor PROC " << name()
     586        std::cout << "Monitor L1/D " << name()
    568587                  << " DCACHE at cycle " << std::dec << m_cpt_total_cycles
    569588                  << " / HIT = " << cache_hit
    … …  
    582601    if (cache_hit != m_debug_previous_i_hit)
    583602    {
    584         std::cout << "Monitor PROC " << name()
     603        std::cout << "Monitor L1/I " << name()
    585604                  << " ICACHE at cycle " << std::dec << m_cpt_total_cycles
    586605                  << " / HIT = " << cache_hit
    … …  
    849868
    850869        // Debug variables
     870        m_debug_previous_mmu       = 0;
    851871        m_debug_previous_i_hit     = false;
    852872        m_debug_previous_d_hit     = false;
    … …  
    962982        for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
    963983
    964         // init the llsc reservation buffer
    965         r_dcache_llsc_valid = false;
     984        // initialize llsc reservation buffer
     985        r_llsc_count = 0;
     986
     987        // initialize monitor
    966988        m_monitor_ok = false;
    967989
    … …  
    969991    }
    970992
    971     // Response FIFOs default values
     993    // vci_rsp_icache FIFO default values
    972994    bool     vci_rsp_fifo_icache_get  = false;
    973995    bool     vci_rsp_fifo_icache_put  = false;
    974996    uint32_t vci_rsp_fifo_icache_data = 0;
    975997
     998    // vci_rsp_dcache FIFO default values
    976999    bool     vci_rsp_fifo_dcache_get  = false;
    9771000    bool     vci_rsp_fifo_dcache_put  = false;
    9781001    uint32_t vci_rsp_fifo_dcache_data = 0;
    9791002
    980     // updt fifo
     1003    // cc_receive_updt FIFO default values
    9811004    bool     cc_receive_updt_fifo_get  = false;
    9821005    bool     cc_receive_updt_fifo_put  = false;
    … …  
    9841007    uint32_t cc_receive_updt_fifo_data = 0;
    9851008    bool     cc_receive_updt_fifo_eop  = false;
     1009
     1010    // llsc requests default values
     1011    bool     llsc_set   = false;
     1012    uint32_t llsc_key   = 0;
     1013    bool     llsc_reset = false;
    9861014
    9871015#ifdef INSTRUMENTATION
    … …  
    21842212    //
    21852213    // 4/ Atomic instructions LL/SC
    2186     //    The LL/SC address are non cacheable (systematic access to memory).
     2214    //    The LL/SC target address are non cacheable (systematic access to memory).
    21872215    //    The llsc buffer contains a registration for an active LL/SC operation
    2188     //    (with an address, a registration key, an aging counter and a valid bit).
     2216    //    (with an address, a registration key, and an aging counter). There is a
     2217    //    valid reservation when the aging counter is non zero.
    21892218    //    - LL requests from the processor are transmitted as a one flit VCI command
    21902219    //      (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
    … …  
    26432672
    26442673                    case iss_t::XTN_MMU_LL_RESET:   // no cache or tlb access
    2645                         r_dcache_llsc_valid = false;
     2674                        r_llsc_count        = 0;
    26462675                        m_drsp.valid        = true;
    26472676                        r_dcache_fsm        = DCACHE_IDLE;
    … …  
    28392868
    28402869                    // LL request (non cachable)
    2841                     // We request a VCI LL transaction to CMD FSM and register
    2842                     // the LL/SC operation in llsc buffer.
     2870                    // We request a VCI LL transaction to CMD FSM.
     2871                    // We register the  address in the llsc reservation buffer,
     2872                    // and cancel any previously registered reservation.
    28432873                    else if (m_dreq.type == iss_t::DATA_LL)
    28442874                    {
    2845                         // register paddr in LLSC buffer
    2846                         r_dcache_llsc_paddr = paddr;
    2847                         r_dcache_llsc_count = LLSC_TIMEOUT;
    2848                         r_dcache_llsc_valid = true;
    2849 
    2850                         // request an LL VCI transaction and go to DCACHE_LL_WAIT state
     2875                        // reset previous LLSC registration / register paddr
     2876                        r_llsc_paddr = paddr;
     2877                        llsc_reset   = true;
     2878
     2879                        // request an LL VCI transaction
    28512880                        r_dcache_vci_ll_req   = true;
    28522881                        r_dcache_vci_paddr    = paddr;
     2882
     2883                        // go to DCACHE_LL_WAIT state
    28532884                        r_dcache_ll_rsp_count = 0;
    28542885                        r_dcache_fsm          = DCACHE_LL_WAIT;
    28552886
    2856                     }// end LL
     2887                    } // end LL
    28572888
    28582889                    // WRITE request:
    … …  
    28882919                            m_cpt_data_write++;
    28892920#endif
    2890                             // cleaning llsc buffer if address matching
    2891                             if (paddr == r_dcache_llsc_paddr.read())
    2892                                 r_dcache_llsc_valid = false;
     2921                            // clean llsc buffer if address matching
     2922                            if (paddr == r_llsc_paddr.read()) llsc_reset = true;
    28932923
    28942924                            if (not cacheable) // uncacheable write
    … …  
    29713001                            m_cpt_data_sc++;
    29723002#endif
    2973                             // checking local success
    2974                             if (r_dcache_llsc_valid.read() and
    2975                                 (r_dcache_llsc_paddr.read() == paddr)) // local success
     3003
     3004                            if ( (r_llsc_count.read() != 0) and (r_llsc_paddr.read() == paddr) ) // local success
    29763005                            {
    29773006                                // request an SC CMD and go to DCACHE_SC_WAIT state
    … …  
    29813010                                r_dcache_fsm         = DCACHE_SC_WAIT;
    29823011                            }
    2983                             else // local fail
     3012                            else                                                         // local fail
    29843013                            {
    29853014                                m_drsp.valid = true;
    … …  
    30563085            else
    30573086                std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
    3058             std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
     3087                std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
    30593088                << " / ptpr  = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
    30603089                << " / BYPASS = " << bypass
    … …  
    36593688        r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
    36603689
    3661         // checking llsc reservation buffer
    3662         if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
    3663             r_dcache_llsc_valid = false;
     3690        // reset llsc reservation buffer when required
     3691        if (r_llsc_paddr.read() == r_dcache_tlb_paddr.read())  llsc_reset = true;
    36643692
    36653693        // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
    … …  
    45734601            if (r_dcache_ll_rsp_count.read() == 0) // first flit
    45744602            {
    4575                 // set key value in llsc reservation buffer
    4576                 r_dcache_llsc_key     = r_vci_rsp_fifo_dcache.read();
     4603                // set llsc reservation buffer
     4604                llsc_set = true;
     4605                llsc_key = r_vci_rsp_fifo_dcache.read();
     4606
     4607                // increment flit count
    45774608                r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
    45784609            }
    … …  
    46624693        r_dcache_dirty_set = set;
    46634694
    4664         // check llsc reservation buffer
    4665         if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
    4666             r_dcache_llsc_valid = false;
     4695        // reset llsc reservation buffer if required
     4696        if (r_llsc_paddr.read() == r_dcache_dirty_paddr.read())  llsc_reset = true;
    46674697
    46684698        // request a CAS CMD and go to DCACHE_DIRTY_WAIT state
    … …  
    51005130    r_wbuf.update();
    51015131
    5102     ///////////////// llsc update //////////////////////////////////////////////////////////
    5103     if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
    5104     if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
     5132    ////////////////////////////////////////////////////////////////////////////////////////
     5133    // The LLSC reservation buffer contains 3 registers:
     5134    // - the r_llsc_count register is a cycle counter. There exist a valid reservation
     5135    //   when this counter is not nul. It is decremented at each cycle when not zero,
     5136    //   and when there is no set or reset request to implement a bounded lifetime for
     5137    //   a given reservation.
     5138    // - the r_llsc_paddr register define the reserved address. It is set by the DCACHE
     5139    //   FSM handling an LL request in IDLE state. A previously registered reservation
     5140    //   is canceled.
     5141    // - the r_llsc_key register contains the key returned by the L2 cache after
     5142    //   a VCI LL transaction. Both the r_llsc_key and the r_llsc_count registers are
     5143    //   set by the DCACHE FSM receiving the L2 cache response in the LL_WAIT state.
     5144    // - A valid reservation is canceled by the reset command from the DCACHE FSM,
     5145    //   when a local write to the reserved address is detected.
     5146    ///////////////////////////////////////////////////////////////////////////////////////
     5147     
     5148    if( llsc_set )
     5149    {
     5150        r_llsc_count = LLSC_TIMEOUT;
     5151        r_llsc_key   = llsc_key;
     5152    }
     5153    else if( llsc_reset )
     5154    {
     5155        r_llsc_count = 0;
     5156    }
     5157    else if( r_llsc_count.read() != 0 )
     5158    {
     5159        r_llsc_count = r_llsc_count.read() - 1;
     5160    }
    51055161
    51065162    //////////////// test processor frozen /////////////////////////////////////////////////
    … …  
    61396195        p_vci.cmdval  = true;
    61406196        p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
    6141         if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
     6197        if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_llsc_key.read();
    61426198        else                           p_vci.wdata = r_dcache_vci_sc_data.read();
    61436199        p_vci.be      = 0xF;
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