Changeset 1061 for trunk/modules/vci_cc_vcache_wrapper/caba/source/src
- Timestamp:
- Oct 10, 2019, 11:35:53 AM (5 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r1047 r1061 497 497 << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] 498 498 << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()] 499 << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] 500 << " | MMU = " << r_mmu_mode.read(); 501 499 << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] << std::endl; 500 501 std::cout << std::hex 502 << " MMU_MODE = " << r_mmu_mode.read() 503 << " | MMU_PTPR = " << r_mmu_ptpr.read() 504 << " | LLSC_COUNT = " << r_llsc_count.read() 505 << " | LLSC_PADDR = " << r_llsc_paddr.read() 506 << " | LLSC_KEY = " << r_llsc_key.read(); 502 507 if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT"; 503 508 if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF"; … … 547 552 } 548 553 554 /////////////////////////// 555 tmpl(void)::mmu_monitor() 556 /////////////////////////// 557 { 558 if( r_mmu_mode.read() != m_debug_previous_mmu ) 559 { 560 std::cout << " !!! MMU_MODE change in " << name() << " : " 561 << std::hex << m_debug_previous_mmu << " -> " << r_mmu_mode.read() 562 << " at cycle " << std::dec << m_cpt_total_cycles << std::endl; 563 564 m_debug_previous_mmu = r_mmu_mode.read(); 565 } 566 } 567 549 568 ////////////////////////////////////////// 550 569 tmpl(void)::cache_monitor(paddr_t addr) … … 565 584 if (cache_hit != m_debug_previous_d_hit) 566 585 { 567 std::cout << "Monitor PROC" << name()586 std::cout << "Monitor L1/D " << name() 568 587 << " DCACHE at cycle " << std::dec << m_cpt_total_cycles 569 588 << " / HIT = " << cache_hit … … 582 601 if (cache_hit != m_debug_previous_i_hit) 583 602 { 584 std::cout << "Monitor PROC" << name()603 std::cout << "Monitor L1/I " << name() 585 604 << " ICACHE at cycle " << std::dec << m_cpt_total_cycles 586 605 << " / HIT = " << cache_hit … … 849 868 850 869 // Debug variables 870 m_debug_previous_mmu = 0; 851 871 m_debug_previous_i_hit = false; 852 872 m_debug_previous_d_hit = false; … … 962 982 for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0; 963 983 964 // init the llsc reservation buffer 965 r_dcache_llsc_valid = false; 984 // initialize llsc reservation buffer 985 r_llsc_count = 0; 986 987 // initialize monitor 966 988 m_monitor_ok = false; 967 989 … … 969 991 } 970 992 971 // Response FIFOsdefault values993 // vci_rsp_icache FIFO default values 972 994 bool vci_rsp_fifo_icache_get = false; 973 995 bool vci_rsp_fifo_icache_put = false; 974 996 uint32_t vci_rsp_fifo_icache_data = 0; 975 997 998 // vci_rsp_dcache FIFO default values 976 999 bool vci_rsp_fifo_dcache_get = false; 977 1000 bool vci_rsp_fifo_dcache_put = false; 978 1001 uint32_t vci_rsp_fifo_dcache_data = 0; 979 1002 980 // updt fifo1003 // cc_receive_updt FIFO default values 981 1004 bool cc_receive_updt_fifo_get = false; 982 1005 bool cc_receive_updt_fifo_put = false; … … 984 1007 uint32_t cc_receive_updt_fifo_data = 0; 985 1008 bool cc_receive_updt_fifo_eop = false; 1009 1010 // llsc requests default values 1011 bool llsc_set = false; 1012 uint32_t llsc_key = 0; 1013 bool llsc_reset = false; 986 1014 987 1015 #ifdef INSTRUMENTATION … … 2184 2212 // 2185 2213 // 4/ Atomic instructions LL/SC 2186 // The LL/SC address are non cacheable (systematic access to memory).2214 // The LL/SC target address are non cacheable (systematic access to memory). 2187 2215 // The llsc buffer contains a registration for an active LL/SC operation 2188 // (with an address, a registration key, an aging counter and a valid bit). 2216 // (with an address, a registration key, and an aging counter). There is a 2217 // valid reservation when the aging counter is non zero. 2189 2218 // - LL requests from the processor are transmitted as a one flit VCI command 2190 2219 // (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must … … 2643 2672 2644 2673 case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access 2645 r_ dcache_llsc_valid = false;2674 r_llsc_count = 0; 2646 2675 m_drsp.valid = true; 2647 2676 r_dcache_fsm = DCACHE_IDLE; … … 2839 2868 2840 2869 // LL request (non cachable) 2841 // We request a VCI LL transaction to CMD FSM and register 2842 // the LL/SC operation in llsc buffer. 2870 // We request a VCI LL transaction to CMD FSM. 2871 // We register the address in the llsc reservation buffer, 2872 // and cancel any previously registered reservation. 2843 2873 else if (m_dreq.type == iss_t::DATA_LL) 2844 2874 { 2845 // register paddr in LLSC buffer 2846 r_dcache_llsc_paddr = paddr; 2847 r_dcache_llsc_count = LLSC_TIMEOUT; 2848 r_dcache_llsc_valid = true; 2849 2850 // request an LL VCI transaction and go to DCACHE_LL_WAIT state 2875 // reset previous LLSC registration / register paddr 2876 r_llsc_paddr = paddr; 2877 llsc_reset = true; 2878 2879 // request an LL VCI transaction 2851 2880 r_dcache_vci_ll_req = true; 2852 2881 r_dcache_vci_paddr = paddr; 2882 2883 // go to DCACHE_LL_WAIT state 2853 2884 r_dcache_ll_rsp_count = 0; 2854 2885 r_dcache_fsm = DCACHE_LL_WAIT; 2855 2886 2856 } // end LL2887 } // end LL 2857 2888 2858 2889 // WRITE request: … … 2888 2919 m_cpt_data_write++; 2889 2920 #endif 2890 // cleaning llsc buffer if address matching 2891 if (paddr == r_dcache_llsc_paddr.read()) 2892 r_dcache_llsc_valid = false; 2921 // clean llsc buffer if address matching 2922 if (paddr == r_llsc_paddr.read()) llsc_reset = true; 2893 2923 2894 2924 if (not cacheable) // uncacheable write … … 2971 3001 m_cpt_data_sc++; 2972 3002 #endif 2973 // checking local success 2974 if (r_dcache_llsc_valid.read() and 2975 (r_dcache_llsc_paddr.read() == paddr)) // local success 3003 3004 if ( (r_llsc_count.read() != 0) and (r_llsc_paddr.read() == paddr) ) // local success 2976 3005 { 2977 3006 // request an SC CMD and go to DCACHE_SC_WAIT state … … 2981 3010 r_dcache_fsm = DCACHE_SC_WAIT; 2982 3011 } 2983 else // local fail3012 else // local fail 2984 3013 { 2985 3014 m_drsp.valid = true; … … 3056 3085 else 3057 3086 std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss"; 3058 std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()3087 std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() 3059 3088 << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) 3060 3089 << " / BYPASS = " << bypass … … 3659 3688 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); 3660 3689 3661 // checking llsc reservation buffer 3662 if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read()) 3663 r_dcache_llsc_valid = false; 3690 // reset llsc reservation buffer when required 3691 if (r_llsc_paddr.read() == r_dcache_tlb_paddr.read()) llsc_reset = true; 3664 3692 3665 3693 // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state … … 4573 4601 if (r_dcache_ll_rsp_count.read() == 0) // first flit 4574 4602 { 4575 // set key value in llsc reservation buffer 4576 r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); 4603 // set llsc reservation buffer 4604 llsc_set = true; 4605 llsc_key = r_vci_rsp_fifo_dcache.read(); 4606 4607 // increment flit count 4577 4608 r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1; 4578 4609 } … … 4662 4693 r_dcache_dirty_set = set; 4663 4694 4664 // check llsc reservation buffer 4665 if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read()) 4666 r_dcache_llsc_valid = false; 4695 // reset llsc reservation buffer if required 4696 if (r_llsc_paddr.read() == r_dcache_dirty_paddr.read()) llsc_reset = true; 4667 4697 4668 4698 // request a CAS CMD and go to DCACHE_DIRTY_WAIT state … … 5100 5130 r_wbuf.update(); 5101 5131 5102 ///////////////// llsc update ////////////////////////////////////////////////////////// 5103 if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1; 5104 if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false; 5132 //////////////////////////////////////////////////////////////////////////////////////// 5133 // The LLSC reservation buffer contains 3 registers: 5134 // - the r_llsc_count register is a cycle counter. There exist a valid reservation 5135 // when this counter is not nul. It is decremented at each cycle when not zero, 5136 // and when there is no set or reset request to implement a bounded lifetime for 5137 // a given reservation. 5138 // - the r_llsc_paddr register define the reserved address. It is set by the DCACHE 5139 // FSM handling an LL request in IDLE state. A previously registered reservation 5140 // is canceled. 5141 // - the r_llsc_key register contains the key returned by the L2 cache after 5142 // a VCI LL transaction. Both the r_llsc_key and the r_llsc_count registers are 5143 // set by the DCACHE FSM receiving the L2 cache response in the LL_WAIT state. 5144 // - A valid reservation is canceled by the reset command from the DCACHE FSM, 5145 // when a local write to the reserved address is detected. 5146 /////////////////////////////////////////////////////////////////////////////////////// 5147 5148 if( llsc_set ) 5149 { 5150 r_llsc_count = LLSC_TIMEOUT; 5151 r_llsc_key = llsc_key; 5152 } 5153 else if( llsc_reset ) 5154 { 5155 r_llsc_count = 0; 5156 } 5157 else if( r_llsc_count.read() != 0 ) 5158 { 5159 r_llsc_count = r_llsc_count.read() - 1; 5160 } 5105 5161 5106 5162 //////////////// test processor frozen ///////////////////////////////////////////////// … … 6139 6195 p_vci.cmdval = true; 6140 6196 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 6141 if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_ dcache_llsc_key.read();6197 if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_llsc_key.read(); 6142 6198 else p_vci.wdata = r_dcache_vci_sc_data.read(); 6143 6199 p_vci.be = 0xF;
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