Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 1054) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 1061) @@ -47,5 +47,5 @@ #include "iss2.h" -#define LLSC_TIMEOUT 10000 +#define LLSC_TIMEOUT 1000000 namespace soclib { @@ -343,4 +343,5 @@ bool m_debug_cmd_fsm; uint32_t m_previous_status; + uint32_t m_debug_previous_mmu; @@ -587,8 +588,7 @@ ////////////////////////////////////////////////////////////////// - sc_signal r_dcache_llsc_paddr; - sc_signal r_dcache_llsc_key; - sc_signal r_dcache_llsc_count; - sc_signal r_dcache_llsc_valid; + sc_signal r_llsc_paddr; + sc_signal r_llsc_key; + sc_signal r_llsc_count; //////////////////////////////// @@ -754,4 +754,5 @@ void print_frozen_stats(); void print_trace(size_t mode = 0); + void mmu_monitor(); void cache_monitor(paddr_t addr); void start_monitor(paddr_t,paddr_t); Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 1054) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 1061) @@ -497,7 +497,12 @@ << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()] - << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] - << " | MMU = " << r_mmu_mode.read(); - + << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] << std::endl; + + std::cout << std::hex + << " MMU_MODE = " << r_mmu_mode.read() + << " | MMU_PTPR = " << r_mmu_ptpr.read() + << " | LLSC_COUNT = " << r_llsc_count.read() + << " | LLSC_PADDR = " << r_llsc_paddr.read() + << " | LLSC_KEY = " << r_llsc_key.read(); if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT"; if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF"; @@ -547,4 +552,18 @@ } +/////////////////////////// +tmpl(void)::mmu_monitor() +/////////////////////////// +{ + if( r_mmu_mode.read() != m_debug_previous_mmu ) + { + std::cout << " !!! MMU_MODE change in " << name() << " : " + << std::hex << m_debug_previous_mmu << " -> " << r_mmu_mode.read() + << " at cycle " << std::dec << m_cpt_total_cycles << std::endl; + + m_debug_previous_mmu = r_mmu_mode.read(); + } +} + ////////////////////////////////////////// tmpl(void)::cache_monitor(paddr_t addr) @@ -565,5 +584,5 @@ if (cache_hit != m_debug_previous_d_hit) { - std::cout << "Monitor PROC " << name() + std::cout << "Monitor L1/D " << name() << " DCACHE at cycle " << std::dec << m_cpt_total_cycles << " / HIT = " << cache_hit @@ -582,5 +601,5 @@ if (cache_hit != m_debug_previous_i_hit) { - std::cout << "Monitor PROC " << name() + std::cout << "Monitor L1/I " << name() << " ICACHE at cycle " << std::dec << m_cpt_total_cycles << " / HIT = " << cache_hit @@ -849,4 +868,5 @@ // Debug variables + m_debug_previous_mmu = 0; m_debug_previous_i_hit = false; m_debug_previous_d_hit = false; @@ -962,6 +982,8 @@ for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0; - // init the llsc reservation buffer - r_dcache_llsc_valid = false; + // initialize llsc reservation buffer + r_llsc_count = 0; + + // initialize monitor m_monitor_ok = false; @@ -969,14 +991,15 @@ } - // Response FIFOs default values + // vci_rsp_icache FIFO default values bool vci_rsp_fifo_icache_get = false; bool vci_rsp_fifo_icache_put = false; uint32_t vci_rsp_fifo_icache_data = 0; + // vci_rsp_dcache FIFO default values bool vci_rsp_fifo_dcache_get = false; bool vci_rsp_fifo_dcache_put = false; uint32_t vci_rsp_fifo_dcache_data = 0; - // updt fifo + // cc_receive_updt FIFO default values bool cc_receive_updt_fifo_get = false; bool cc_receive_updt_fifo_put = false; @@ -984,4 +1007,9 @@ uint32_t cc_receive_updt_fifo_data = 0; bool cc_receive_updt_fifo_eop = false; + + // llsc requests default values + bool llsc_set = false; + uint32_t llsc_key = 0; + bool llsc_reset = false; #ifdef INSTRUMENTATION @@ -2184,7 +2212,8 @@ // // 4/ Atomic instructions LL/SC - // The LL/SC address are non cacheable (systematic access to memory). + // The LL/SC target address are non cacheable (systematic access to memory). // The llsc buffer contains a registration for an active LL/SC operation - // (with an address, a registration key, an aging counter and a valid bit). + // (with an address, a registration key, and an aging counter). There is a + // valid reservation when the aging counter is non zero. // - LL requests from the processor are transmitted as a one flit VCI command // (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must @@ -2643,5 +2672,5 @@ case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access - r_dcache_llsc_valid = false; + r_llsc_count = 0; m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; @@ -2839,20 +2868,22 @@ // LL request (non cachable) - // We request a VCI LL transaction to CMD FSM and register - // the LL/SC operation in llsc buffer. + // We request a VCI LL transaction to CMD FSM. + // We register the address in the llsc reservation buffer, + // and cancel any previously registered reservation. else if (m_dreq.type == iss_t::DATA_LL) { - // register paddr in LLSC buffer - r_dcache_llsc_paddr = paddr; - r_dcache_llsc_count = LLSC_TIMEOUT; - r_dcache_llsc_valid = true; - - // request an LL VCI transaction and go to DCACHE_LL_WAIT state + // reset previous LLSC registration / register paddr + r_llsc_paddr = paddr; + llsc_reset = true; + + // request an LL VCI transaction r_dcache_vci_ll_req = true; r_dcache_vci_paddr = paddr; + + // go to DCACHE_LL_WAIT state r_dcache_ll_rsp_count = 0; r_dcache_fsm = DCACHE_LL_WAIT; - }// end LL + } // end LL // WRITE request: @@ -2888,7 +2919,6 @@ m_cpt_data_write++; #endif - // cleaning llsc buffer if address matching - if (paddr == r_dcache_llsc_paddr.read()) - r_dcache_llsc_valid = false; + // clean llsc buffer if address matching + if (paddr == r_llsc_paddr.read()) llsc_reset = true; if (not cacheable) // uncacheable write @@ -2971,7 +3001,6 @@ m_cpt_data_sc++; #endif - // checking local success - if (r_dcache_llsc_valid.read() and - (r_dcache_llsc_paddr.read() == paddr)) // local success + + if ( (r_llsc_count.read() != 0) and (r_llsc_paddr.read() == paddr) ) // local success { // request an SC CMD and go to DCACHE_SC_WAIT state @@ -2981,5 +3010,5 @@ r_dcache_fsm = DCACHE_SC_WAIT; } - else // local fail + else // local fail { m_drsp.valid = true; @@ -3056,5 +3085,5 @@ else std::cout << " DTLB miss"; - std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() + std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) << " / BYPASS = " << bypass @@ -3659,7 +3688,6 @@ r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); - // checking llsc reservation buffer - if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read()) - r_dcache_llsc_valid = false; + // reset llsc reservation buffer when required + if (r_llsc_paddr.read() == r_dcache_tlb_paddr.read()) llsc_reset = true; // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state @@ -4573,6 +4601,9 @@ if (r_dcache_ll_rsp_count.read() == 0) // first flit { - // set key value in llsc reservation buffer - r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); + // set llsc reservation buffer + llsc_set = true; + llsc_key = r_vci_rsp_fifo_dcache.read(); + + // increment flit count r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1; } @@ -4662,7 +4693,6 @@ r_dcache_dirty_set = set; - // check llsc reservation buffer - if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read()) - r_dcache_llsc_valid = false; + // reset llsc reservation buffer if required + if (r_llsc_paddr.read() == r_dcache_dirty_paddr.read()) llsc_reset = true; // request a CAS CMD and go to DCACHE_DIRTY_WAIT state @@ -5100,7 +5130,33 @@ r_wbuf.update(); - ///////////////// llsc update ////////////////////////////////////////////////////////// - if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1; - if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false; + //////////////////////////////////////////////////////////////////////////////////////// + // The LLSC reservation buffer contains 3 registers: + // - the r_llsc_count register is a cycle counter. There exist a valid reservation + // when this counter is not nul. It is decremented at each cycle when not zero, + // and when there is no set or reset request to implement a bounded lifetime for + // a given reservation. + // - the r_llsc_paddr register define the reserved address. It is set by the DCACHE + // FSM handling an LL request in IDLE state. A previously registered reservation + // is canceled. + // - the r_llsc_key register contains the key returned by the L2 cache after + // a VCI LL transaction. Both the r_llsc_key and the r_llsc_count registers are + // set by the DCACHE FSM receiving the L2 cache response in the LL_WAIT state. + // - A valid reservation is canceled by the reset command from the DCACHE FSM, + // when a local write to the reserved address is detected. + /////////////////////////////////////////////////////////////////////////////////////// + + if( llsc_set ) + { + r_llsc_count = LLSC_TIMEOUT; + r_llsc_key = llsc_key; + } + else if( llsc_reset ) + { + r_llsc_count = 0; + } + else if( r_llsc_count.read() != 0 ) + { + r_llsc_count = r_llsc_count.read() - 1; + } //////////////// test processor frozen ///////////////////////////////////////////////// @@ -6139,5 +6195,5 @@ p_vci.cmdval = true; p_vci.address = r_dcache_vci_paddr.read() & ~0x3; - if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read(); + if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_llsc_key.read(); else p_vci.wdata = r_dcache_vci_sc_data.read(); p_vci.be = 0xF;