Index: /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
===================================================================
--- /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 108)
+++ /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 109)
@@ -780,8 +780,10 @@
             case ICACHE_ERROR:
                 {
+                    if ( (addr_40)ireq.addr == (addr_40)r_icache_addr_save ) {
+                        irsp.error          = true;
+                        irsp.valid          = true;
+                    }
                     r_icache_fsm = ICACHE_IDLE;
                     r_vci_rsp_ins_error = false;
-                    irsp.error          = true;
-                    irsp.valid          = true;
                     break;
                 }
@@ -1567,5 +1569,7 @@
 
                 if ( p_vci_ini_rw.reop.read() ) {
-                    assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                    assert( ((r_vci_rsp_cpt == m_icache_words - 1) ||
+                             p_vci_ini_rw.rerror.read() ||
+                             (r_vci_rsp_ins_error.read()&0x1))&&
                             "The VCI response packet for instruction miss is too short");
                     r_icache_miss_req = false;
@@ -1596,5 +1600,7 @@
                 r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
                 if ( p_vci_ini_rw.reop.read() ) {
-                    assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    assert( ((r_vci_rsp_cpt == m_dcache_words - 1) 
+                             || (p_vci_ini_rw.rerror.read()&0x1)
+                             || r_vci_rsp_data_error.read()) &&
                             "illegal VCI response packet for data read miss");
                     r_dcache_miss_req = false;