Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
===================================================================
--- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 113)
+++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 114)
@@ -285,7 +285,7 @@
         std::cout << "- WRITE LENGTH       = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl;
     }
-    /////////////////////////
-    tmpl(void)::print_trace()
-    /////////////////////////
+    ////////////////////////////////////
+    tmpl(void)::print_trace(size_t mode)
+    ////////////////////////////////////
     {
         typename iss_t::InstructionRequest  ireq;
@@ -294,4 +294,6 @@
 
         std::cout << std::dec << "CC_XCACHE_WRAPPER " << name() << std::endl;
+        std::cout << " proc state  : PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr 
+                  << std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl;
         std::cout << " cache state : " << icache_fsm_state_str[r_icache_fsm] << " / "
                                        << dcache_fsm_state_str[r_dcache_fsm] << " / "
@@ -299,6 +301,12 @@
                                        << rsp_fsm_state_str[r_vci_rsp_fsm] << " / "
                                        << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl;
-        std::cout << " proc state  : PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr 
-                  << std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl;
+        if( r_vci_tgt_fsm != TGT_IDLE ) 
+        {
+            std::cout << "    ... coherence request address = " << std::hex << r_tgt_addr.read() << std::endl;
+        }
+        if(mode & 0x1)
+        {
+            r_wbuf.printTrace();
+        }
     }
     //////////////////////////