- Timestamp:
- Nov 12, 2010, 12:21:16 PM (14 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source
- Files:
-
- 2 edited
-
include/vci_mem_cache_v4.h (modified) (3 diffs)
-
src/vci_mem_cache_v4.cpp (modified) (13 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r82 r116 58 58 #include "update_tab_v4.h" 59 59 60 #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab 61 #define UPDATE_TAB_LINES 4 // Number of lines in the update tab 62 #define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate 60 #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab 61 #define UPDATE_TAB_LINES 4 // Number of lines in the update tab 63 62 64 63 namespace soclib { namespace caba { … … 328 327 void print_stats(); 329 328 329 void print_trace(); 330 330 331 private: 331 332 332 333 // Component attributes 333 const size_t m_initiators; // Number of initiators334 const size_t m_heap_size; // Size of the heap335 const size_t m_ways; // Number of ways in a set336 const size_t m_sets; // Number of cache sets337 const size_t m_words;// Number of words in a line338 const size_t m_srcid_ixr;// Srcid for requests to XRAM339 const size_t m_srcid_ini;// Srcid for requests to processors340 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache341 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache334 const size_t m_initiators; // Number of initiators 335 const size_t m_heap_size; // Size of the heap 336 const size_t m_ways; // Number of ways in a set 337 const size_t m_sets; // Number of cache sets 338 const size_t m_words; // Number of words in a line 339 const size_t m_srcid_ixr; // Srcid for requests to XRAM 340 const size_t m_srcid_ini; // Srcid for requests to processors 341 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache 342 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache 342 343 vci_addr_t *m_coherence_table; // address(srcid) 343 TransactionTab m_transaction_tab; 344 UpdateTab m_update_tab;// pending update & invalidate345 CacheDirectory m_cache_directory; 346 HeapDirectory m_heap_directory; // heap directory344 TransactionTab m_transaction_tab; // xram transaction table 345 UpdateTab m_update_tab; // pending update & invalidate 346 CacheDirectory m_cache_directory; // data cache directory 347 HeapDirectory m_heap_directory; // heap directory 347 348 348 349 data_t ***m_cache_data; // data array[set][way][word] … … 355 356 356 357 // broadcast address 357 vci_addr_t broadcast_addr;358 vci_addr_t m_broadcast_address; 358 359 359 360 ////////////////////////////////////////////////// -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r83 r116 38 38 namespace soclib { namespace caba { 39 39 40 #ifdef DEBUG_VCI_MEM_CACHE41 40 const char *tgt_cmd_fsm_str[] = { 42 "TGT_CMD_IDLE ",43 "TGT_CMD_READ ",41 "TGT_CMD_IDLE ", 42 "TGT_CMD_READ ", 44 43 "TGT_CMD_READ_EOP", 45 "TGT_CMD_WRITE ",46 "TGT_CMD_ATOMIC ",44 "TGT_CMD_WRITE ", 45 "TGT_CMD_ATOMIC ", 47 46 }; 48 47 const char *tgt_rsp_fsm_str[] = { 49 "TGT_RSP_READ_IDLE ",50 "TGT_RSP_WRITE_IDLE ",51 "TGT_RSP_LLSC_IDLE ",52 "TGT_RSP_XRAM_IDLE ",53 "TGT_RSP_INIT_IDLE ",48 "TGT_RSP_READ_IDLE ", 49 "TGT_RSP_WRITE_IDLE ", 50 "TGT_RSP_LLSC_IDLE ", 51 "TGT_RSP_XRAM_IDLE ", 52 "TGT_RSP_INIT_IDLE ", 54 53 "TGT_RSP_CLEANUP_IDLE", 55 "TGT_RSP_READ ",56 "TGT_RSP_WRITE ",57 "TGT_RSP_LLSC ",58 "TGT_RSP_XRAM ",59 "TGT_RSP_INIT ",60 "TGT_RSP_CLEANUP ",54 "TGT_RSP_READ ", 55 "TGT_RSP_WRITE ", 56 "TGT_RSP_LLSC ", 57 "TGT_RSP_XRAM ", 58 "TGT_RSP_INIT ", 59 "TGT_RSP_CLEANUP ", 61 60 }; 62 61 const char *init_cmd_fsm_str[] = { 63 "INIT_CMD_INVAL_IDLE ",64 "INIT_CMD_INVAL_NLINE ",65 "INIT_CMD_XRAM_BRDCAST ",66 "INIT_CMD_UPDT_IDLE ",67 "INIT_CMD_WRITE_BRDCAST ",68 "INIT_CMD_UPDT_NLINE ",69 "INIT_CMD_UPDT_INDEX ",70 "INIT_CMD_UPDT_DATA ",71 "INIT_CMD_SC_UPDT_IDLE ",72 "INIT_CMD_SC_BRDCAST ",73 "INIT_CMD_SC_UPDT_NLINE ",74 "INIT_CMD_SC_UPDT_INDEX ",75 "INIT_CMD_SC_UPDT_DATA ",62 "INIT_CMD_INVAL_IDLE ", 63 "INIT_CMD_INVAL_NLINE ", 64 "INIT_CMD_XRAM_BRDCAST ", 65 "INIT_CMD_UPDT_IDLE ", 66 "INIT_CMD_WRITE_BRDCAST ", 67 "INIT_CMD_UPDT_NLINE ", 68 "INIT_CMD_UPDT_INDEX ", 69 "INIT_CMD_UPDT_DATA ", 70 "INIT_CMD_SC_UPDT_IDLE ", 71 "INIT_CMD_SC_BRDCAST ", 72 "INIT_CMD_SC_UPDT_NLINE ", 73 "INIT_CMD_SC_UPDT_INDEX ", 74 "INIT_CMD_SC_UPDT_DATA ", 76 75 "INIT_CMD_SC_UPDT_DATA_HIGH", 77 76 }; 78 77 const char *init_rsp_fsm_str[] = { 79 "INIT_RSP_IDLE ",80 "INIT_RSP_UPT_LOCK ",78 "INIT_RSP_IDLE ", 79 "INIT_RSP_UPT_LOCK ", 81 80 "INIT_RSP_UPT_CLEAR", 82 "INIT_RSP_END ",81 "INIT_RSP_END ", 83 82 }; 84 83 const char *read_fsm_str[] = { 85 "READ_IDLE ",86 "READ_DIR_LOCK ",87 "READ_DIR_HIT ",88 "READ_HEAP_LOCK ",84 "READ_IDLE ", 85 "READ_DIR_LOCK ", 86 "READ_DIR_HIT ", 87 "READ_HEAP_LOCK ", 89 88 "READ_HEAP_WRITE", 90 89 "READ_HEAP_ERASE", 91 "READ_HEAP_LAST ",92 "READ_RSP ",93 "READ_TRT_LOCK ",94 "READ_TRT_SET ",95 "READ_XRAM_REQ ",90 "READ_HEAP_LAST ", 91 "READ_RSP ", 92 "READ_TRT_LOCK ", 93 "READ_TRT_SET ", 94 "READ_XRAM_REQ ", 96 95 }; 97 96 const char *write_fsm_str[] = { 98 "WRITE_IDLE ",99 "WRITE_NEXT ",100 "WRITE_DIR_LOCK ",101 "WRITE_DIR_HIT_READ ",102 "WRITE_DIR_HIT ",103 "WRITE_UPT_LOCK ",104 "WRITE_HEAP_LOCK ",105 "WRITE_UPT_REQ ",106 "WRITE_UPDATE ",107 "WRITE_UPT_DEC ",108 "WRITE_RSP ",109 "WRITE_TRT_LOCK ",110 "WRITE_TRT_DATA ",111 "WRITE_TRT_SET ",112 "WRITE_WAIT ",113 "WRITE_XRAM_REQ ",97 "WRITE_IDLE ", 98 "WRITE_NEXT ", 99 "WRITE_DIR_LOCK ", 100 "WRITE_DIR_HIT_READ ", 101 "WRITE_DIR_HIT ", 102 "WRITE_UPT_LOCK ", 103 "WRITE_HEAP_LOCK ", 104 "WRITE_UPT_REQ ", 105 "WRITE_UPDATE ", 106 "WRITE_UPT_DEC ", 107 "WRITE_RSP ", 108 "WRITE_TRT_LOCK ", 109 "WRITE_TRT_DATA ", 110 "WRITE_TRT_SET ", 111 "WRITE_WAIT ", 112 "WRITE_XRAM_REQ ", 114 113 "WRITE_TRT_WRITE_LOCK", 115 "WRITE_INVAL_LOCK ",116 "WRITE_DIR_INVAL ",117 "WRITE_INVAL ",118 "WRITE_XRAM_SEND ",114 "WRITE_INVAL_LOCK ", 115 "WRITE_DIR_INVAL ", 116 "WRITE_INVAL ", 117 "WRITE_XRAM_SEND ", 119 118 }; 120 119 const char *ixr_rsp_fsm_str[] = { 121 "IXR_RSP_IDLE ",122 "IXR_RSP_ACK ",120 "IXR_RSP_IDLE ", 121 "IXR_RSP_ACK ", 123 122 "IXR_RSP_TRT_ERASE", 124 "IXR_RSP_TRT_READ ",123 "IXR_RSP_TRT_READ ", 125 124 }; 126 125 const char *xram_rsp_fsm_str[] = { 127 "XRAM_RSP_IDLE ",128 "XRAM_RSP_TRT_COPY ",129 "XRAM_RSP_TRT_DIRTY ",130 "XRAM_RSP_DIR_LOCK ",131 "XRAM_RSP_DIR_UPDT ",132 "XRAM_RSP_DIR_RSP ",133 "XRAM_RSP_INVAL_LOCK ",134 "XRAM_RSP_INVAL_WAIT ",135 "XRAM_RSP_INVAL ",126 "XRAM_RSP_IDLE ", 127 "XRAM_RSP_TRT_COPY ", 128 "XRAM_RSP_TRT_DIRTY ", 129 "XRAM_RSP_DIR_LOCK ", 130 "XRAM_RSP_DIR_UPDT ", 131 "XRAM_RSP_DIR_RSP ", 132 "XRAM_RSP_INVAL_LOCK ", 133 "XRAM_RSP_INVAL_WAIT ", 134 "XRAM_RSP_INVAL ", 136 135 "XRAM_RSP_WRITE_DIRTY", 137 "XRAM_RSP_HEAP_ERASE ",138 "XRAM_RSP_HEAP_LAST ",136 "XRAM_RSP_HEAP_ERASE ", 137 "XRAM_RSP_HEAP_LAST ", 139 138 }; 140 139 const char *ixr_cmd_fsm_str[] = { 141 "IXR_CMD_READ_IDLE ",142 "IXR_CMD_WRITE_IDLE ",143 "IXR_CMD_LLSC_IDLE ",144 "IXR_CMD_XRAM_IDLE ",145 "IXR_CMD_READ_NLINE ",146 "IXR_CMD_WRITE_NLINE ",147 "IXR_CMD_LLSC_NLINE ",148 "IXR_CMD_XRAM_DATA ",140 "IXR_CMD_READ_IDLE ", 141 "IXR_CMD_WRITE_IDLE ", 142 "IXR_CMD_LLSC_IDLE ", 143 "IXR_CMD_XRAM_IDLE ", 144 "IXR_CMD_READ_NLINE ", 145 "IXR_CMD_WRITE_NLINE ", 146 "IXR_CMD_LLSC_NLINE ", 147 "IXR_CMD_XRAM_DATA ", 149 148 }; 150 149 const char *llsc_fsm_str[] = { 151 "LLSC_IDLE ",152 "SC_DIR_LOCK ",153 "SC_DIR_HIT_READ ",150 "LLSC_IDLE ", 151 "SC_DIR_LOCK ", 152 "SC_DIR_HIT_READ ", 154 153 "SC_DIR_HIT_WRITE", 155 "SC_UPT_LOCK ",156 "SC_WAIT ",157 "SC_HEAP_LOCK ",158 "SC_UPT_REQ ",159 "SC_UPDATE ",160 "SC_TRT_LOCK ",161 "SC_INVAL_LOCK ",162 "SC_DIR_INVAL ",163 "SC_INVAL ",164 "SC_XRAM_SEND ",165 "SC_RSP_FALSE ",166 "SC_RSP_TRUE ",167 "LLSC_TRT_LOCK ",168 "LLSC_TRT_SET ",169 "LLSC_XRAM_REQ ",154 "SC_UPT_LOCK ", 155 "SC_WAIT ", 156 "SC_HEAP_LOCK ", 157 "SC_UPT_REQ ", 158 "SC_UPDATE ", 159 "SC_TRT_LOCK ", 160 "SC_INVAL_LOCK ", 161 "SC_DIR_INVAL ", 162 "SC_INVAL ", 163 "SC_XRAM_SEND ", 164 "SC_RSP_FALSE ", 165 "SC_RSP_TRUE ", 166 "LLSC_TRT_LOCK ", 167 "LLSC_TRT_SET ", 168 "LLSC_XRAM_REQ ", 170 169 }; 171 170 const char *cleanup_fsm_str[] = { 172 "CLEANUP_IDLE ",173 "CLEANUP_DIR_LOCK ",174 "CLEANUP_DIR_WRITE ",175 "CLEANUP_HEAP_LOCK ",171 "CLEANUP_IDLE ", 172 "CLEANUP_DIR_LOCK ", 173 "CLEANUP_DIR_WRITE ", 174 "CLEANUP_HEAP_LOCK ", 176 175 "CLEANUP_HEAP_SEARCH", 177 "CLEANUP_HEAP_CLEAN ",178 "CLEANUP_HEAP_FREE ",179 "CLEANUP_UPT_LOCK ",180 "CLEANUP_UPT_WRITE ",181 "CLEANUP_WRITE_RSP ",182 "CLEANUP_RSP ",176 "CLEANUP_HEAP_CLEAN ", 177 "CLEANUP_HEAP_FREE ", 178 "CLEANUP_UPT_LOCK ", 179 "CLEANUP_UPT_WRITE ", 180 "CLEANUP_WRITE_RSP ", 181 "CLEANUP_RSP ", 183 182 }; 184 183 const char *alloc_dir_fsm_str[] = { 185 "ALLOC_DIR_READ ",186 "ALLOC_DIR_WRITE ",187 "ALLOC_DIR_LLSC ",188 "ALLOC_DIR_CLEANUP ",184 "ALLOC_DIR_READ ", 185 "ALLOC_DIR_WRITE ", 186 "ALLOC_DIR_LLSC ", 187 "ALLOC_DIR_CLEANUP ", 189 188 "ALLOC_DIR_XRAM_RSP", 190 189 }; 191 190 const char *alloc_trt_fsm_str[] = { 192 "ALLOC_TRT_READ ",193 "ALLOC_TRT_WRITE ",194 "ALLOC_TRT_LLSC ",191 "ALLOC_TRT_READ ", 192 "ALLOC_TRT_WRITE ", 193 "ALLOC_TRT_LLSC ", 195 194 "ALLOC_TRT_XRAM_RSP", 196 "ALLOC_TRT_IXR_RSP ",195 "ALLOC_TRT_IXR_RSP ", 197 196 }; 198 197 const char *alloc_upt_fsm_str[] = { 199 "ALLOC_UPT_WRITE ",198 "ALLOC_UPT_WRITE ", 200 199 "ALLOC_UPT_XRAM_RSP", 201 200 "ALLOC_UPT_INIT_RSP", 202 "ALLOC_UPT_CLEANUP ",201 "ALLOC_UPT_CLEANUP ", 203 202 }; 204 203 const char *alloc_heap_fsm_str[] = { 205 "ALLOC_HEAP_READ ",206 "ALLOC_HEAP_WRITE ",207 "ALLOC_HEAP_LLSC ",208 "ALLOC_HEAP_CLEANUP ",204 "ALLOC_HEAP_READ ", 205 "ALLOC_HEAP_WRITE ", 206 "ALLOC_HEAP_LLSC ", 207 "ALLOC_HEAP_CLEANUP ", 209 208 "ALLOC_HEAP_XRAM_RSP", 210 209 }; 211 212 #endif213 210 214 211 #define tmpl(x) template<typename vci_param> x VciMemCacheV4<vci_param> … … 322 319 323 320 // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum 324 broadcast_addr= 0x3 | (0x7C1F << (vci_param::N-20));321 m_broadcast_address = 0x3 | (0x7C1F << (vci_param::N-20)); 325 322 326 323 // Get the segments associated to the MemCache … … 396 393 397 394 } // end constructor 395 396 ////////////////////////////////////////////////// 397 // This function prints a trace of internal states 398 ////////////////////////////////////////////////// 399 400 tmpl(void)::print_trace() 401 { 402 std::cout << "MEM_CACHE " << name() << std::endl; 403 std::cout << " / " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] 404 << " / " << read_fsm_str[r_read_fsm] 405 << " / " << write_fsm_str[r_write_fsm] 406 << " / " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] 407 << " / " << init_cmd_fsm_str[r_init_cmd_fsm] 408 << " / " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl; 409 } 398 410 399 411 ///////////////////////////////////////// … … 607 619 #endif 608 620 609 610 621 //////////////////////////////////////////////////////////////////////////////////// 611 622 // TGT_CMD FSM … … 630 641 { 631 642 if ( p_vci_tgt.cmdval ) { 632 assert( (p_vci_tgt.srcid.read() < m_initiators) 633 && "VCI_MEM_CACHE error in VCI_MEM_CACHE : Thereceived SRCID is larger than the number of initiators");643 assert( (p_vci_tgt.srcid.read() < m_initiators) && 644 "VCI_MEM_CACHE error in direct request : received SRCID is larger than the number of initiators"); 634 645 635 646 bool reached = false; … … 646 657 if ( !reached ) 647 658 { 648 std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE"<< std::endl;659 std::cout << "VCI_MEM_CACHE Out of segment access in " << name() << std::endl; 649 660 std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl; 650 661 std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl; … … 2315 2326 case CLEANUP_IDLE: 2316 2327 { 2317 2318 2328 if ( p_vci_tgt_cleanup.cmdval.read() ) { 2319 2329 assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) && 2320 "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than the number of initiators"); 2330 "VCI_MEM_CACHE error in a cleanup request : received SRCID is larger than the number of initiators"); 2331 2321 2332 bool reached = false; 2322 2333 for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){ … … 2325 2336 } 2326 2337 } 2338 // only write request to a mapped address that are not broadcast are handled 2327 2339 if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) && 2328 (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&2329 reached) {2330 2340 ((p_vci_tgt_cleanup.address.read() & 0x3) == 0) && 2341 reached) 2342 { 2331 2343 m_cpt_cleanup++; 2332 2344 … … 2575 2587 if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP ) 2576 2588 { 2577 size_t index ;2589 size_t index = 0; 2578 2590 bool hit_inval; 2579 2591 hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index); … … 4106 4118 // Command signals on the p_vci_ixr port 4107 4119 //////////////////////////////////////////////////////////// 4108 4109 4120 4110 4121 p_vci_ixr.be = 0xF; … … 4333 4344 case INIT_CMD_XRAM_BRDCAST: 4334 4345 p_vci_ini.cmdval = true; 4335 p_vci_ini.address = broadcast_addr;4346 p_vci_ini.address = m_broadcast_address; 4336 4347 p_vci_ini.wdata = (uint32_t)r_xram_rsp_to_init_cmd_nline.read(); 4337 4348 p_vci_ini.be = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3); … … 4343 4354 case INIT_CMD_WRITE_BRDCAST: 4344 4355 p_vci_ini.cmdval = true; 4345 p_vci_ini.address = broadcast_addr;4356 p_vci_ini.address = m_broadcast_address; 4346 4357 p_vci_ini.wdata = (addr_t)r_write_to_init_cmd_nline.read(); 4347 4358 p_vci_ini.be = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3); … … 4398 4409 case INIT_CMD_SC_BRDCAST: 4399 4410 p_vci_ini.cmdval = true; 4400 p_vci_ini.address = broadcast_addr;4411 p_vci_ini.address = m_broadcast_address; 4401 4412 p_vci_ini.wdata = (addr_t)r_llsc_to_init_cmd_nline.read(); 4402 4413 p_vci_ini.be = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
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