Changeset 119 for trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Timestamp:
- Dec 6, 2010, 6:12:46 AM (14 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper2_v1.h (modified) (2 diffs)
-
src/vci_cc_vcache_wrapper2_v1.cpp (modified) (59 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r88 r119 68 68 ICACHE_TLB1_READ, // 02 69 69 ICACHE_TLB1_WRITE, // 03 70 ICACHE_TLB1_UPDT, // 04 71 ICACHE_TLB2_READ, // 05 72 ICACHE_TLB2_WRITE, // 06 73 ICACHE_TLB2_UPDT, // 07 74 ICACHE_SW_FLUSH, // 08 75 ICACHE_TLB_FLUSH, // 09 76 ICACHE_CACHE_FLUSH, // 0a 77 ICACHE_TLB_INVAL, // 0b 78 ICACHE_CACHE_INVAL, // 0c 79 ICACHE_CACHE_INVAL_PA, // 0d 80 ICACHE_MISS_WAIT, // 0e 81 ICACHE_UNC_WAIT, // 0f 82 ICACHE_MISS_UPDT, // 10 83 ICACHE_ERROR, // 11 84 ICACHE_CC_INVAL, // 12 85 ICACHE_TLB_CC_INVAL, // 13 70 ICACHE_TLB1_UPDT_SEL, // 04 71 ICACHE_TLB1_UPDT, // 05 72 ICACHE_TLB2_READ, // 06 73 ICACHE_TLB2_WRITE, // 07 74 ICACHE_TLB2_UPDT_SEL, // 08 75 ICACHE_TLB2_UPDT, // 09 76 ICACHE_SW_FLUSH, // 0a 77 ICACHE_TLB_FLUSH, // 0b 78 ICACHE_CACHE_FLUSH, // 0c 79 ICACHE_TLB_INVAL, // 0d 80 ICACHE_CACHE_INVAL, // 0e 81 ICACHE_CACHE_INVAL_PA, // 0f 82 ICACHE_MISS_WAIT, // 10 83 ICACHE_UNC_WAIT, // 11 84 ICACHE_MISS_UPDT, // 12 85 ICACHE_ERROR, // 13 86 ICACHE_CC_INVAL, // 14 87 ICACHE_TLB_CC_INVAL, // 15 86 88 }; 87 89 … … 94 96 DCACHE_TLB1_READ, // 05 95 97 DCACHE_TLB1_READ_UPDT, // 06 96 DCACHE_TLB1_UPDT, // 07 97 DCACHE_DTLB2_READ_CACHE, // 08 98 DCACHE_TLB2_LL_WAIT, // 09 99 DCACHE_TLB2_SC_WAIT, // 0a 100 DCACHE_TLB2_READ, // 0b 101 DCACHE_TLB2_READ_UPDT, // 0c 102 DCACHE_TLB2_UPDT, // 0d 103 DCACHE_CTXT_SWITCH, // 0e 104 DCACHE_ICACHE_FLUSH, // 0f 105 DCACHE_DCACHE_FLUSH, // 10 106 DCACHE_ITLB_INVAL, // 11 107 DCACHE_DTLB_INVAL, // 12 108 DCACHE_ICACHE_INVAL, // 13 109 DCACHE_DCACHE_INVAL, // 14 110 DCACHE_ICACHE_INVAL_PA, // 15 111 DCACHE_DCACHE_INVAL_PA, // 16 112 DCACHE_DCACHE_SYNC, // 17 113 DCACHE_LL_DIRTY_WAIT, // 18 114 DCACHE_SC_DIRTY_WAIT, // 19 115 DCACHE_WRITE_UPDT, // 1a 116 DCACHE_WRITE_DIRTY, // 1b 117 DCACHE_WRITE_REQ, // 1c 118 DCACHE_MISS_WAIT, // 1d 119 DCACHE_MISS_UPDT, // 1e 120 DCACHE_UNC_WAIT, // 1f 121 DCACHE_ERROR, // 20 122 DCACHE_ITLB_READ, // 21 123 DCACHE_ITLB_UPDT, // 22 124 DCACHE_ITLB_LL_WAIT, // 23 125 DCACHE_ITLB_SC_WAIT, // 24 126 DCACHE_CC_CHECK, // 25 127 DCACHE_CC_INVAL, // 26 128 DCACHE_CC_UPDT, // 27 129 DCACHE_CC_NOP, // 28 130 DCACHE_TLB_CC_INVAL, // 29 131 DCACHE_ITLB_CLEANUP, // 2a 98 DCACHE_TLB1_UPDT_SEL, // 07 99 DCACHE_TLB1_UPDT, // 08 100 DCACHE_DTLB2_READ_CACHE, // 09 101 DCACHE_TLB2_LL_WAIT, // 0a 102 DCACHE_TLB2_SC_WAIT, // 0b 103 DCACHE_TLB2_READ, // 0c 104 DCACHE_TLB2_READ_UPDT, // 0d 105 DCACHE_TLB2_UPDT_SEL, // 0e 106 DCACHE_TLB2_UPDT, // 0f 107 DCACHE_CTXT_SWITCH, // 10 108 DCACHE_ICACHE_FLUSH, // 11 109 DCACHE_DCACHE_FLUSH, // 12 110 DCACHE_ITLB_INVAL, // 13 111 DCACHE_DTLB_INVAL, // 14 112 DCACHE_ICACHE_INVAL, // 15 113 DCACHE_DCACHE_INVAL, // 16 114 DCACHE_ICACHE_INVAL_PA, // 17 115 DCACHE_DCACHE_INVAL_PA, // 18 116 DCACHE_DCACHE_SYNC, // 19 117 DCACHE_LL_DIRTY_WAIT, // 1a 118 DCACHE_SC_DIRTY_WAIT, // 1b 119 DCACHE_WRITE_UPDT, // 1c 120 DCACHE_WRITE_DIRTY, // 1d 121 DCACHE_WRITE_REQ, // 1e 122 DCACHE_MISS_WAIT, // 1f 123 DCACHE_MISS_UPDT, // 20 124 DCACHE_UNC_WAIT, // 21 125 DCACHE_ERROR, // 22 126 DCACHE_ITLB_READ, // 23 127 DCACHE_ITLB_UPDT, // 24 128 DCACHE_ITLB_LL_WAIT, // 25 129 DCACHE_ITLB_SC_WAIT, // 26 130 DCACHE_CC_CHECK, // 27 131 DCACHE_CC_INVAL, // 28 132 DCACHE_CC_UPDT, // 29 133 DCACHE_CC_NOP, // 2a 134 DCACHE_TLB_CC_INVAL, // 2b 135 DCACHE_ITLB_CLEANUP, // 2c 132 136 }; 133 137 -
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r108 r119 40 40 "ICACHE_BIS", 41 41 "ICACHE_TLB1_READ", 42 "ICACHE_TLB1_WRITE", 42 "ICACHE_TLB1_WRITE", 43 "ICACHE_TLB1_UPDT_SEL", 43 44 "ICACHE_TLB1_UPDT", 44 45 "ICACHE_TLB2_READ", 45 "ICACHE_TLB2_WRITE", 46 "ICACHE_TLB2_WRITE", 47 "ICACHE_TLB2_UPDT_SEL", 46 48 "ICACHE_TLB2_UPDT", 47 49 "ICACHE_SW_FLUSH", … … 65 67 "DCACHE_TLB1_SC_WAIT", 66 68 "DCACHE_TLB1_READ", 67 "DCACHE_TLB1_READ_UPDT", 69 "DCACHE_TLB1_READ_UPDT", 70 "DCACHE_TLB1_UPDT_SEL", 68 71 "DCACHE_TLB1_UPDT", 69 72 "DCACHE_DTLB2_READ_CACHE", … … 72 75 "DCACHE_TLB2_READ", 73 76 "DCACHE_TLB2_READ_UPDT", 77 "DCACHE_TLB2_UPDT_SEL", 74 78 "DCACHE_TLB2_UPDT", 75 79 "DCACHE_CTXT_SWITCH", … … 1117 1121 if ( !icache_hit_c ) 1118 1122 { 1119 m_cpt_ins_miss++;1120 m_cost_ins_miss_frz++;1121 1123 if ( icache_cached ) 1122 1124 { … … 1125 1127 r_icache_vaddr_req = ireq.addr; 1126 1128 r_icache_fsm = ICACHE_MISS_WAIT; 1129 m_cpt_ins_miss++; 1130 m_cost_ins_miss_frz++; 1127 1131 } 1128 1132 else … … 1150 1154 case ICACHE_BIS: 1151 1155 { 1156 if ( ireq.valid ) m_cost_ins_miss_frz++; 1157 1152 1158 // external cache invalidate request 1153 1159 if ( r_tgt_icache_req ) 1154 1160 { 1155 if ( ireq.valid ) m_cost_ins_miss_frz++;1156 1161 r_icache_fsm = ICACHE_CC_INVAL; 1157 1162 r_icache_fsm_save = r_icache_fsm; … … 1162 1167 if ( r_dcache_itlb_inval_req ) 1163 1168 { 1164 if ( ireq.valid ) m_cost_ins_miss_frz++;1165 1169 r_itlb_inval_req = true; 1166 1170 r_icache_fsm = ICACHE_TLB_CC_INVAL; … … 1172 1176 if ( r_icache_inval_tlb_rsp ) 1173 1177 { 1174 if ( ireq.valid ) m_cost_ins_miss_frz++;1175 1178 r_icache_inval_tlb_rsp = false; 1176 1179 r_icache_fsm = ICACHE_IDLE; … … 1284 1287 { 1285 1288 r_icache_pte_update = r_dcache_rsp_itlb_miss; 1286 r_icache_fsm = ICACHE_TLB1_UPDT ;1289 r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 1287 1290 } 1288 1291 else … … 1300 1303 { 1301 1304 r_icache_pte_update = r_dcache_rsp_itlb_miss; 1302 r_icache_fsm = ICACHE_TLB1_UPDT ;1305 r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 1303 1306 } 1304 1307 else … … 1377 1380 else 1378 1381 { 1379 r_icache_fsm = ICACHE_TLB1_UPDT ;1382 r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 1380 1383 } 1381 1384 } … … 1405 1408 } 1406 1409 ////////////////////// 1407 case ICACHE_TLB1_UPDT :1410 case ICACHE_TLB1_UPDT_SEL: 1408 1411 { 1409 1412 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1413 m_cost_ins_tlb_update_acc_frz++; 1410 1414 1411 1415 // external cache invalidate request … … 1426 1430 } 1427 1431 1428 // TLB update and invalidate different PTE1429 if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )1430 {1431 paddr_t victim_index = 0;1432 r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);1433 r_dcache_itlb_cleanup_line = victim_index;1434 m_cpt_cc_cleanup_ins++;1435 r_icache_fsm = ICACHE_IDLE;1436 }1437 1438 1432 // TLB update and invalidate same PTE 1439 1433 if ( r_icache_inval_tlb_rsp ) … … 1441 1435 r_icache_inval_tlb_rsp = false; 1442 1436 r_icache_fsm = ICACHE_IDLE; 1443 } 1437 break; 1438 } 1439 1440 if ( r_dcache_itlb_cleanup_req ) break; 1441 1442 size_t way = 0; 1443 size_t set = 0; 1444 paddr_t victim_index = 0; 1445 1446 bool cleanup = icache_tlb.select((r_icache_vaddr_req.read()>> PAGE_M_NBITS),&victim_index,&way,&set); 1447 r_icache_way = way; 1448 r_icache_set = set; 1449 if (cleanup) 1450 { 1451 r_dcache_itlb_cleanup_req = true; 1452 r_dcache_itlb_cleanup_line = victim_index; 1453 m_cpt_cc_cleanup_ins++; 1454 } 1455 r_icache_fsm = ICACHE_TLB1_UPDT; 1456 break; 1457 } 1458 ///////////////////// 1459 case ICACHE_TLB1_UPDT: 1460 { 1461 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1462 m_cost_ins_tlb_update_acc_frz++; 1463 1464 icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2))); 1465 r_icache_fsm = ICACHE_IDLE; 1444 1466 break; 1445 1467 } … … 1494 1516 if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set 1495 1517 { 1496 r_icache_fsm = ICACHE_TLB2_UPDT ;1518 r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 1497 1519 r_icache_pte_update = r_dcache_rsp_itlb_miss; 1498 1520 } … … 1510 1532 if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set 1511 1533 { 1512 r_icache_fsm = ICACHE_TLB2_UPDT ;1534 r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 1513 1535 r_icache_pte_update = r_dcache_rsp_itlb_miss; 1514 1536 } … … 1588 1610 else 1589 1611 { 1590 r_icache_fsm = ICACHE_TLB2_UPDT ;1612 r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 1591 1613 } 1592 1614 } … … 1615 1637 break; 1616 1638 } 1617 ///////////////////// 1618 case ICACHE_TLB2_UPDT :1639 ////////////////////////// 1640 case ICACHE_TLB2_UPDT_SEL: 1619 1641 { 1620 1642 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1643 m_cost_ins_tlb_update_acc_frz++; 1621 1644 1622 1645 // external cache invalidate request … … 1637 1660 } 1638 1661 1639 // TLB update and invalidate different PTE1640 if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )1641 {1642 paddr_t victim_index = 0;1643 r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);1644 r_dcache_itlb_cleanup_line = victim_index;1645 m_cpt_cc_cleanup_ins++;1646 r_icache_fsm = ICACHE_IDLE;1647 }1648 1662 // TLB update and invalidate same PTE 1649 1663 if ( r_icache_inval_tlb_rsp ) … … 1651 1665 r_icache_inval_tlb_rsp = false; 1652 1666 r_icache_fsm = ICACHE_IDLE; 1653 } 1654 break; 1667 break; 1668 } 1669 1670 if ( r_dcache_itlb_cleanup_req ) break; 1671 1672 size_t way = 0; 1673 size_t set = 0; 1674 paddr_t victim_index = 0; 1675 1676 bool cleanup = icache_tlb.select((r_icache_vaddr_req.read()>> PAGE_K_NBITS),&victim_index,&way,&set); 1677 r_icache_way = way; 1678 r_icache_set = set; 1679 if (cleanup) 1680 { 1681 r_dcache_itlb_cleanup_req = true; 1682 r_dcache_itlb_cleanup_line = victim_index; 1683 m_cpt_cc_cleanup_ins++; 1684 } 1685 r_icache_fsm = ICACHE_TLB2_UPDT; 1686 break; 1687 } 1688 ///////////////////// 1689 case ICACHE_TLB2_UPDT: 1690 { 1691 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1692 m_cost_ins_tlb_update_acc_frz++; 1693 1694 icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2))); 1695 r_icache_fsm = ICACHE_IDLE; 1696 break; 1655 1697 } 1656 1698 ///////////////////////////// … … 1988 2030 1989 2031 r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); 1990 r_icache_cleanup_line = victim_index; m_cpt_cc_cleanup_ins++; 2032 r_icache_cleanup_line = victim_index; 2033 m_cpt_cc_cleanup_ins++; 1991 2034 r_icache_fsm = ICACHE_IDLE; 1992 2035 } … … 2014 2057 m_cost_ins_miss_frz++; 2015 2058 } 2016 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )||2017 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE )||2018 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))&& (ireq.valid) )2059 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 2060 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 2061 ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && (ireq.valid) ) 2019 2062 { 2020 2063 m_cost_ins_tlb_miss_frz++; … … 2045 2088 m_cost_ins_miss_frz++; 2046 2089 } 2047 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )||2048 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE )||2049 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))&& (ireq.valid) )2090 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 2091 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 2092 ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && (ireq.valid) ) 2050 2093 { 2051 2094 m_cost_ins_tlb_miss_frz++; … … 2054 2097 if ( r_itlb_inval_req ) break; 2055 2098 // invalidate cache 2056 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) ||2057 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||2058 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT)) &&2099 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 2100 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 2101 ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && 2059 2102 (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 2060 2103 { … … 2074 2117 } 2075 2118 } // end switch r_icache_fsm 2076 2077 2119 #ifdef SOCLIB_MODULE_DEBUG 2078 2120 std::cout << name() << " Instruction Response: " << irsp << std::endl; … … 2293 2335 else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit 2294 2336 { 2337 if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 2338 2295 2339 data_t rsp_itlb_miss; 2296 2340 bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss); … … 2765 2809 } 2766 2810 break; 2767 /*2768 case iss_t::DATA_READ:2769 m_cpt_read++;2770 if ( dcache_hit_c )2771 {2772 r_dcache_buf_unc_valid = false;2773 r_dcache_fsm = DCACHE_IDLE;2774 drsp.valid = true;2775 drsp.rdata = dcache_rdata;2776 }2777 else2778 {2779 if ( dcache_cached )2780 {2781 r_dcache_miss_req = true;2782 r_dcache_fsm = DCACHE_MISS_WAIT;2783 m_cpt_data_miss++;2784 m_cost_data_miss_frz++;2785 }2786 else2787 {2788 r_dcache_unc_req = true;2789 r_dcache_fsm = DCACHE_UNC_WAIT;2790 m_cpt_unc_read++;2791 m_cost_unc_read_frz++;2792 }2793 }2794 break;2795 case iss_t::DATA_LL:2796 if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr) && r_dcache_buf_unc_valid)2797 {2798 r_dcache_buf_unc_valid = false;2799 r_dcache_fsm = DCACHE_IDLE;2800 drsp.valid = true;2801 drsp.rdata = dcache_rdata;2802 }2803 else2804 {2805 r_dcache_llsc_reserved = true;2806 r_dcache_llsc_addr_save = tlb_dpaddr;2807 r_dcache_unc_req = true;2808 r_dcache_fsm = DCACHE_UNC_WAIT;2809 }2810 break;2811 case iss_t::DATA_SC:2812 if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr))2813 {2814 r_dcache_llsc_reserved = false;2815 r_dcache_unc_req = true;2816 r_dcache_fsm = DCACHE_UNC_WAIT;2817 }2818 else2819 {2820 if ( r_dcache_buf_unc_valid )2821 {2822 r_dcache_llsc_reserved = false;2823 r_dcache_buf_unc_valid = false;2824 drsp.valid = true;2825 drsp.rdata = dcache_rdata;2826 }2827 r_dcache_fsm = DCACHE_IDLE;2828 }2829 break;2830 */2831 2811 case iss_t::DATA_WRITE: 2832 2812 m_cpt_write++; … … 2918 2898 case DCACHE_BIS: 2919 2899 { 2900 if ( dreq.valid ) m_cost_data_miss_frz++; 2901 2920 2902 // external cache invalidate request 2921 2903 if ( r_tgt_dcache_req ) … … 2923 2905 r_dcache_fsm = DCACHE_CC_CHECK; 2924 2906 r_dcache_fsm_save = r_dcache_fsm; 2925 if ( dreq.valid ) m_cost_data_miss_frz++;2926 2907 break; 2927 2908 } … … 2932 2913 r_dcache_inval_tlb_rsp = false; 2933 2914 r_dcache_fsm = DCACHE_IDLE; 2934 if ( dreq.valid ) m_cost_data_miss_frz++;2935 2915 break; 2936 2916 } … … 3228 3208 r_dcache_tlb_ll_dirty_req = true; 3229 3209 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3230 //m_cpt_dcache_data_write++;3231 3210 m_cpt_data_tlb_update_dirty++; 3232 3211 m_cost_data_tlb_update_dirty_frz++; … … 3251 3230 { 3252 3231 r_dcache_pte_update = tlb_data; 3253 r_dcache_fsm = DCACHE_TLB1_UPDT ;3232 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3254 3233 } 3255 3234 else … … 3267 3246 { 3268 3247 r_dcache_pte_update = tlb_data; 3269 r_dcache_fsm = DCACHE_TLB1_UPDT ;3248 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3270 3249 } 3271 3250 else … … 3292 3271 { 3293 3272 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3294 m_cost_data_tlb_update_acc_frz++; 3273 m_cost_data_tlb_update_acc_frz++; 3274 3295 3275 // external cache invalidate request 3296 3276 if ( r_tgt_dcache_req ) … … 3414 3394 bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update); 3415 3395 assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 3416 r_dcache_fsm = DCACHE_TLB1_UPDT ;3396 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3417 3397 m_cpt_dcache_data_write++; 3418 3398 } … … 3579 3559 r_dcache_tlb_ll_dirty_req = true; 3580 3560 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3581 //m_cpt_dcache_data_write++;3582 3561 m_cpt_data_tlb_update_dirty++; 3583 3562 m_cost_data_tlb_update_dirty_frz++; … … 3601 3580 { 3602 3581 r_dcache_pte_update = rsp_dtlb_miss; 3603 r_dcache_fsm = DCACHE_TLB1_UPDT ;3582 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3604 3583 } 3605 3584 else … … 3617 3596 { 3618 3597 r_dcache_pte_update = rsp_dtlb_miss; 3619 r_dcache_fsm = DCACHE_TLB1_UPDT ;3598 r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 3620 3599 } 3621 3600 else … … 3632 3611 break; 3633 3612 } 3634 ////////////////////// 3635 case DCACHE_TLB1_UPDT :3613 ///////////////////////// 3614 case DCACHE_TLB1_UPDT_SEL: 3636 3615 { 3637 3616 m_cost_data_tlb_miss_frz++; 3638 3617 m_cost_data_tlb_update_acc_frz++; 3618 3639 3619 // external cache invalidate request 3640 3620 if ( r_tgt_dcache_req ) … … 3647 3627 if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp ) 3648 3628 { 3629 size_t way = 0; 3630 size_t set = 0; 3649 3631 paddr_t victim_index = 0; 3650 if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index)) 3651 { 3652 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 3653 } 3654 bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 3655 assert(set_hit && "TLB1_UPDT set hit error"); 3656 r_dcache_fsm = DCACHE_IDLE; 3632 bool cleanup = dcache_tlb.select((dreq.addr >> PAGE_M_NBITS),&victim_index,&way,&set); 3633 if (cleanup) 3634 { 3635 r_dcache_dtlb_cleanup_req = true; 3636 r_dcache_dtlb_cleanup_line = victim_index; 3637 m_cpt_cc_cleanup_data++; 3638 } 3639 r_dcache_way = way; 3640 r_dcache_set = set; 3641 r_dcache_fsm = DCACHE_TLB1_UPDT; 3657 3642 } 3658 3643 else … … 3663 3648 } 3664 3649 break; 3650 } 3651 ////////////////////// 3652 case DCACHE_TLB1_UPDT: 3653 { 3654 m_cost_data_tlb_miss_frz++; 3655 m_cost_data_tlb_update_acc_frz++; 3656 3657 if (r_dcache_dtlb_cleanup_req) r_dcache.setinbit(r_dcache_dtlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 3658 bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 3659 assert(set_hit && "TLB1_UPDT set hit error"); 3660 dcache_tlb.update(r_dcache_pte_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2))); 3661 r_dcache_fsm = DCACHE_IDLE; 3662 break; 3665 3663 } 3666 3664 ///////////////////////////// … … 3715 3713 r_dcache_pte_update = tlb_data; 3716 3714 r_dcache_ppn_update = tlb_data_ppn; 3717 r_dcache_fsm = DCACHE_TLB2_UPDT ;3715 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3718 3716 } 3719 3717 else … … 3726 3724 r_dcache_pte_update = tlb_data; 3727 3725 r_dcache_ppn_update = tlb_data_ppn; 3728 r_dcache_fsm = DCACHE_TLB2_UPDT ;3726 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3729 3727 } 3730 3728 else … … 3744 3742 r_dcache_pte_update = tlb_data; 3745 3743 r_dcache_ppn_update = tlb_data_ppn; 3746 r_dcache_fsm = DCACHE_TLB2_UPDT ;3744 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3747 3745 } 3748 3746 else … … 3893 3891 bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update); 3894 3892 assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 3895 r_dcache_fsm = DCACHE_TLB2_UPDT ;3893 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 3896 3894 m_cpt_dcache_data_write++; 3897 3895 } … … 4044 4042 r_dcache_pte_update = rsp_dtlb_miss; 4045 4043 r_dcache_ppn_update = tlb_data_ppn; 4046 r_dcache_fsm = DCACHE_TLB2_UPDT ;4044 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 4047 4045 } 4048 4046 else … … 4054 4052 r_dcache_pte_update = rsp_dtlb_miss; 4055 4053 r_dcache_ppn_update = tlb_data_ppn; 4056 r_dcache_fsm = DCACHE_TLB2_UPDT ;4054 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 4057 4055 } 4058 4056 else … … 4072 4070 r_dcache_pte_update = rsp_dtlb_miss; 4073 4071 r_dcache_ppn_update = tlb_data_ppn; 4074 r_dcache_fsm = DCACHE_TLB2_UPDT ;4072 r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 4075 4073 } 4076 4074 else … … 4088 4086 break; 4089 4087 } 4090 ////////////////////// 4091 case DCACHE_TLB2_UPDT :4088 ////////////////////////// 4089 case DCACHE_TLB2_UPDT_SEL: 4092 4090 { 4093 4091 m_cost_data_tlb_miss_frz++; 4092 m_cost_data_tlb_update_acc_frz++; 4094 4093 4095 4094 // external cache invalidate request … … 4103 4102 if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp ) 4104 4103 { 4104 size_t way = 0; 4105 size_t set = 0; 4105 4106 paddr_t victim_index = 0; 4106 if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index)) 4107 { 4108 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 4109 } 4110 bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 4111 assert(set_hit && "TLB2_UPDT set hit error"); 4112 r_dcache_fsm = DCACHE_IDLE; 4107 bool cleanup = dcache_tlb.select((dreq.addr >> PAGE_K_NBITS),&victim_index,&way,&set); 4108 if (cleanup) 4109 { 4110 r_dcache_dtlb_cleanup_req = true; 4111 r_dcache_dtlb_cleanup_line = victim_index; 4112 m_cpt_cc_cleanup_data++; 4113 } 4114 r_dcache_way = way; 4115 r_dcache_set = set; 4116 r_dcache_fsm = DCACHE_TLB2_UPDT; 4113 4117 } 4114 4118 else … … 4119 4123 } 4120 4124 break; 4125 } 4126 ////////////////////// 4127 case DCACHE_TLB2_UPDT: 4128 { 4129 m_cost_data_tlb_miss_frz++; 4130 m_cost_data_tlb_update_acc_frz++; 4131 4132 if (r_dcache_dtlb_cleanup_req) r_dcache.setinbit(r_dcache_dtlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 4133 bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 4134 assert(set_hit && "TLB2_UPDT set hit error"); 4135 dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2))); 4136 r_dcache_fsm = DCACHE_IDLE; 4137 break; 4121 4138 } 4122 4139 /////////////////////// … … 4889 4906 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4890 4907 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4891 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT)) && (dreq.valid) )4908 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) ) 4892 4909 { 4893 4910 m_cost_data_tlb_miss_frz++; … … 4933 4950 if ( dcache_hit ) 4934 4951 { 4935 if (((( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )||4952 if (((( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL ) || 4936 4953 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4937 4954 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || … … 4992 5009 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4993 5010 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4994 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT)) && (dreq.valid) )5011 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) ) 4995 5012 { 4996 5013 m_cost_data_tlb_miss_frz++; … … 5023 5040 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 5024 5041 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 5025 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT)) && (dreq.valid) )5042 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) ) 5026 5043 { 5027 5044 m_cost_data_tlb_miss_frz++; … … 5046 5063 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 5047 5064 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 5048 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT)) && (dreq.valid) )5065 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) ) 5049 5066 { 5050 5067 m_cost_data_tlb_miss_frz++; … … 5077 5094 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 5078 5095 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 5079 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT)) && (dreq.valid) )5096 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) ) 5080 5097 { 5081 5098 m_cost_data_tlb_miss_frz++; … … 5088 5105 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 5089 5106 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 5090 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )||5107 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL ) || 5091 5108 ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 5092 5109 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) || … … 6045 6062 6046 6063 } // end switch TGT_FSM 6064 6047 6065 #ifdef SOCLIB_MODULE_DEBUG 6048 6066 std::cout << name()
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