Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 11)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 12)
@@ -1067,4 +1067,5 @@
                 r_itlb_read_dcache_req = true;
 		r_icache_vaddr_req = ireq.addr;
+		r_itlb_k_read_dcache   = true;
                 r_icache_fsm = ICACHE_TLB2_READ;
                 m_cpt_ins_tlb_miss++;
@@ -1667,5 +1668,8 @@
         if ( r_tgt_icache_req )
         {
-            r_tgt_icache_req = false;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
         }
 
@@ -1727,4 +1731,12 @@
     {	
         if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
 
         paddr_t ipaddr = 0;                     
@@ -1755,5 +1767,14 @@
     ////////////////////////
     case ICACHE_CACHE_INVAL_PA:
-    {	
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+	
         paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
 
@@ -1989,5 +2010,5 @@
         else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
                /* (r_icache_fsm_save == ICACHE_UNC_WAIT)||*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
-                (r_icache_tlb_nline.read() == r_dcache_itlb_inval_line.read()))
+                (r_icache_tlb_nline == r_dcache_itlb_inval_line))
         {
             r_icache_inval_tlb_rsp = true;
@@ -2190,6 +2211,7 @@
 
     	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
-	    if ( (r_icache_fsm == ICACHE_TLB2_READ) && itlb_hit_dcache )
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
 	    {	
+		r_itlb_k_read_dcache = false;
 	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
 		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
@@ -2533,6 +2555,5 @@
             else                    // using actual physical address for uncached access
             {
-                dcache_hit_c = ((tlb_dpaddr == (paddr_t)r_dcache_paddr_save) && r_dcache_buf_unc_valid ); 
-                dcache_rdata = r_dcache_miss_buf[0];
+		dcache_hit_c = false;
             }
 
@@ -2618,5 +2639,4 @@
                         if ( dcache_hit_c ) 
                         {
-                            r_dcache_buf_unc_valid = false;
                             r_dcache_fsm = DCACHE_IDLE;
                             drsp.valid = true;
@@ -3987,9 +4007,11 @@
     {
         // external cache invalidate request
-        if ( r_tgt_dcache_req )
-        {
-            r_tgt_dcache_req = false;
-        }   
-
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }  
         size_t way = r_dcache_way;
         size_t set = r_dcache_set;
@@ -4057,4 +4079,13 @@
     case DCACHE_DCACHE_INVAL:
     {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }  
+
         m_cpt_dcache_dir_read += m_dcache_ways;
         vaddr_t invadr = dreq.wdata;
@@ -4105,4 +4136,12 @@
     case DCACHE_DCACHE_INVAL_PA:
     {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }  
         m_cpt_dcache_dir_read += m_dcache_ways;
         paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
@@ -4300,7 +4339,5 @@
             if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
             {
-                r_dcache_fsm = DCACHE_IDLE;
                 r_dcache_inval_tlb_rsp = false;
-		break;
             }
 
@@ -4330,5 +4367,6 @@
 
             }		
-            r_dcache_buf_unc_valid = true;
+	    drsp.valid = true;
+	    drsp.rdata = r_dcache_miss_buf[0];
 	    r_dcache_fsm = DCACHE_IDLE;
 	}	
@@ -4801,5 +4839,5 @@
         if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
              (r_dcache_fsm_save == DCACHE_UNC_WAIT)||(r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
-             (r_dcache_tlb_nline.read() == r_dcache_dtlb_inval_line.read()))
+             (r_dcache_tlb_nline == r_dcache_dtlb_inval_line))
         {
             r_dcache_inval_tlb_rsp = true;
@@ -5644,5 +5682,5 @@
 	}
         else
-	{                                    
+	{           
 	    p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
             p_vci_ini_c.trdid  = 0; // cleanup data