Changeset 120
- Timestamp:
- Dec 16, 2010, 1:11:49 AM (14 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r119 r120 151 151 CMD_DATA_MISS, // 0c 152 152 CMD_DATA_WRITE, // 0d 153 CMD_INS_CLEANUP, // 0e154 CMD_DATA_CLEANUP, // 0f155 153 }; 156 154 … … 170 168 RSP_DATA_UNC, // 0c 171 169 RSP_DATA_WRITE, // 0d 172 RSP_INS_CLEANUP, // 0e 173 RSP_DATA_CLEANUP, // 0f 170 }; 171 enum cleanup_fsm_state_e { 172 CLEANUP_IDLE, // 00 173 CLEANUP_DATA, // 01 174 CLEANUP_INS, // 02 174 175 }; 175 176 … … 384 385 data_t *r_dcache_miss_buf; 385 386 387 sc_signal<int> r_cleanup_fsm; 388 386 389 // VCI_TGT FSM REGISTERS 387 390 data_t *r_tgt_buf; -
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r119 r120 34 34 //#define SOCLIB_MODULE_DEBUG 35 35 //#define EVALUATION_CACHE 36 36 37 #ifdef SOCLIB_MODULE_DEBUG 37 38 namespace { … … 122 123 "CMD_DATA_MISS", 123 124 "CMD_DATA_WRITE", 124 "CMD_INS_CLEANUP",125 "CMD_DATA_CLEANUP",126 125 }; 127 126 const char *rsp_fsm_state_str[] = { … … 140 139 "RSP_DATA_UNC", 141 140 "RSP_DATA_WRITE", 142 "RSP_INS_CLEANUP", 143 "RSP_DATA_CLEANUP", 141 }; 142 const char *cleanup_fsm_state_str[] = { 143 "CLEANUP_IDLE", 144 "CLEANUP_DATA", 145 "CLEANUP_INS", 144 146 }; 145 147 const char *tgt_fsm_state_str[] = { … … 281 283 r_vci_rsp_data_error("r_vci_rsp_data_error"), 282 284 r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"), 285 286 r_cleanup_fsm("r_cleanup_fsm"), 283 287 284 288 r_vci_tgt_fsm("r_vci_tgt_fsm"), … … 424 428 r_inval_itlb_fsm = INVAL_ITLB_IDLE; 425 429 r_inval_dtlb_fsm = INVAL_DTLB_IDLE; 430 r_cleanup_fsm = CLEANUP_IDLE; 426 431 427 432 // write buffer & caches … … 624 629 << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm] 625 630 << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 631 << " cleanup fsm: " << cleanup_fsm_state_str[r_cleanup_fsm] 626 632 << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 627 633 << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl; … … 755 761 r_vci_tgt_fsm = TGT_REQ_ICACHE; 756 762 m_cpt_cc_inval_ins++ ; 757 758 763 } 759 764 } // end if address … … 1260 1265 if ( !r_dcache_rsp_itlb_error ) // vci response ok 1261 1266 { 1262 if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped 1267 if (r_itlb_acc_redo_req) 1268 { 1269 r_itlb_acc_redo_req = false; 1270 r_itlb_read_dcache_req = true; 1271 //r_icache_fsm = ICACHE_IDLE; 1272 } 1273 else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped 1263 1274 { 1264 1275 r_icache_ptba_ok = false; … … 1334 1345 else 1335 1346 { 1347 if ( r_itlb_acc_redo_req ) r_itlb_acc_redo_req = false; 1336 1348 r_icache_inval_tlb_rsp = false; 1337 1349 r_icache_fsm = ICACHE_IDLE; … … 1504 1516 if ( !r_dcache_rsp_itlb_error ) // VCI response ok 1505 1517 { 1506 if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped 1518 if (r_itlb_acc_redo_req) 1519 { 1520 r_itlb_acc_redo_req = false; 1521 r_itlb_read_dcache_req = true; 1522 //r_icache_fsm = ICACHE_IDLE; 1523 } 1524 else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped 1507 1525 { 1508 1526 r_icache_error_type = MMU_READ_PT2_UNMAPPED; … … 1564 1582 else 1565 1583 { 1584 if ( r_itlb_acc_redo_req ) r_itlb_acc_redo_req = false; 1566 1585 r_icache_inval_tlb_rsp = false; 1567 1586 r_icache_fsm = ICACHE_IDLE; … … 4698 4717 4699 4718 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 4700 break; 4701 } 4702 4703 if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation 4719 } 4720 else if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation 4704 4721 { 4705 4722 if ( r_dcache_cleanup_req ) break; … … 4709 4726 r_dcache_fsm = DCACHE_IDLE; 4710 4727 r_dcache_inval_rsp = false; 4711 break; 4728 r_itlb_read_dcache_req = false; 4729 r_itlb_acc_redo_req = true; 4712 4730 } 4713 4714 r_dcache_fsm = DCACHE_ITLB_UPDT; 4731 else 4732 { 4733 r_dcache_fsm = DCACHE_ITLB_UPDT; 4734 } 4715 4735 } 4716 4736 break; … … 4745 4765 r_dcache_fsm = DCACHE_IDLE; 4746 4766 r_dcache_inval_rsp = false; 4767 r_itlb_read_dcache_req = false; 4768 r_itlb_acc_redo_req = true; 4747 4769 break; 4748 4770 } … … 5273 5295 5274 5296 r_vci_cmd_cpt = 0; 5275 5276 if (r_icache_cleanup_req) 5277 { 5278 r_vci_cmd_fsm = CMD_INS_CLEANUP; 5279 m_cpt_icleanup_transaction++; 5280 } 5281 else if (r_dcache_cleanup_req) 5282 { 5283 r_vci_cmd_fsm = CMD_DATA_CLEANUP; 5284 m_cpt_dcleanup_transaction++; 5285 } 5286 else if (r_dcache_itlb_read_req) 5297 if (r_dcache_itlb_read_req) 5287 5298 { 5288 5299 r_vci_cmd_fsm = CMD_ITLB_READ; … … 5367 5378 break; 5368 5379 5369 case CMD_INS_CLEANUP:5370 case CMD_DATA_CLEANUP:5371 if ( p_vci_ini_c.cmdack.read() )5372 {5373 r_vci_cmd_fsm = CMD_IDLE;5374 }5375 break;5376 5377 5380 default: 5378 5381 if ( p_vci_ini_rw.cmdack.read() ) … … 5394 5397 5395 5398 case RSP_IDLE: 5396 assert( !p_vci_ini_rw.rspval.read() && !p_vci_ini_c.rspval.read() &&"Unexpected response" );5399 assert( !p_vci_ini_rw.rspval.read() && "Unexpected response" ); 5397 5400 5398 5401 if (r_vci_cmd_fsm != CMD_IDLE) … … 5400 5403 5401 5404 r_vci_rsp_cpt = 0; 5402 if (r_icache_cleanup_req) // ICACHE cleanup response 5403 { 5404 r_vci_rsp_fsm = RSP_INS_CLEANUP; 5405 } 5406 else if (r_dcache_cleanup_req) // DCACHE cleanup response 5407 { 5408 r_vci_rsp_fsm = RSP_DATA_CLEANUP; 5409 } 5410 else if (r_dcache_itlb_read_req) // ITLB miss response 5405 if (r_dcache_itlb_read_req) // ITLB miss response 5411 5406 { 5412 5407 r_vci_rsp_fsm = RSP_ITLB_READ; … … 5733 5728 } 5734 5729 break; 5735 5736 case RSP_INS_CLEANUP: 5737 case RSP_DATA_CLEANUP: 5738 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 5739 { 5740 m_cost_icleanup_transaction++; 5741 } 5742 else 5743 { 5744 m_cost_dcleanup_transaction++; 5745 } 5746 5730 } // end switch r_vci_rsp_fsm 5731 5732 // add for blocage 5733 switch (r_cleanup_fsm) { 5734 5735 case CLEANUP_IDLE: 5736 { 5737 if ( p_vci_ini_c.cmdack.read() ) 5738 { 5739 if (r_dcache_cleanup_req) 5740 { 5741 r_cleanup_fsm = CLEANUP_DATA; 5742 m_cpt_dcleanup_transaction++; 5743 } 5744 else if (r_icache_cleanup_req) 5745 { 5746 r_cleanup_fsm = CLEANUP_INS; 5747 m_cpt_icleanup_transaction++; 5748 } 5749 } 5750 break; 5751 } 5752 case CLEANUP_DATA: 5753 { 5754 m_cost_dcleanup_transaction++; 5747 5755 if ( ! p_vci_ini_c.rspval.read() ) 5748 5756 break; … … 5750 5758 "illegal VCI response packet for icache cleanup"); 5751 5759 assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) && 5752 "error in response packet for icache cleanup"); 5753 5754 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 5755 { 5756 r_icache_cleanup_req = false; 5757 } 5758 else 5759 { 5760 r_dcache_cleanup_req = false; 5761 } 5762 r_vci_rsp_fsm = RSP_IDLE; 5763 break; 5764 5765 } // end switch r_vci_rsp_fsm 5760 "error in response packet for icache cleanup"); 5761 5762 r_dcache_cleanup_req = false; 5763 r_cleanup_fsm = CLEANUP_IDLE; 5764 break; 5765 } 5766 case CLEANUP_INS: 5767 { 5768 m_cost_icleanup_transaction++; 5769 if ( ! p_vci_ini_c.rspval.read() ) 5770 break; 5771 assert( p_vci_ini_c.reop.read() && 5772 "illegal VCI response packet for icache cleanup"); 5773 assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) && 5774 "error in response packet for icache cleanup"); 5775 5776 r_icache_cleanup_req = false; 5777 r_cleanup_fsm = CLEANUP_IDLE; 5778 break; 5779 } 5780 } // end switch r_cleanup_fsm 5781 5766 5782 } // end transition() 5767 5783 … … 5771 5787 { 5772 5788 // VCI initiator response 5773 5774 5789 p_vci_ini_rw.rspack = true; 5775 p_vci_ini_c.rspack = true;5776 5790 5777 5791 // VCI initiator command 5778 5779 5792 p_vci_ini_rw.pktid = 0; 5780 5793 p_vci_ini_rw.srcid = m_srcid_rw; … … 5784 5797 p_vci_ini_rw.clen = 0; 5785 5798 p_vci_ini_rw.cfixed = false; 5786 5787 p_vci_ini_c.cmdval = false;5788 p_vci_ini_c.address = 0;5789 p_vci_ini_c.wdata = 0;5790 p_vci_ini_c.be = 0;5791 p_vci_ini_c.plen = 0;5792 p_vci_ini_c.cmd = vci_param::CMD_NOP;5793 p_vci_ini_c.trdid = 0;5794 p_vci_ini_c.pktid = 0;5795 p_vci_ini_c.srcid = 0;5796 p_vci_ini_c.cons = false;5797 p_vci_ini_c.wrap = false;5798 p_vci_ini_c.contig = false;5799 p_vci_ini_c.clen = 0;5800 p_vci_ini_c.cfixed = false;5801 p_vci_ini_c.eop = false;5802 5799 5803 5800 switch (r_vci_cmd_fsm) { … … 5972 5969 p_vci_ini_rw.eop = true; 5973 5970 break; 5974 5975 case CMD_INS_CLEANUP: 5976 case CMD_DATA_CLEANUP: 5977 p_vci_ini_rw.cmdval = false; 5978 p_vci_ini_rw.address = 0; 5979 p_vci_ini_rw.wdata = 0; 5980 p_vci_ini_rw.be = 0; 5981 p_vci_ini_rw.trdid = 0; 5982 p_vci_ini_rw.plen = 0; 5983 p_vci_ini_rw.cmd = vci_param::CMD_NOP; 5984 p_vci_ini_rw.eop = false; 5985 5986 p_vci_ini_c.cmdval = true; 5987 if ( r_vci_cmd_fsm == CMD_INS_CLEANUP ) 5971 } // end switch r_vci_cmd_fsm 5972 5973 5974 // VCI initiator command 5975 switch (r_cleanup_fsm) { 5976 5977 case CLEANUP_IDLE: 5978 p_vci_ini_c.cmdval = r_icache_cleanup_req || r_dcache_cleanup_req; 5979 p_vci_ini_c.rspack = false; 5980 if ( r_icache_cleanup_req ) 5988 5981 { 5989 5982 p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2); … … 6006 5999 p_vci_ini_c.clen = 0; 6007 6000 p_vci_ini_c.cfixed = false; 6008 p_vci_ini_c.eop = true; 6009 break; 6010 6011 } // end switch r_vci_cmd_fsm 6001 p_vci_ini_c.eop = true; 6002 break; 6003 6004 case CLEANUP_DATA: 6005 case CLEANUP_INS: 6006 p_vci_ini_c.cmdval = false; 6007 p_vci_ini_c.rspack = true; 6008 p_vci_ini_c.address = 0; 6009 p_vci_ini_c.trdid = 0; 6010 p_vci_ini_c.wdata = 0; 6011 p_vci_ini_c.be = 0; 6012 p_vci_ini_c.plen = 0; 6013 p_vci_ini_c.cmd = vci_param::CMD_NOP; 6014 p_vci_ini_c.pktid = 0; 6015 p_vci_ini_c.srcid = m_srcid_c; 6016 p_vci_ini_c.cons = false; 6017 p_vci_ini_c.wrap = false; 6018 p_vci_ini_c.contig = false; 6019 p_vci_ini_c.clen = 0; 6020 p_vci_ini_c.cfixed = false; 6021 p_vci_ini_c.eop = false; 6022 break; 6023 6024 } // end switch r_vci_cmd_cleanup_fsm 6025 6012 6026 6013 6027 // VCI_TGT … … 6068 6082 << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval 6069 6083 << " p_vci_ini_rw.address: " << p_vci_ini_rw.address 6084 << " p_vci_ini_rw.srcid: " << p_vci_ini_rw.srcid 6070 6085 << " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata 6071 6086 << " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
Note: See TracChangeset
for help on using the changeset viewer.