Changeset 13

Timestamp:

Apr 8, 2010, 2:27:14 PM (15 years ago)

Author:

bouyer

Message:

Fix build with systemcass (add .read() on register access)

File:

• trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp (modified) (2 diffs)

trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp

@@ -2010 +2010 @@
         else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
                /* (r_icache_fsm_save == ICACHE_UNC_WAIT)||*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
-                (r_icache_tlb_nline == r_dcache_itlb_inval_line))
+                (r_icache_tlb_nline.read() == r_dcache_itlb_inval_line.read()))
         {
             r_icache_inval_tlb_rsp = true;
@@ -4839 +4839 @@
         if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
              (r_dcache_fsm_save == DCACHE_UNC_WAIT)||(r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
-             (r_dcache_tlb_nline == r_dcache_dtlb_inval_line))
+             (r_dcache_tlb_nline.read() == r_dcache_dtlb_inval_line.read()))
         {
             r_dcache_inval_tlb_rsp = true;