Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
===================================================================
--- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 118)
+++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 134)
@@ -32,6 +32,7 @@
 #include <inttypes.h>
 #include <systemc>
+#include <queue>
 #include "caba_base_module.h"
-#include "write_buffer.h"
+#include "multi_write_buffer.h"
 #include "generic_cache.h"
 #include "vci_initiator.h"
@@ -40,4 +41,80 @@
 #include "static_assert.h"
 
+/*
+ * CC_XCACHE_WRAPPER_SELECT_VICTIM :
+ *   The selection and the update of cache (after a read miss)
+ *   are separated in two step
+ *   Also, the cleanup can be send in parallel at the read miss.
+ *
+ * CC_XCACHE_WRAPPER_FIFO_RSP
+ *   Two simple fifo (each 2x32 depth) receive the cache line from
+ *   RAM. Instead of two buffers (m_icache_words and m_dcache_words)
+ *   
+ * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
+ *   Update cache in "2*cache_words" cycles (read+mask, write)
+ *   
+ * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
+ *   Update cache with only modified data (be != 0)
+ *   
+ * CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
+ *   Write buffer scheme for update step :
+ *     1    - multi_scan
+ *     2    - round_robin_scan
+ *     3    - one_scan
+ *     else - default scheme
+ *
+ * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
+ *   Write buffer access is conditionnal with dcache_miss_req and icache_miss_req
+ *     1    - two access authorized
+ *     2    - one access with static priority (dcache prior)
+ *     3    - one access with static priority (icache prior)
+ *     4    - one access with round robin priority
+ * 
+ * CC_XCACHE_WRAPPER_STOP_SIMULATION :
+ *   stop simulation if processor is stall after a long time
+ *   (configurable with "stop_simulation" function)
+ *
+ * CC_XCACHE_WRAPPER_DEBUG :
+ *   Add log to help the debugging
+ *
+ * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN :
+ *   Number of cycle before to prinf debug message
+ *
+ * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
+ *   Print transaction between the cpu and the cache
+ */
+
+// implementation
+#ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM
+#define CC_XCACHE_WRAPPER_SELECT_VICTIM             0
+#endif
+#ifndef CC_XCACHE_WRAPPER_FIFO_RSP
+#define CC_XCACHE_WRAPPER_FIFO_RSP                  0
+#endif
+#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
+#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE     1
+#endif
+#ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
+#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1
+#endif
+#ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
+#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME        0
+#endif
+#ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
+#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY          2
+#endif  
+// debugging
+#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
+#define CC_XCACHE_WRAPPER_STOP_SIMULATION           1
+#endif
+#ifndef CC_XCACHE_WRAPPER_DEBUG
+#define CC_XCACHE_WRAPPER_DEBUG                     0
+#endif
+#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
+#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN           200000
+#endif
+#ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
+#define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION  0
+#endif
 
 namespace soclib {
@@ -58,8 +135,11 @@
     typedef uint32_t    	be_t;
     typedef typename vci_param::fast_addr_t vci_addr_t;
+
     enum dcache_fsm_state_e {
         DCACHE_IDLE,
         DCACHE_WRITE_UPDT,
-        DCACHE_WRITE_REQ,
+#if CC_XCACHE_WRAPPER_SELECT_VICTIM
+        DCACHE_MISS_VICTIM,
+#endif
         DCACHE_MISS_WAIT,
         DCACHE_MISS_UPDT,
@@ -67,4 +147,5 @@
         DCACHE_SC_WAIT,
         DCACHE_INVAL,
+        DCACHE_SYNC,
         DCACHE_ERROR,
         DCACHE_CC_CHECK,
@@ -76,4 +157,7 @@
     enum icache_fsm_state_e {
         ICACHE_IDLE,
+#if CC_XCACHE_WRAPPER_SELECT_VICTIM
+        ICACHE_MISS_VICTIM,
+#endif
         ICACHE_MISS_WAIT,
         ICACHE_MISS_UPDT,
@@ -94,6 +178,4 @@
         CMD_DATA_WRITE,
         CMD_DATA_SC,
-        CMD_INS_CLEANUP,
-        CMD_DATA_CLEANUP,
     };
 
@@ -106,6 +188,4 @@
         RSP_DATA_WRITE,
         RSP_DATA_SC,
-        RSP_INS_CLEANUP,
-        RSP_DATA_CLEANUP,
     };
 
@@ -122,4 +202,28 @@
     };
 
+    enum cleanup_fsm_state_e {
+        CLEANUP_IDLE,
+        CLEANUP_DCACHE,
+        CLEANUP_ICACHE,
+    };
+
+    enum transaction_type_c_e {
+        // convention with memcache
+        TYPE_DATA_CLEANUP = 0x0,
+        TYPE_INS_CLEANUP  = 0x1
+    };
+
+    enum transaction_type_rw_e {
+        // convention with memcache
+        // b0 : 1 if cached
+        // b1 : 1 if instruction
+        // b2 : 1 if sc
+        TYPE_DATA_UNC     = 0x0,
+        TYPE_DATA_MISS    = 0x1,
+        TYPE_INS_UNC      = 0x2,
+        TYPE_INS_MISS     = 0x3,
+        TYPE_DATA_SC      = 0x4, // sc is data and no cached
+    };
+
 public:
 
@@ -143,8 +247,17 @@
     const size_t        m_dcache_ways;
     const size_t        m_dcache_words;
+    const uint32_t      m_dcache_words_shift;
     const size_t        m_dcache_yzmask;
     const size_t        m_icache_ways;
     const size_t        m_icache_words;
+    const uint32_t      m_icache_words_shift;
     const size_t        m_icache_yzmask;
+    const size_t        m_cache_words; // max between m_dcache_words and m_icache_words
+
+#if CC_XCACHE_WRAPPER_STOP_SIMULATION
+    bool                m_stop_simulation;
+    uint32_t            m_stop_simulation_nb_frz_cycles_max;
+    uint32_t            m_stop_simulation_nb_frz_cycles;
+#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
 
     // REGISTERS
@@ -154,7 +267,4 @@
     sc_signal<data_t>       r_dcache_wdata_save;
     sc_signal<data_t>       r_dcache_rdata_save;
-    sc_signal<data_64>      r_dcache_ll_data;
-    sc_signal<addr_40>      r_dcache_ll_addr;
-    sc_signal<bool>         r_dcache_ll_valid;
     sc_signal<int>          r_dcache_type_save;
     sc_signal<be_t>         r_dcache_be_save;
@@ -163,8 +273,14 @@
     sc_signal<addr_40>      r_dcache_cleanup_line;
     sc_signal<bool>         r_dcache_miss_req;
+    sc_signal<size_t>       r_dcache_miss_way;
+    sc_signal<size_t>       r_dcache_miss_set;
     sc_signal<bool>         r_dcache_unc_req;
     sc_signal<bool>         r_dcache_sc_req;
-    sc_signal<bool>         r_dcache_write_req;
     sc_signal<bool>         r_dcache_inval_rsp;
+    sc_signal<size_t>       r_dcache_update_addr;
+    sc_signal<data_64>      r_dcache_ll_data;
+    sc_signal<addr_40>      r_dcache_ll_addr;
+    sc_signal<bool>         r_dcache_ll_valid;
+    sc_signal<bool>         r_dcache_previous_unc;
 
     sc_signal<int>          r_icache_fsm;
@@ -172,8 +288,11 @@
     sc_signal<addr_40>      r_icache_addr_save;
     sc_signal<bool>         r_icache_miss_req;
+    sc_signal<size_t>       r_icache_miss_way;
+    sc_signal<size_t>       r_icache_miss_set;
     sc_signal<bool>         r_icache_unc_req;
     sc_signal<bool>         r_icache_cleanup_req;
     sc_signal<addr_40>      r_icache_cleanup_line;
     sc_signal<bool>         r_icache_inval_rsp;
+    sc_signal<size_t>       r_icache_update_addr;
 
     sc_signal<int>          r_vci_cmd_fsm;
@@ -181,4 +300,5 @@
     sc_signal<size_t>       r_vci_cmd_max;       
     sc_signal<size_t>       r_vci_cmd_cpt;       
+    sc_signal<bool>         r_vci_cmd_dcache_prior;
       
     sc_signal<int>          r_vci_rsp_fsm;
@@ -186,11 +306,22 @@
     sc_signal<bool>         r_vci_rsp_data_error;    
     sc_signal<size_t>       r_vci_rsp_cpt;  
-
-    data_t                  *r_icache_miss_buf;    
-    data_t                  *r_dcache_miss_buf;    
+    sc_signal<bool>         r_vci_rsp_ack;
+
+#if CC_XCACHE_WRAPPER_FIFO_RSP
+    std::queue<data_t>      r_icache_miss_buf;
+    std::queue<data_t>      r_dcache_miss_buf;
+#else
+    bool                   *r_icache_miss_val;    //[m_icache_words]
+    data_t                 *r_icache_miss_buf;    //[m_icache_words]
+    bool                   *r_dcache_miss_val;    //[m_dcache_words]
+    data_t                 *r_dcache_miss_buf;    //[m_dcache_words]
+#endif
     sc_signal<bool>         r_icache_buf_unc_valid;
 
-    data_t                  *r_tgt_buf;
-    be_t                    *r_tgt_be;
+    data_t                 *r_tgt_buf;            //[m_cache_words]
+    be_t                   *r_tgt_be;             //[m_cache_words]
+#if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
+    sc_signal<uint32_t>     r_cache_word;
+#endif
 
     sc_signal<int>          r_vci_tgt_fsm;
@@ -199,9 +330,9 @@
     sc_signal<bool>         r_tgt_update;
     sc_signal<bool>         r_tgt_update_data;
-    sc_signal<bool>         r_tgt_brdcast;
+  //sc_signal<bool>         r_tgt_brdcast;
     sc_signal<size_t>       r_tgt_srcid;
     sc_signal<size_t>       r_tgt_pktid;
     sc_signal<size_t>       r_tgt_trdid;
-    sc_signal<size_t>       r_tgt_plen;
+  //sc_signal<size_t>       r_tgt_plen;
     sc_signal<bool>         r_tgt_icache_req;
     sc_signal<bool>         r_tgt_dcache_req;
@@ -209,47 +340,59 @@
     sc_signal<bool>         r_tgt_dcache_rsp;
 
-    WriteBuffer<addr_40>        r_wbuf;
+    sc_signal<int>          r_cleanup_fsm;		// controls initiator port of the coherence network
+
+    MultiWriteBuffer<addr_40>   r_wbuf;
     GenericCache<vci_addr_t>    r_icache;
     GenericCache<vci_addr_t>    r_dcache;
 
+#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
+    std::ofstream               log_dcache_transaction_file;
+#endif
+
     // Activity counters
-    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
-    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
-    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
-    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
-
-    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
-    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
-    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
-    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
-
-    uint32_t m_cpt_cc_update;               // number of coherence update packets 
-    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
-
-    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	    // total number of cycles 
-
-    uint32_t m_cpt_read;                    // total number of read instructions
-    uint32_t m_cpt_write;                   // total number of write instructions
-    uint32_t m_cpt_data_miss;               // number of read miss
-    uint32_t m_cpt_ins_miss;                // number of instruction miss
-    uint32_t m_cpt_unc_read;                // number of read uncached
-    uint32_t m_cpt_write_cached;            // number of cached write
-
-    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
-    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
-    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
-    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
-
-    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
-    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
-    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
-    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
-
-    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
-    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
-    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
-    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
-    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+    uint32_t m_cpt_dcache_data_read;             // * DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;            // * DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;              // * DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;             // * DCACHE DIR WRITE
+                                                 
+    uint32_t m_cpt_icache_data_read;             // * ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;            // * ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;              // * ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;             // * ICACHE DIR WRITE
+
+    uint32_t m_cpt_cc_update_icache;             // number of coherence update packets (for icache)
+    uint32_t m_cpt_cc_update_dcache;             // number of coherence update packets (for dcache)
+    uint32_t m_cpt_cc_inval_broadcast;           // number of coherence inval packets
+    uint32_t m_cpt_cc_inval_icache;              // number of coherence inval packets
+    uint32_t m_cpt_cc_inval_dcache;              // number of coherence inval packets
+    uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
+    uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
+
+    uint32_t m_cpt_frz_cycles;	                 // * number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	             // total number of cycles 
+
+    uint32_t m_cpt_data_read;                    //   number of data read
+    uint32_t m_cpt_data_read_miss;               //   number of data read miss
+    uint32_t m_cpt_data_read_uncached;           //   number of data read uncached
+    uint32_t m_cpt_data_write;                   //   number of data write
+    uint32_t m_cpt_data_write_miss;              //   number of data write miss
+    uint32_t m_cpt_data_write_uncached;          //   number of data write uncached
+    uint32_t m_cpt_ins_miss;                     // * number of instruction miss
+
+    uint32_t m_cost_write_frz;                   // * number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;               // * number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;                // * number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;                // * number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;            // * number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;            // * number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;              // * number of VCI uncached read transactions
+    uint32_t m_cpt_data_write_transaction;       // * number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;           // * cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;           // * cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;             // * cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;           // * cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;         // * cumulated length for VCI WRITE transactions
 
 protected:
@@ -271,5 +414,9 @@
                        size_t dcache_ways,
                        size_t dcache_sets,
-                       size_t dcache_words );
+                       size_t dcache_words,
+                       size_t wbuf_nwords,
+                       size_t wbuf_nlines,
+                       size_t wbuf_timeout
+                         );
 
     ~VciCcXCacheWrapperV4();
@@ -278,4 +425,8 @@
     void print_cpi();
     void print_stats();
+
+// #if CC_XCACHE_WRAPPER_STOP_SIMULATION
+    void stop_simulation (uint32_t);
+// #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
 
 private:
@@ -300,5 +451,2 @@
 
 // vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
-
-
-
