Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 137) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 138) @@ -189,4 +189,6 @@ XRAM_RSP_HEAP_ERASE, XRAM_RSP_HEAP_LAST, + XRAM_RSP_ERROR_ERASE, + XRAM_RSP_ERROR_RSP, }; @@ -393,5 +395,4 @@ sc_signal r_tgt_cmd_fsm; - sc_signal r_index; size_t nseg; size_t ncseg; @@ -634,4 +635,5 @@ sc_signal r_xram_rsp_to_tgt_rsp_word; // first word index sc_signal r_xram_rsp_to_tgt_rsp_length;// length of the response + sc_signal r_xram_rsp_to_tgt_rsp_rerror;// send error to requester // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) Index: trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h (revision 137) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h (revision 138) @@ -31,4 +31,5 @@ std::vector wdata; // write buffer (one cache line) std::vector wdata_be; // be for each data in the write buffer + bool rerror; // error returned by xram ///////////////////////////////////////////////////////////////////// @@ -72,5 +73,6 @@ word_index = source.word_index; wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end()); - wdata.assign(source.wdata.begin(),source.wdata.end()); + wdata.assign(source.wdata.begin(),source.wdata.end()); + rerror = source.rerror; } @@ -95,4 +97,5 @@ } std::cout << std::endl; + std::cout << "rerror = " << rerror << std::endl; } @@ -106,4 +109,5 @@ wdata.clear(); valid=false; + rerror=false; } @@ -120,4 +124,5 @@ wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end()); wdata.assign(source.wdata.begin(),source.wdata.end()); + rerror = source.rerror; } @@ -363,6 +368,7 @@ ///////////////////////////////////////////////////////////////////// void write_rsp(const size_t index, - const size_t word, - const data_t data) + const size_t word, + const data_t data, + const bool rerror) { assert( (index < size_tab) @@ -377,4 +383,5 @@ data_t mask = be_to_mask(tab[index].wdata_be[word]); tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask); + tab[index].rerror |= rerror; } Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 137) +++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 138) @@ -143,4 +143,6 @@ "XRAM_RSP_HEAP_ERASE ", "XRAM_RSP_HEAP_LAST ", + "XRAM_RSP_ERROR_ERASE", + "XRAM_RSP_ERROR_RSP ", }; const char *ixr_cmd_fsm_str[] = { @@ -651,25 +653,5 @@ PRINTF(" * Request from %d at address %llx\n",(uint32_t)p_vci_tgt.srcid.read(),(uint64_t)p_vci_tgt.address.read()); - assert( (p_vci_tgt.srcid.read() < m_initiators) && - "VCI_MEM_CACHE error in direct request : received SRCID is larger than the number of initiators"); - - bool reached = false; - for ( size_t index = 0 ; index < nseg && !reached ; index++) - { -// if ( m_seg[index]->contains((addr_t)(p_vci_tgt.address.read())) ) { - if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) { - reached = true; - r_index = index; - } - } - - if ( !reached ) - { - std::cout << "VCI_MEM_CACHE Out of segment access in " << name() << std::endl; - std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl; - std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl; - exit(0); - } - else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) + if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) { r_tgt_cmd_fsm = TGT_CMD_READ; @@ -1867,9 +1849,11 @@ case IXR_RSP_IDLE: // test if it's a read or a write transaction { - if ( p_vci_ixr.rspval ) { + if ( p_vci_ixr.rspval.read() ) { r_ixr_rsp_cpt = 0; r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); - if ( p_vci_ixr.reop ) r_ixr_rsp_fsm = IXR_RSP_ACK; - else r_ixr_rsp_fsm = IXR_RSP_TRT_READ; + if ( p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read()&0x1)) + r_ixr_rsp_fsm = IXR_RSP_ACK; + else + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; } break; @@ -1877,6 +1861,9 @@ //////////////////////// case IXR_RSP_ACK: // Acknowledge the vci response - r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; - break; + { + if(p_vci_ixr.rspval.read()) + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + break; + } //////////////////////// case IXR_RSP_TRT_ERASE: // erase the entry in the TRT @@ -1903,7 +1890,8 @@ data_t data = p_vci_ixr.rdata.read(); size_t index = r_ixr_rsp_trt_index.read(); - assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) + assert( ((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || + p_vci_ixr.rerror.read()) && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); - m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data); + m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data, p_vci_ixr.rerror.read()&0x1); r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1; if ( eop ) { @@ -1972,5 +1960,5 @@ { if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) { - r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; + r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; #ifdef TDEBUG if(m_cpt_cycles > DEBUG_START_CYCLE){ @@ -2010,5 +1998,8 @@ r_xram_rsp_victim_dirty = victim.dirty; - r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; + if(!trt_entry.rerror) + r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; + else + r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; #ifdef TDEBUG if(m_cpt_cycles > DEBUG_START_CYCLE){ @@ -2212,4 +2203,5 @@ r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_rerror = false; r_xram_rsp_to_tgt_rsp_req = true; @@ -2324,4 +2316,48 @@ r_xram_rsp_fsm = XRAM_RSP_IDLE; + break; + } + /////////////////////// + case XRAM_RSP_ERROR_ERASE: // erase xram transaction + { + +#ifdef TDEBUG +if(m_cpt_cycles > DEBUG_START_CYCLE){ + std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_ERROR_ERASE transaction table : " << std::endl; + for(size_t i = 0 ; i < m_transaction_tab.size() ; i++) + m_transaction_tab.print(i); +} +#endif + + m_transaction_tab.erase(r_xram_rsp_trt_index.read()); + + // Next state + if ( r_xram_rsp_trt_buf.proc_read ) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + break; + } + ////////////////////// + case XRAM_RSP_ERROR_RSP: // send a request to TGT_RSP FSM in case of read + { + if ( !r_xram_rsp_to_tgt_rsp_req.read() ) { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for (size_t i=0; i < m_words; i++) { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_rerror = true; + r_xram_rsp_to_tgt_rsp_req = true; + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#ifdef DDEBUG +if(m_cpt_cycles > DEBUG_START_CYCLE){ + std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl; +} +#endif + } break; } @@ -3613,5 +3649,6 @@ { if ( p_vci_tgt.rspack ) { - if ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) { + if ( (r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) + || r_xram_rsp_to_tgt_rsp_rerror.read() ) { r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; r_xram_rsp_to_tgt_rsp_req = false; @@ -4301,6 +4338,7 @@ p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)); + p_vci_tgt.rerror = r_xram_rsp_to_tgt_rsp_rerror.read(); + p_vci_tgt.reop = (( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) + || r_xram_rsp_to_tgt_rsp_rerror.read()); break; case TGT_RSP_INIT: