Changeset 139 for trunk/modules/vci_cc_vcache_wrapper2_v1/caba
- Timestamp:
- Mar 2, 2011, 11:09:56 AM (14 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r130 r139 169 169 RSP_DATA_WRITE, // 0d 170 170 }; 171 enum cleanup_fsm_state_e { 172 CLEANUP_IDLE, // 00 173 CLEANUP_DATA, // 01 174 CLEANUP_INS, // 02 171 enum cleanup_cmd_fsm_state_e { 172 CLEANUP_CMD_IDLE, // 00 173 CLEANUP_CMD_DATA, // 01 174 CLEANUP_CMD_INS, // 02 175 }; 176 177 enum cleanup_rsp_fsm_state_e { 178 CLEANUP_RSP_IDLE, // 00 179 CLEANUP_RSP_DATA, // 01 180 CLEANUP_RSP_INS, // 02 175 181 }; 176 182 … … 385 391 data_t *r_dcache_miss_buf; 386 392 387 sc_signal<int> r_cleanup_fsm; 393 sc_signal<int> r_cleanup_cmd_fsm; 394 sc_signal<int> r_cleanup_rsp_fsm; 388 395 389 396 // VCI_TGT FSM REGISTERS … … 523 530 uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets 524 531 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets 532 533 uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets 534 uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets 535 uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets 536 uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets 537 525 538 uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets 526 539 uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets -
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r130 r139 140 140 "RSP_DATA_WRITE", 141 141 }; 142 const char *cleanup_fsm_state_str[] = { 143 "CLEANUP_IDLE", 144 "CLEANUP_DATA", 145 "CLEANUP_INS", 142 const char *cleanup_cmd_fsm_state_str[] = { 143 "CLEANUP_CMD_IDLE", 144 "CLEANUP_CMD_DATA", 145 "CLEANUP_CMD_INS", 146 }; 147 const char *cleanup_rsp_fsm_state_str[] = { 148 "CLEANUP_RSP_IDLE", 149 "CLEANUP_RSP_DATA", 150 "CLEANUP_RSP_INS", 146 151 }; 147 152 const char *tgt_fsm_state_str[] = { … … 284 289 r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"), 285 290 286 r_cleanup_fsm("r_cleanup_fsm"), 291 r_cleanup_cmd_fsm("r_cleanup_cmd_fsm"), 292 r_cleanup_rsp_fsm("r_cleanup_rsp_fsm"), 287 293 288 294 r_vci_tgt_fsm("r_vci_tgt_fsm"), … … 389 395 << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm] 390 396 << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 391 << " cleanup fsm: " << cleanup_fsm_state_str[r_cleanup_fsm] 397 << " cleanup cmd fsm: " << cleanup_cmd_fsm_state_str[r_cleanup_cmd_fsm] 398 << " cleanup rsp fsm: " << cleanup_rsp_fsm_state_str[r_cleanup_rsp_fsm] 392 399 << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 393 400 << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl; … … 428 435 << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 429 436 << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 430 << "- DCACHE FROZEN BY TLB OP= " << (float)(m_cost_ins_tlb_occup_cache_frz+m_cost_data_tlb_occup_cache_frz)/m_cpt_dcache_frz_cycles << std::endl437 << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 431 438 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 432 439 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl … … 434 441 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl 435 442 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl 443 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 444 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl 445 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl 446 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl 436 447 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 437 448 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl … … 458 469 m_cpt_icache_dir_write = 0; 459 470 460 471 m_cpt_frz_cycles = 0; 461 472 m_cpt_dcache_frz_cycles = 0; 462 473 m_cpt_total_cycles = 0; 463 474 464 475 m_cpt_read = 0; … … 527 538 m_cost_dtlb_sc_dirty_transaction = 0; 528 539 529 m_cpt_cc_broadcast = 0;530 540 m_cpt_cc_update_data = 0; 531 m_cpt_cc_inval_data = 0; 532 m_cpt_cc_inval_ins = 0; 541 m_cpt_cc_inval_ins = 0; 542 m_cpt_cc_inval_data = 0; 543 m_cpt_cc_broadcast = 0; 544 545 m_cost_updt_data_frz = 0; 546 m_cost_inval_ins_frz = 0; 547 m_cost_inval_data_frz = 0; 548 m_cost_broadcast_frz = 0; 549 533 550 m_cpt_cc_cleanup_data = 0; 534 m_cpt_cc_cleanup_ins = 0;551 m_cpt_cc_cleanup_ins = 0; 535 552 } 536 553 … … 550 567 r_inval_itlb_fsm = INVAL_ITLB_IDLE; 551 568 r_inval_dtlb_fsm = INVAL_DTLB_IDLE; 552 r_cleanup_fsm = CLEANUP_IDLE; 569 r_cleanup_cmd_fsm = CLEANUP_CMD_IDLE; 570 r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE; 553 571 554 572 // write buffer & caches … … 723 741 m_cost_ins_tlb_occup_cache_frz = 0; 724 742 m_cost_data_tlb_occup_cache_frz = 0; 743 744 m_cpt_ins_tlb_inval = 0; 745 m_cpt_data_tlb_inval = 0; 746 m_cost_ins_tlb_inval_frz = 0; 747 m_cost_data_tlb_inval_frz = 0; 748 749 m_cpt_cc_update_data = 0; 750 m_cpt_cc_inval_ins = 0; 751 m_cpt_cc_inval_data = 0; 752 m_cpt_cc_broadcast = 0; 753 754 m_cost_updt_data_frz = 0; 755 m_cost_inval_ins_frz = 0; 756 m_cost_inval_data_frz = 0; 757 m_cost_broadcast_frz = 0; 758 759 m_cpt_cc_cleanup_data = 0; 760 m_cpt_cc_cleanup_ins = 0; 725 761 726 762 m_cpt_itlbmiss_transaction = 0; … … 751 787 << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm] 752 788 << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 753 << " cleanup fsm: " << cleanup_fsm_state_str[r_cleanup_fsm] 789 << " cleanup cmd fsm: " << cleanup_cmd_fsm_state_str[r_cleanup_cmd_fsm] 790 << " cleanup rsp fsm: " << cleanup_rsp_fsm_state_str[r_cleanup_rsp_fsm] 754 791 << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 755 792 << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl; … … 843 880 r_vci_tgt_fsm = TGT_REQ_BROADCAST; 844 881 m_cpt_cc_broadcast++; 882 m_cost_broadcast_frz++; 845 883 } 846 884 else // multi-update or multi-invalidate for data type … … 859 897 r_vci_tgt_fsm = TGT_REQ_DCACHE; 860 898 m_cpt_cc_inval_data++ ; 899 m_cost_inval_data_frz++; 861 900 } 862 901 else if (cell == 4) // update … … 871 910 r_vci_tgt_fsm = TGT_UPDT_WORD; 872 911 m_cpt_cc_update_data++ ; 912 m_cost_updt_data_frz++; 873 913 } 874 914 else if (cell == 8) … … 883 923 r_vci_tgt_fsm = TGT_REQ_ICACHE; 884 924 m_cpt_cc_inval_ins++ ; 925 m_cost_inval_ins_frz++; 885 926 } 886 927 } // end if address … … 891 932 case TGT_UPDT_WORD: 892 933 { 934 m_cost_updt_data_frz++; 935 893 936 if (p_vci_tgt.cmdval.read()) 894 937 { … … 908 951 case TGT_UPDT_DATA: 909 952 { 953 m_cost_updt_data_frz++; 954 910 955 if (p_vci_tgt.cmdval.read()) 911 956 { … … 927 972 case TGT_REQ_BROADCAST: 928 973 { 974 m_cost_broadcast_frz++; 975 929 976 if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 930 977 { … … 938 985 case TGT_REQ_ICACHE: 939 986 { 987 m_cost_inval_ins_frz++; 988 940 989 if ( !r_tgt_icache_req.read() ) 941 990 { … … 948 997 case TGT_REQ_DCACHE: 949 998 { 999 if (r_tgt_update) 1000 m_cost_updt_data_frz++; 1001 else 1002 m_cost_inval_data_frz++; 1003 950 1004 if ( !r_tgt_dcache_req.read() ) 951 1005 { … … 958 1012 case TGT_RSP_BROADCAST: 959 1013 { 1014 m_cost_broadcast_frz++; 1015 960 1016 // no response 961 1017 if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) … … 986 1042 case TGT_RSP_ICACHE: 987 1043 { 1044 m_cost_inval_ins_frz++; 1045 988 1046 if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 989 1047 { … … 996 1054 case TGT_RSP_DCACHE: 997 1055 { 1056 if (r_tgt_update) 1057 m_cost_updt_data_frz++; 1058 else 1059 m_cost_inval_data_frz++; 1060 998 1061 if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() ) 999 1062 { … … 1241 1304 r_icache_vaddr_req = ireq.addr; 1242 1305 r_icache_fsm = ICACHE_BIS; 1243 m_cost_ins_miss_frz++;1306 //m_cost_ins_miss_frz++; 1244 1307 } 1245 1308 else // cached or uncached access with a correct speculative physical address … … 1281 1344 case ICACHE_BIS: 1282 1345 { 1283 //if ( ireq.valid ) m_cost_ins_miss_frz++;1284 1285 1346 // external cache invalidate request 1286 1347 if ( r_tgt_icache_req ) … … 1585 1646 r_dcache_itlb_cleanup_req = true; 1586 1647 r_dcache_itlb_cleanup_line = victim_index; 1587 m_cpt_cc_cleanup_ins++;1648 //m_cpt_cc_cleanup_ins++; 1588 1649 } 1589 1650 r_icache_fsm = ICACHE_TLB1_UPDT; … … 1642 1703 r_itlb_acc_redo_req = false; 1643 1704 r_itlb_read_dcache_req = true; 1644 //r_icache_fsm = ICACHE_IDLE;1645 1705 } 1646 1706 else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped … … 1822 1882 r_dcache_itlb_cleanup_req = true; 1823 1883 r_dcache_itlb_cleanup_line = victim_index; 1824 m_cpt_cc_cleanup_ins++;1884 //m_cpt_cc_cleanup_ins++; 1825 1885 } 1826 1886 r_icache_fsm = ICACHE_TLB2_UPDT; … … 1941 2001 if ( !r_dcache_itlb_cleanup_req ) 1942 2002 { 1943 r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index); 2003 bool dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index); 2004 r_dcache_itlb_cleanup_req = dcache_itlb_cleanup_req; 1944 2005 r_dcache_itlb_cleanup_line = victim_index; 1945 m_cpt_cc_cleanup_ins++;2006 //if (dcache_itlb_cleanup_req) m_cpt_cc_cleanup_ins++; 1946 2007 r_dcache_xtn_req = false; 1947 2008 r_itlb_translation_valid = false; … … 1979 2040 { 1980 2041 // invalidate and cleanup if necessary 1981 r_icache_cleanup_req = r_icache.inval(ipaddr); 2042 bool icache_cleanup_req = r_icache.inval(ipaddr); 2043 r_icache_cleanup_req = icache_cleanup_req; 1982 2044 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1983 m_cpt_cc_cleanup_ins++;2045 if (icache_cleanup_req) m_cpt_cc_cleanup_ins++; 1984 2046 } 1985 2047 r_dcache_xtn_req = false; … … 2004 2066 { 2005 2067 // invalidate and cleanup if necessary 2006 r_icache_cleanup_req = r_icache.inval(ipaddr); 2068 bool icache_cleanup_req = r_icache.inval(ipaddr); 2069 r_icache_cleanup_req = icache_cleanup_req; 2007 2070 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 2008 m_cpt_cc_cleanup_ins++;2071 if (icache_cleanup_req) m_cpt_cc_cleanup_ins++; 2009 2072 r_dcache_xtn_req = false; 2010 2073 r_icache_fsm = ICACHE_IDLE; … … 2102 2165 2103 2166 if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false; 2104 //if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;2105 2167 break; 2106 2168 } … … 2170 2232 m_cpt_icache_data_write++; 2171 2233 2172 r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); 2234 bool icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); 2235 r_icache_cleanup_req = icache_cleanup_req; 2173 2236 r_icache_cleanup_line = victim_index; 2174 m_cpt_cc_cleanup_ins++;2237 if (icache_cleanup_req) m_cpt_cc_cleanup_ins++; 2175 2238 r_icache_fsm = ICACHE_IDLE; 2176 2239 } … … 2258 2321 } 2259 2322 } // end switch r_icache_fsm 2323 2260 2324 #ifdef SOCLIB_MODULE_DEBUG 2261 2325 std::cout << name() << " Instruction Response: " << irsp << std::endl; 2262 2326 #endif 2327 2263 2328 //////////////////////////////////////////////////////////////////////////////////// 2264 2329 // INVAL ITLB CHECK FSM … … 3039 3104 case DCACHE_BIS: 3040 3105 { 3041 //if ( dreq.valid ) m_cost_data_miss_frz++;3042 3043 3106 // external cache invalidate request 3044 3107 if ( r_tgt_dcache_req ) … … 3295 3358 { 3296 3359 m_cost_data_tlb_miss_frz++; 3360 if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++; 3297 3361 3298 3362 // external cache invalidate request … … 3349 3413 r_dcache_tlb_ll_dirty_req = true; 3350 3414 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3351 m_cpt_data_tlb_update_dirty++;3352 m_cost_data_tlb_update_dirty_frz++;3353 3415 } 3354 3416 else … … 3546 3608 { 3547 3609 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3610 if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++; 3548 3611 3549 3612 // external cache invalidate request … … 3605 3668 { 3606 3669 m_cost_data_tlb_miss_frz++; 3670 if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++; 3607 3671 3608 3672 // external cache invalidate request … … 3700 3764 r_dcache_tlb_ll_dirty_req = true; 3701 3765 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3702 m_cpt_data_tlb_update_dirty++;3703 m_cost_data_tlb_update_dirty_frz++;3704 3766 } 3705 3767 else … … 3776 3838 r_dcache_dtlb_cleanup_req = true; 3777 3839 r_dcache_dtlb_cleanup_line = victim_index; 3778 m_cpt_cc_cleanup_data++;3840 //m_cpt_cc_cleanup_data++; 3779 3841 } 3780 3842 r_dcache_way = way; … … 4121 4183 data_t rsp_dtlb_miss; 4122 4184 data_t tlb_data_ppn; 4123 //bool write_hit = false;4124 4185 paddr_t victim_index = 0; 4125 4186 size_t way = 0; … … 4251 4312 r_dcache_dtlb_cleanup_req = true; 4252 4313 r_dcache_dtlb_cleanup_line = victim_index; 4253 m_cpt_cc_cleanup_data++;4314 //m_cpt_cc_cleanup_data++; 4254 4315 } 4255 4316 r_dcache_way = way; … … 4436 4497 if ( dcache_hit_t ) 4437 4498 { 4438 r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); 4499 bool dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); 4500 r_dcache_cleanup_req = dcache_cleanup_req; 4439 4501 r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); 4440 m_cpt_cc_cleanup_data++;4502 if (dcache_cleanup_req) m_cpt_cc_cleanup_data++; 4441 4503 4442 4504 if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) … … 4478 4540 if ( !r_dcache_cleanup_req ) 4479 4541 { 4480 r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); 4542 bool dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set); 4543 r_dcache_cleanup_req = dcache_cleanup_req; 4481 4544 r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); 4482 m_cpt_cc_cleanup_data++;4545 if (dcache_cleanup_req) m_cpt_cc_cleanup_data++; 4483 4546 4484 4547 if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) … … 5055 5118 } 5056 5119 5120 if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) 5121 { 5122 m_cost_ins_tlb_occup_cache_frz++; 5123 } 5124 5057 5125 // DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT 5058 5126 // DCACHE_TLB2_LL_WAIT DCACHE_TLB2_SC_WAIT DCACHE_SC_DIRTY_WAIT … … 5061 5129 ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 5062 5130 || (( ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 5063 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) /*|| 5064 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) || 5065 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 5066 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 5067 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) || 5068 ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )*/ ) && 5131 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) ) && 5069 5132 ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 5070 || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) /*|| ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || 5071 ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT )*/ ) && 5133 || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ) && 5072 5134 ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) ) 5073 5135 { … … 5158 5220 } 5159 5221 5222 if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) 5223 { 5224 m_cost_ins_tlb_occup_cache_frz++; 5225 } 5226 5160 5227 m_cpt_dcache_dir_write++; 5161 5228 m_cpt_dcache_data_write++; … … 5188 5255 m_cost_data_tlb_miss_frz++; 5189 5256 } 5257 if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) 5258 { 5259 m_cost_ins_tlb_occup_cache_frz++; 5260 } 5190 5261 5191 5262 r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read()); … … 5210 5281 { 5211 5282 m_cost_data_tlb_miss_frz++; 5283 } 5284 if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) 5285 { 5286 m_cost_ins_tlb_occup_cache_frz++; 5212 5287 } 5213 5288 … … 5241 5316 { 5242 5317 m_cost_data_tlb_miss_frz++; 5318 } 5319 if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) 5320 { 5321 m_cost_ins_tlb_occup_cache_frz++; 5243 5322 } 5244 5323 … … 5281 5360 case DCACHE_ITLB_CLEANUP: 5282 5361 { 5283 //if ( dreq.valid ) m_cost_data_miss_frz++;5284 5285 5362 r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()<<(uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false); 5286 5363 r_dcache_itlb_cleanup_req = false; … … 5762 5839 { 5763 5840 r_dcache_tlb_sc_fail = true; 5764 //r_dcache_tlb_ll_acc_req = true;5765 5841 } 5766 5842 r_dcache_tlb_sc_acc_req = false; … … 5803 5879 { 5804 5880 r_dcache_tlb_sc_fail = true; 5805 //r_dcache_tlb_ll_dirty_req = true;5806 5881 } 5807 5882 r_dcache_tlb_sc_dirty_req = false; … … 5870 5945 } // end switch r_vci_rsp_fsm 5871 5946 5872 // add for blocage 5873 switch (r_cleanup_fsm) { 5874 5875 case CLEANUP_IDLE: 5876 { 5877 if ( p_vci_ini_c.cmdack.read() ) 5878 { 5879 if (r_dcache_cleanup_req) 5880 { 5881 r_cleanup_fsm = CLEANUP_DATA; 5947 ////////////////////////////////////////////////////////////////////////// 5948 // CLEANUP CMD FSM 5949 // 5950 // This FSM is synchronized with the CLEANUP RSP FSM, as both FSMs exit the 5951 // IDLE state simultaneously. 5952 ////////////////////////////////////////////////////////////////////////// 5953 5954 switch (r_cleanup_cmd_fsm) { 5955 5956 case CLEANUP_CMD_IDLE: 5957 if (r_cleanup_rsp_fsm != CLEANUP_RSP_IDLE) 5958 break; 5959 5960 if (r_dcache_cleanup_req) 5961 { 5962 r_cleanup_cmd_fsm = CLEANUP_CMD_DATA; 5882 5963 m_cpt_dcleanup_transaction++; 5883 5884 5885 5886 r_cleanup_fsm = CLEANUP_INS;5964 } 5965 else if (r_icache_cleanup_req) 5966 { 5967 r_cleanup_cmd_fsm = CLEANUP_CMD_INS; 5887 5968 m_cpt_icleanup_transaction++; 5888 } 5889 } 5890 break; 5891 } 5892 case CLEANUP_DATA: 5893 { 5894 m_cost_dcleanup_transaction++; 5969 } 5970 break; 5971 5972 default: 5973 if ( p_vci_ini_c.cmdack.read() ) 5974 { 5975 r_cleanup_cmd_fsm = CLEANUP_CMD_IDLE; 5976 } 5977 break; 5978 5979 } // end switch r_vci_cmd_fsm 5980 5981 ////////////////////////////////////////////////////////////////////////// 5982 // CLEANUP RSP FSM 5983 // 5984 // This FSM is synchronized with the CLEANUP CMD FSM, as both FSMs exit the 5985 // IDLE state simultaneously. 5986 ////////////////////////////////////////////////////////////////////////// 5987 5988 switch (r_cleanup_rsp_fsm) { 5989 5990 case CLEANUP_RSP_IDLE: 5991 { 5992 assert(!p_vci_ini_c.rspval.read() && "Unexpected response" ); 5993 5994 if (r_cleanup_cmd_fsm != CLEANUP_CMD_IDLE) 5995 break; 5996 5997 if (r_dcache_cleanup_req) 5998 { 5999 r_cleanup_rsp_fsm = CLEANUP_RSP_DATA; 6000 } 6001 else if (r_icache_cleanup_req) 6002 { 6003 r_cleanup_rsp_fsm = CLEANUP_RSP_INS; 6004 } 6005 break; 6006 } 6007 case CLEANUP_RSP_DATA: 6008 { 6009 m_cost_dcleanup_transaction++; 6010 if ( ! p_vci_ini_c.rspval.read() ) 6011 break; 6012 assert( p_vci_ini_c.reop.read() && 6013 "illegal VCI response packet for dcache cleanup"); 6014 assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) && 6015 "error in response packet for dcache cleanup"); 6016 6017 r_dcache_cleanup_req = false; 6018 r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE; 6019 break; 6020 } 6021 case CLEANUP_RSP_INS: 6022 { 6023 m_cost_icleanup_transaction++; 5895 6024 if ( ! p_vci_ini_c.rspval.read() ) 5896 6025 break; … … 5900 6029 "error in response packet for icache cleanup"); 5901 6030 5902 r_dcache_cleanup_req = false;5903 r_cleanup_fsm = CLEANUP_IDLE;5904 break;5905 }5906 case CLEANUP_INS:5907 {5908 m_cost_icleanup_transaction++;5909 if ( ! p_vci_ini_c.rspval.read() )5910 break;5911 assert( p_vci_ini_c.reop.read() &&5912 "illegal VCI response packet for icache cleanup");5913 assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&5914 "error in response packet for icache cleanup");5915 5916 6031 r_icache_cleanup_req = false; 5917 r_cleanup_ fsm = CLEANUP_IDLE;6032 r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE; 5918 6033 break; 5919 6034 } … … 6111 6226 } // end switch r_vci_cmd_fsm 6112 6227 6113 6114 // VCI initiator command 6115 switch (r_cleanup_fsm) { 6116 6117 case CLEANUP_IDLE: 6118 p_vci_ini_c.cmdval = r_icache_cleanup_req || r_dcache_cleanup_req; 6119 p_vci_ini_c.rspack = false; 6120 if ( r_icache_cleanup_req ) 6121 { 6122 p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2); 6123 p_vci_ini_c.trdid = 1; // cleanup instruction 6124 } 6125 else 6126 { 6127 p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2); 6128 p_vci_ini_c.trdid = 0; // cleanup data 6129 } 6130 p_vci_ini_c.wdata = 0; 6131 p_vci_ini_c.be = 0; 6132 p_vci_ini_c.plen = 4; 6133 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 6134 p_vci_ini_c.pktid = 0; 6135 p_vci_ini_c.srcid = m_srcid_c; 6136 p_vci_ini_c.cons = false; 6137 p_vci_ini_c.wrap = false; 6138 p_vci_ini_c.contig = false; 6139 p_vci_ini_c.clen = 0; 6140 p_vci_ini_c.cfixed = false; 6141 p_vci_ini_c.eop = true; 6142 break; 6143 6144 case CLEANUP_DATA: 6145 case CLEANUP_INS: 6228 p_vci_ini_c.rspack = true; 6229 6230 switch (r_cleanup_cmd_fsm) { 6231 6232 case CLEANUP_CMD_IDLE: 6146 6233 p_vci_ini_c.cmdval = false; 6147 p_vci_ini_c.rspack = true;6148 6234 p_vci_ini_c.address = 0; 6149 6235 p_vci_ini_c.trdid = 0; … … 6162 6248 break; 6163 6249 6250 case CLEANUP_CMD_DATA: 6251 p_vci_ini_c.cmdval = true; 6252 p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2); 6253 p_vci_ini_c.trdid = 0; // data cleanup 6254 p_vci_ini_c.wdata = 0; 6255 p_vci_ini_c.be = 0; 6256 p_vci_ini_c.plen = 4; 6257 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 6258 p_vci_ini_c.pktid = 0; 6259 p_vci_ini_c.srcid = m_srcid_c; 6260 p_vci_ini_c.cons = false; 6261 p_vci_ini_c.wrap = false; 6262 p_vci_ini_c.contig = false; 6263 p_vci_ini_c.clen = 0; 6264 p_vci_ini_c.cfixed = false; 6265 p_vci_ini_c.eop = true; 6266 break; 6267 6268 case CLEANUP_CMD_INS: 6269 p_vci_ini_c.cmdval = true; 6270 p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2); 6271 p_vci_ini_c.trdid = 1; // ins cleanup 6272 p_vci_ini_c.wdata = 0; 6273 p_vci_ini_c.be = 0; 6274 p_vci_ini_c.plen = 4; 6275 p_vci_ini_c.cmd = vci_param::CMD_WRITE; 6276 p_vci_ini_c.pktid = 0; 6277 p_vci_ini_c.srcid = m_srcid_c; 6278 p_vci_ini_c.cons = false; 6279 p_vci_ini_c.wrap = false; 6280 p_vci_ini_c.contig = false; 6281 p_vci_ini_c.clen = 0; 6282 p_vci_ini_c.cfixed = false; 6283 p_vci_ini_c.eop = true; 6284 break; 6164 6285 } // end switch r_vci_cmd_cleanup_fsm 6165 6166 6286 6167 6287 // VCI_TGT
Note: See TracChangeset
for help on using the changeset viewer.