Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
===================================================================
--- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 134)
+++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 140)
@@ -31,4 +31,5 @@
 
 #include <inttypes.h>
+#include <fstream>
 #include <systemc>
 #include <queue>
@@ -71,4 +72,8 @@
  *     4    - one access with round robin priority
  * 
+ * CC_XCACHE_WRAPPER_MULTI_CACHE :
+ *     1    - icache static partitionnement
+ *     2    - icache dedicated
+ *
  * CC_XCACHE_WRAPPER_STOP_SIMULATION :
  *   stop simulation if processor is stall after a long time
@@ -81,39 +86,53 @@
  *   Number of cycle before to prinf debug message
  *
- * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
- *   Print transaction between the cpu and the cache
+ * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+ *   Print transaction between :
+ *     - the cpu and the cache (icache and dcache)
+ *     - vci
+ *     - cleanup
+ *     - coherency
  */
 
 // implementation
 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM
-#define CC_XCACHE_WRAPPER_SELECT_VICTIM             0
+#define CC_XCACHE_WRAPPER_SELECT_VICTIM               1
 #endif
 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP
-#define CC_XCACHE_WRAPPER_FIFO_RSP                  0
+#define CC_XCACHE_WRAPPER_FIFO_RSP                    1
 #endif
 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
-#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE     1
+#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE       1
 #endif
 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
-#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1
+#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT   1
 #endif
 #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME
-#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME        0
+#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME          2
 #endif
 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY
-#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY          2
+#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY            4
+#endif  
+#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
+#define CC_XCACHE_WRAPPER_MULTI_CACHE                 2
 #endif  
 // debugging
 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
-#define CC_XCACHE_WRAPPER_STOP_SIMULATION           1
+#define CC_XCACHE_WRAPPER_STOP_SIMULATION             1
 #endif
 #ifndef CC_XCACHE_WRAPPER_DEBUG
-#define CC_XCACHE_WRAPPER_DEBUG                     0
+#define CC_XCACHE_WRAPPER_DEBUG                       0
 #endif
 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
-#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN           200000
-#endif
-#ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
-#define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION  0
+#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN             949900
+#endif
+#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION      0
+#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
+#endif
+
+// don't change
+#if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
+#undef  CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
+#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT   0
 #endif
 
@@ -204,6 +223,7 @@
     enum cleanup_fsm_state_e {
         CLEANUP_IDLE,
-        CLEANUP_DCACHE,
-        CLEANUP_ICACHE,
+        CLEANUP_REQ,
+        CLEANUP_RSP_DCACHE,
+        CLEANUP_RSP_ICACHE,
     };
 
@@ -231,5 +251,5 @@
     sc_in<bool>                             p_clk;
     sc_in<bool>                             p_resetn;
-    sc_in<bool>                             p_irq[iss_t::n_irq];
+    sc_in<bool>                          ** p_irq;//[m_nb_cpu][iss_t::n_irq];
     soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
     soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
@@ -241,8 +261,12 @@
     const soclib::common::AddressDecodingTable<vci_addr_t, bool>    m_cacheability_table;
     const soclib::common::Segment                                   m_segment;
-    iss_t               m_iss;
+    iss_t            ** m_iss; //[m_nb_cpu]
     const uint32_t      m_srcid_rw;   
     const uint32_t      m_srcid_c;   
     
+    const size_t        m_nb_cpu;
+    const size_t        m_nb_icache;
+    const size_t        m_nb_dcache;
+    const size_t        m_nb_cache;
     const size_t        m_dcache_ways;
     const size_t        m_dcache_words;
@@ -258,41 +282,48 @@
     bool                m_stop_simulation;
     uint32_t            m_stop_simulation_nb_frz_cycles_max;
-    uint32_t            m_stop_simulation_nb_frz_cycles;
+    uint32_t          * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
 
     // REGISTERS
-    sc_signal<int>          r_dcache_fsm;
-    sc_signal<int>          r_dcache_fsm_save;
-    sc_signal<addr_40>      r_dcache_addr_save;
-    sc_signal<data_t>       r_dcache_wdata_save;
-    sc_signal<data_t>       r_dcache_rdata_save;
-    sc_signal<int>          r_dcache_type_save;
-    sc_signal<be_t>         r_dcache_be_save;
-    sc_signal<bool>         r_dcache_cached_save;
-    sc_signal<bool>         r_dcache_cleanup_req;
-    sc_signal<addr_40>      r_dcache_cleanup_line;
-    sc_signal<bool>         r_dcache_miss_req;
-    sc_signal<size_t>       r_dcache_miss_way;
-    sc_signal<size_t>       r_dcache_miss_set;
-    sc_signal<bool>         r_dcache_unc_req;
-    sc_signal<bool>         r_dcache_sc_req;
-    sc_signal<bool>         r_dcache_inval_rsp;
-    sc_signal<size_t>       r_dcache_update_addr;
-    sc_signal<data_64>      r_dcache_ll_data;
-    sc_signal<addr_40>      r_dcache_ll_addr;
-    sc_signal<bool>         r_dcache_ll_valid;
-    sc_signal<bool>         r_dcache_previous_unc;
-
-    sc_signal<int>          r_icache_fsm;
-    sc_signal<int>          r_icache_fsm_save;
-    sc_signal<addr_40>      r_icache_addr_save;
-    sc_signal<bool>         r_icache_miss_req;
-    sc_signal<size_t>       r_icache_miss_way;
-    sc_signal<size_t>       r_icache_miss_set;
-    sc_signal<bool>         r_icache_unc_req;
-    sc_signal<bool>         r_icache_cleanup_req;
-    sc_signal<addr_40>      r_icache_cleanup_line;
-    sc_signal<bool>         r_icache_inval_rsp;
-    sc_signal<size_t>       r_icache_update_addr;
+    sc_signal<uint32_t>     r_cpu_prior;
+    sc_signal<uint32_t>   * r_icache_lock;//[m_nb_icache]
+    sc_signal<uint32_t>   * r_dcache_lock;//[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_sync;//[m_nb_dcache]
+
+    sc_signal<int>        * r_dcache_fsm;          //[m_nb_dcache]
+    sc_signal<int>        * r_dcache_fsm_save;     //[m_nb_dcache]
+    sc_signal<addr_40>    * r_dcache_addr_save;    //[m_nb_dcache]
+    sc_signal<data_t>     * r_dcache_wdata_save;   //[m_nb_dcache]
+    sc_signal<data_t>     * r_dcache_rdata_save;   //[m_nb_dcache]
+    sc_signal<int>        * r_dcache_type_save;    //[m_nb_dcache]
+    sc_signal<be_t>       * r_dcache_be_save;      //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_cached_save;  //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_cleanup_req;  //[m_nb_dcache]
+    sc_signal<addr_40>    * r_dcache_cleanup_line; //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_miss_req;     //[m_nb_dcache]
+    sc_signal<size_t>     * r_dcache_miss_way;     //[m_nb_dcache]
+    sc_signal<size_t>     * r_dcache_miss_set;     //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_unc_req;      //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_sc_req;       //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_inval_rsp;    //[m_nb_dcache]
+    sc_signal<size_t>     * r_dcache_update_addr;  //[m_nb_dcache]
+    sc_signal<data_64>   ** r_dcache_ll_data;      //[m_nb_dcache][m_nb_cpu]
+    sc_signal<addr_40>   ** r_dcache_ll_addr;      //[m_nb_dcache][m_nb_cpu]
+    sc_signal<bool>      ** r_dcache_ll_valid;     //[m_nb_dcache][m_nb_cpu]
+    sc_signal<uint32_t>   * r_dcache_num_cpu_save; //[m_nb_dcache]
+    sc_signal<bool>       * r_dcache_previous_unc; //[m_nb_dcache]
+                                                   
+    sc_signal<int>        * r_icache_fsm;          //[m_nb_icache]
+    sc_signal<int>        * r_icache_fsm_save;     //[m_nb_icache]
+    sc_signal<addr_40>    * r_icache_addr_save;    //[m_nb_icache]
+    sc_signal<bool>       * r_icache_miss_req;     //[m_nb_icache]
+    sc_signal<size_t>     * r_icache_miss_way;     //[m_nb_icache]
+    sc_signal<size_t>     * r_icache_miss_set;     //[m_nb_icache]
+    sc_signal<bool>       * r_icache_unc_req;      //[m_nb_icache]
+    sc_signal<bool>       * r_icache_cleanup_req;  //[m_nb_icache]
+    sc_signal<addr_40>    * r_icache_cleanup_line; //[m_nb_icache]
+    sc_signal<bool>       * r_icache_inval_rsp;    //[m_nb_icache]
+    sc_signal<size_t>     * r_icache_update_addr;  //[m_nb_icache]
+    sc_signal<bool>       * r_icache_buf_unc_valid;//[m_nb_icache]
 
     sc_signal<int>          r_vci_cmd_fsm;
@@ -301,24 +332,24 @@
     sc_signal<size_t>       r_vci_cmd_cpt;       
     sc_signal<bool>         r_vci_cmd_dcache_prior;
-      
+    sc_signal<uint32_t>     r_vci_cmd_num_cache;
+
     sc_signal<int>          r_vci_rsp_fsm;
-    sc_signal<bool>         r_vci_rsp_ins_error;    
-    sc_signal<bool>         r_vci_rsp_data_error;    
     sc_signal<size_t>       r_vci_rsp_cpt;  
-    sc_signal<bool>         r_vci_rsp_ack;
+              bool          s_vci_rsp_ack;
+    sc_signal<uint32_t>     r_vci_rsp_num_cache;
+    sc_signal<bool>       * r_vci_rsp_ins_error;  //[m_nb_icache]
+    sc_signal<bool>       * r_vci_rsp_data_error; //[m_nb_dcache]
 
 #if CC_XCACHE_WRAPPER_FIFO_RSP
-    std::queue<data_t>      r_icache_miss_buf;
-    std::queue<data_t>      r_dcache_miss_buf;
+    std::queue<data_t>    * r_icache_miss_buf;    //[m_nb_icache]
+    std::queue<data_t>    * r_dcache_miss_buf;    //[m_nb_dcache]
 #else
-    bool                   *r_icache_miss_val;    //[m_icache_words]
-    data_t                 *r_icache_miss_buf;    //[m_icache_words]
-    bool                   *r_dcache_miss_val;    //[m_dcache_words]
-    data_t                 *r_dcache_miss_buf;    //[m_dcache_words]
-#endif
-    sc_signal<bool>         r_icache_buf_unc_valid;
-
-    data_t                 *r_tgt_buf;            //[m_cache_words]
-    be_t                   *r_tgt_be;             //[m_cache_words]
+    bool                 ** r_icache_miss_val;    //[m_nb_icache][m_icache_words]
+    data_t               ** r_icache_miss_buf;    //[m_nb_icache][m_icache_words]
+    bool                 ** r_dcache_miss_val;    //[m_nb_dcache][m_dcache_words]
+    data_t               ** r_dcache_miss_buf;    //[m_nb_dcache][m_dcache_words]
+#endif
+    data_t                * r_tgt_buf;            //[m_cache_words]
+    be_t                  * r_tgt_be;             //[m_cache_words]
 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
     sc_signal<uint32_t>     r_cache_word;
@@ -326,5 +357,6 @@
 
     sc_signal<int>          r_vci_tgt_fsm;
-    sc_signal<addr_40>      r_tgt_addr;
+    sc_signal<addr_40>      r_tgt_iaddr;
+    sc_signal<addr_40>      r_tgt_daddr;
     sc_signal<size_t>       r_tgt_word;
     sc_signal<bool>         r_tgt_update;
@@ -335,64 +367,96 @@
     sc_signal<size_t>       r_tgt_trdid;
   //sc_signal<size_t>       r_tgt_plen;
-    sc_signal<bool>         r_tgt_icache_req;
-    sc_signal<bool>         r_tgt_dcache_req;
-    sc_signal<bool>         r_tgt_icache_rsp;
-    sc_signal<bool>         r_tgt_dcache_rsp;
+    sc_signal<uint32_t>     r_tgt_num_cache;
+    sc_signal<bool>       * r_tgt_icache_req; //[m_nb_icache]
+    sc_signal<bool>       * r_tgt_icache_rsp; //[m_nb_icache]
+    sc_signal<bool>       * r_tgt_dcache_req; //[m_nb_dcache]
+    sc_signal<bool>       * r_tgt_dcache_rsp; //[m_nb_dcache]
 
     sc_signal<int>          r_cleanup_fsm;		// controls initiator port of the coherence network
-
-    MultiWriteBuffer<addr_40>   r_wbuf;
-    GenericCache<vci_addr_t>    r_icache;
-    GenericCache<vci_addr_t>    r_dcache;
-
-#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
-    std::ofstream               log_dcache_transaction_file;
+    sc_signal<uint32_t>     r_cleanup_num_cache;
+    sc_signal<bool>         r_cleanup_icache;
+
+    MultiWriteBuffer<addr_40>** r_wbuf;
+    GenericCache<vci_addr_t> ** r_icache;
+    GenericCache<vci_addr_t> ** r_dcache;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+    std::ofstream             * log_transaction_file_icache; //[m_nb_cpu]
+    std::ofstream             * log_transaction_file_dcache; //[m_nb_cpu]
+    std::ofstream               log_transaction_file_cmd;
+    std::ofstream               log_transaction_file_tgt;
+    std::ofstream               log_transaction_file_cleanup;
 #endif
 
     // Activity counters
-    uint32_t m_cpt_dcache_data_read;             // * DCACHE DATA READ
-    uint32_t m_cpt_dcache_data_write;            // * DCACHE DATA WRITE
-    uint32_t m_cpt_dcache_dir_read;              // * DCACHE DIR READ
-    uint32_t m_cpt_dcache_dir_write;             // * DCACHE DIR WRITE
-                                                 
-    uint32_t m_cpt_icache_data_read;             // * ICACHE DATA READ
-    uint32_t m_cpt_icache_data_write;            // * ICACHE DATA WRITE
-    uint32_t m_cpt_icache_dir_read;              // * ICACHE DIR READ
-    uint32_t m_cpt_icache_dir_write;             // * ICACHE DIR WRITE
-
-    uint32_t m_cpt_cc_update_icache;             // number of coherence update packets (for icache)
-    uint32_t m_cpt_cc_update_dcache;             // number of coherence update packets (for dcache)
-    uint32_t m_cpt_cc_inval_broadcast;           // number of coherence inval packets
-    uint32_t m_cpt_cc_inval_icache;              // number of coherence inval packets
-    uint32_t m_cpt_cc_inval_dcache;              // number of coherence inval packets
-    uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
-    uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
-
-    uint32_t m_cpt_frz_cycles;	                 // * number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	             // total number of cycles 
-
-    uint32_t m_cpt_data_read;                    //   number of data read
-    uint32_t m_cpt_data_read_miss;               //   number of data read miss
-    uint32_t m_cpt_data_read_uncached;           //   number of data read uncached
-    uint32_t m_cpt_data_write;                   //   number of data write
-    uint32_t m_cpt_data_write_miss;              //   number of data write miss
-    uint32_t m_cpt_data_write_uncached;          //   number of data write uncached
-    uint32_t m_cpt_ins_miss;                     // * number of instruction miss
-
-    uint32_t m_cost_write_frz;                   // * number of frozen cycles related to write buffer         
-    uint32_t m_cost_data_miss_frz;               // * number of frozen cycles related to data miss
-    uint32_t m_cost_unc_read_frz;                // * number of frozen cycles related to uncached read
-    uint32_t m_cost_ins_miss_frz;                // * number of frozen cycles related to ins miss
-
-    uint32_t m_cpt_imiss_transaction;            // * number of VCI instruction miss transactions
-    uint32_t m_cpt_dmiss_transaction;            // * number of VCI data miss transactions
-    uint32_t m_cpt_unc_transaction;              // * number of VCI uncached read transactions
-    uint32_t m_cpt_data_write_transaction;       // * number of VCI write transactions
-
-    uint32_t m_cost_imiss_transaction;           // * cumulated duration for VCI IMISS transactions
-    uint32_t m_cost_dmiss_transaction;           // * cumulated duration for VCI DMISS transactions
-    uint32_t m_cost_unc_transaction;             // * cumulated duration for VCI UNC transactions
-    uint32_t m_cost_write_transaction;           // * cumulated duration for VCI WRITE transactions
-    uint32_t m_length_write_transaction;         // * cumulated length for VCI WRITE transactions
+    uint32_t   m_cpt_dcache_data_read;             // * DCACHE DATA READ
+    uint32_t   m_cpt_dcache_data_write;            // * DCACHE DATA WRITE
+    uint32_t   m_cpt_dcache_dir_read;              // * DCACHE DIR READ
+    uint32_t   m_cpt_dcache_dir_write;             // * DCACHE DIR WRITE
+                                                   
+    uint32_t   m_cpt_icache_data_read;             // * ICACHE DATA READ
+    uint32_t   m_cpt_icache_data_write;            // * ICACHE DATA WRITE
+    uint32_t   m_cpt_icache_dir_read;              // * ICACHE DIR READ
+    uint32_t   m_cpt_icache_dir_write;             // * ICACHE DIR WRITE
+               
+    uint32_t   m_cpt_cc_update_icache;             // number of coherence update packets (for icache)
+    uint32_t   m_cpt_cc_update_dcache;             // number of coherence update packets (for dcache)
+    uint32_t   m_cpt_cc_inval_broadcast;           // number of coherence inval packets
+    uint32_t   m_cpt_cc_inval_icache;              // number of coherence inval packets
+    uint32_t   m_cpt_cc_inval_dcache;              // number of coherence inval packets
+    uint32_t   m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
+    uint32_t   m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
+               
+    uint32_t * m_cpt_frz_cycles;	               // * number of cycles where the cpu is frozen
+    uint32_t   m_cpt_total_cycles;	               // total number of cycles 
+               
+    uint32_t   m_cpt_data_read;                    //   number of data read
+    uint32_t   m_cpt_data_read_miss;               //   number of data read miss
+    uint32_t   m_cpt_data_read_uncached;           //   number of data read uncached
+    uint32_t   m_cpt_data_write;                   //   number of data write
+    uint32_t   m_cpt_data_write_miss;              //   number of data write miss
+    uint32_t   m_cpt_data_write_uncached;          //   number of data write uncached
+    uint32_t   m_cpt_ins_miss;                     // * number of instruction miss
+               
+    uint32_t   m_cost_write_frz;                   // * number of frozen cycles related to write buffer         
+    uint32_t   m_cost_data_miss_frz;               // * number of frozen cycles related to data miss
+    uint32_t   m_cost_unc_read_frz;                // * number of frozen cycles related to uncached read
+    uint32_t   m_cost_ins_miss_frz;                // * number of frozen cycles related to ins miss
+               
+    uint32_t   m_cpt_imiss_transaction;            // * number of VCI instruction miss transactions
+    uint32_t   m_cpt_dmiss_transaction;            // * number of VCI data miss transactions
+    uint32_t   m_cpt_unc_transaction;              // * number of VCI uncached read transactions
+    uint32_t   m_cpt_data_write_transaction;       // * number of VCI write transactions
+               
+    uint32_t   m_cost_imiss_transaction;           // * cumulated duration for VCI IMISS transactions
+    uint32_t   m_cost_dmiss_transaction;           // * cumulated duration for VCI DMISS transactions
+    uint32_t   m_cost_unc_transaction;             // * cumulated duration for VCI UNC transactions
+    uint32_t   m_cost_write_transaction;           // * cumulated duration for VCI WRITE transactions
+    uint32_t   m_length_write_transaction;         // * cumulated length for VCI WRITE transactions
+
+    uint32_t * m_cpt_icache_access; //[m_nb_icache]
+    uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
+
+    uint32_t ** m_cpt_fsm_dcache;  //[m_nb_dcache]
+    uint32_t ** m_cpt_fsm_icache;  //[m_nb_icache]
+    uint32_t  * m_cpt_fsm_cmd;
+    uint32_t  * m_cpt_fsm_rsp;
+    uint32_t  * m_cpt_fsm_tgt;
+    uint32_t  * m_cpt_fsm_cleanup;
+
+    // Non blocking multi-cache
+    typename iss_t::InstructionRequest  * ireq        ; //[m_nb_icache]
+    typename iss_t::InstructionResponse * irsp        ; //[m_nb_icache]
+    bool                                * ireq_cached ; //[m_nb_icache]
+    uint32_t                            * ireq_num_cpu; //[m_nb_dcache]
+    typename iss_t::DataRequest         * dreq        ; //[m_nb_dcache]
+    typename iss_t::DataResponse        * drsp        ; //[m_nb_dcache]
+    bool                                * dreq_cached ; //[m_nb_dcache]
+    uint32_t                            * dreq_num_cpu; //[m_nb_dcache]
+
+    const uint32_t m_num_cache_LSB;
+    const uint32_t m_num_cache_MSB;
+          addr_40  m_num_cache_LSB_mask;
+          addr_40  m_num_cache_mask;
 
 protected:
@@ -409,4 +473,6 @@
                        const soclib::common::IntTab &initiator_index_c,
                        const soclib::common::IntTab &target_index,
+                       size_t nb_cpu,
+                       size_t nb_cache,
                        size_t icache_ways,
                        size_t icache_sets,
@@ -435,5 +501,10 @@
     void genMoore();
 
-    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    uint32_t get_num_cache     (addr_40 & addr);
+    uint32_t get_num_cache_only(addr_40   addr);
+    void     set_num_cache     (addr_40 & addr, uint32_t num_cache);
+    addr_40  set_num_cache_only(addr_40   addr, uint32_t num_cache);
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC     == (int)vci_param::STORE_COND_ATOMIC);
     soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
 };
