Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
===================================================================
--- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 134)
+++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 140)
@@ -55,49 +55,127 @@
 ///////////////////////////////////////////////////////////////////////////////
 
-#include <cassert>
 #include <iomanip>
 #include "arithmetics.h"
+#include "size.h"
 #include "../include/vci_cc_xcache_wrapper_v4.h"
 
+// =====[ DEBUG ]====================================
+
+#define ASSERT_VERBOSE
+#define ASSERT_NCYCLES m_cpt_total_cycles
+
+#include "debug.h"
+
 #if CC_XCACHE_WRAPPER_DEBUG
-# define PRINTF(msg...) do { if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) printf(msg); } while (0); 
+# define PRINTF(msg...) PRINTF_COND(m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN,msg)
 #else
 # define PRINTF(msg...)
 #endif
 
-# define ASSERT(cond,msg) assert ((cond) and msg);
-
+// =====[ FIFO_RSP ]=================================
+
+// FIXME : une FIFO avec le numéro du cache !
 #if CC_XCACHE_WRAPPER_FIFO_RSP
-# define CACHE_MISS_BUF_ALLOC
-# define CACHE_MISS_BUF_DEALLOC
-# define CACHE_MISS_BUF_RESET(c)        while (r_##c##cache_miss_buf.size()>0) {r_##c##cache_miss_buf.pop();}
-# define CACHE_MISS_BUF_REQ_INIT(c)
-# define CACHE_MISS_BUF_RSP_VAL(c,n)    (r_##c##cache_miss_buf.size()>0)
-# define CACHE_MISS_BUF_RSP_ACK(c)      (r_##c##cache_miss_buf.size()<2)
-# define CACHE_MISS_BUF_RSP_DATA(c,n)   r_##c##cache_miss_buf.front()
-# define CACHE_MISS_BUF_RSP_POP(c)      do { r_##c##cache_miss_buf.pop();} while (0)
-# define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do { r_##c##cache_miss_buf.push(d);} while (0)
-# define CACHE_MISS_BUF_RSP_PRINT(c)    do { PRINTF("    * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size());} while (0)
+# define CACHE_MISS_BUF_ALLOC             do { \
+                                              r_icache_miss_buf = new std::queue<data_t> [m_nb_icache]; \
+                                              r_dcache_miss_buf = new std::queue<data_t> [m_nb_dcache]; \
+                                          } while (0)
+# define CACHE_MISS_BUF_DEALLOC           do { \
+                                              delete [] r_icache_miss_buf; \
+                                              delete [] r_dcache_miss_buf; \
+                                          } while (0)
+# define CACHE_MISS_BUF_RESET(c)          do { \
+                                              for (uint32_t x=0; x<m_nb_##c##cache; ++x) { \
+                                                  while (r_##c##cache_miss_buf[x].size()>0) { \
+                                                      r_##c##cache_miss_buf[x].pop(); \
+                                                  } \
+                                              } \
+                                          } while (0)
+# define CACHE_MISS_BUF_REQ_INIT(c,x)      
+# define CACHE_MISS_BUF_RSP_VAL(c,x,n)    (r_##c##cache_miss_buf[x].size()>0)
+# define CACHE_MISS_BUF_RSP_ACK(c,x)      (r_##c##cache_miss_buf[x].size()<2)
+# define CACHE_MISS_BUF_RSP_DATA(c,x,n)   r_##c##cache_miss_buf[x].front()
+# define CACHE_MISS_BUF_RSP_POP(c,x)      do {                                            \
+                                              r_##c##cache_miss_buf[x].pop(); \
+                                          } while (0)
+# define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \
+                                              r_##c##cache_miss_buf[x].push(d); \
+                                          } while (0)
+# define CACHE_MISS_BUF_RSP_PRINT(c)      do { \
+                                              for (uint32_t x=0; x<m_nb_##c##cache; ++x) { \
+                                                  PRINTF("    * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf[x].size()); \
+                                              } \
+                                          } while (0)
+#else                                      
+# define CACHE_MISS_BUF_ALLOC             do { \
+                                              r_icache_miss_val = new bool   * [m_nb_icache]; \
+                                              r_icache_miss_buf = new data_t * [m_nb_icache]; \
+                                              for (uint32_t x=0; x<m_nb_icache;++x) { \
+                                                  r_icache_miss_val [x] = new bool   [m_icache_words]; \
+                                                  r_icache_miss_buf [x] = new data_t [m_icache_words]; \
+                                              } \
+                                              r_dcache_miss_val = new bool   * [m_nb_dcache]; \
+                                              r_dcache_miss_buf = new data_t * [m_nb_dcache]; \
+                                              for (uint32_t x=0; x<m_nb_dcache;++x) { \
+                                                  r_dcache_miss_val [x] = new bool   [m_dcache_words]; \
+                                                  r_dcache_miss_buf [x] = new data_t [m_dcache_words]; \
+                                              } \
+                                          } while (0)
+# define CACHE_MISS_BUF_DEALLOC           do { \
+                                              for (uint32_t x=0; x<m_nb_icache;++x) { \
+                                                  delete [] r_icache_miss_val[x]; \
+                                                  delete [] r_icache_miss_buf[x]; \
+                                              } \
+                                              delete [] r_icache_miss_val; \
+                                              delete [] r_icache_miss_buf; \
+                                              for (uint32_t x=0; x<m_nb_dcache;++x) { \
+                                                  delete [] r_dcache_miss_val[x]; \
+                                                  delete [] r_dcache_miss_buf[x]; \
+                                              } \
+                                              delete [] r_dcache_miss_val; \
+                                              delete [] r_dcache_miss_buf; \
+                                          } while (0)
+# define CACHE_MISS_BUF_RESET(c)           
+# define CACHE_MISS_BUF_REQ_INIT(c,x)     do { \
+                                              for (uint32_t i=0; i<m_##c##cache_words;++i) \
+                                                  r_##c##cache_miss_val[x][i] = false; \
+                                          } while (0)
+# define CACHE_MISS_BUF_RSP_VAL(c,x,n)    r_##c##cache_miss_val[x][n]
+# define CACHE_MISS_BUF_RSP_ACK(c,x)      true
+# define CACHE_MISS_BUF_RSP_DATA(c,x,n)   r_##c##cache_miss_buf[x][n]
+# define CACHE_MISS_BUF_RSP_POP(c,x)         
+# define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \
+                                              r_##c##cache_miss_val[x][n] = true; \
+                                              r_##c##cache_miss_buf[x][n] = d; \
+                                          } while (0)
+# define CACHE_MISS_BUF_RSP_PRINT(c)      do { \
+                                              for (uint32_t x=0; x<m_nb_##c##cache;++x) \
+                                                  for (uint32_t i=0; i<m_##c##cache_words;++i) \
+                                                      PRINTF("%d %x |",r_##c##cache_miss_val[x][i],r_##c##cache_miss_buf[x][i]); PRINTF("\n"); \
+                                          } while (0)
+#endif
+
+// =====[ MULTI_CACHE ]==============================
+
+#if (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+# define get_num_icache(     addr,num_cpu)   get_num_cache     (addr)          
+# define get_num_icache_only(addr,num_cpu)   get_num_cache_only(addr)          
+# define set_num_icache(     addr,num_cache) set_num_cache     (addr,num_cache)
+# define set_num_icache_only(addr,num_cache) set_num_cache_only(addr,num_cache)
+# define get_num_dcache(     addr)           get_num_cache     (addr)          
+# define get_num_dcache_only(addr)           get_num_cache_only(addr)          
+# define set_num_dcache(     addr,num_cache) set_num_cache     (addr,num_cache)
+# define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache)
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+# define get_num_icache(     addr,num_cpu)   num_cpu
+# define get_num_icache_only(addr,num_cpu)   num_cpu
+# define set_num_icache(     addr,num_cache) do  {} while (0)
+# define set_num_icache_only(addr,num_cache) addr
+# define get_num_dcache(     addr)           get_num_cache     (addr)          
+# define get_num_dcache_only(addr)           get_num_cache_only(addr)          
+# define set_num_dcache(     addr,num_cache) set_num_cache     (addr,num_cache)
+# define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache)
 #else
-# define CACHE_MISS_BUF_ALLOC           do { \
-                                        r_icache_miss_val = new bool  [m_icache_words]; \
-                                        r_icache_miss_buf = new data_t[m_icache_words]; \
-                                        r_dcache_miss_val = new bool  [m_dcache_words]; \
-                                        r_dcache_miss_buf = new data_t[m_dcache_words]; \
-                                        } while (0)
-# define CACHE_MISS_BUF_DEALLOC         do { \
-                                        delete [] r_icache_miss_val; \
-                                        delete [] r_icache_miss_buf; \
-                                        delete [] r_dcache_miss_val; \
-                                        delete [] r_dcache_miss_buf; \
-                                        } while (0)
-# define CACHE_MISS_BUF_RESET(c)
-# define CACHE_MISS_BUF_REQ_INIT(c)     do {for (uint32_t i=0; i<m_##c##cache_words;++i) r_##c##cache_miss_val[i] = false;} while (0)
-# define CACHE_MISS_BUF_RSP_VAL(c,n)    r_##c##cache_miss_val[n]
-# define CACHE_MISS_BUF_RSP_ACK(c)      true
-# define CACHE_MISS_BUF_RSP_DATA(c,n)   r_##c##cache_miss_buf[n]
-# define CACHE_MISS_BUF_RSP_POP(c)
-# define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do {r_##c##cache_miss_val[n] = true; r_##c##cache_miss_buf[n] = d;} while (0)
-# define CACHE_MISS_BUF_RSP_PRINT(c)    do {for (uint32_t i=0; i<m_##c##cache_words;++i) PRINTF("%d %x |",r_##c##cache_miss_val[i],r_##c##cache_miss_buf[i]); PRINTF("\n");} while (0)
+#error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE"
 #endif
 
@@ -170,6 +248,7 @@
         const char *cleanup_fsm_state_str[] = {
             "CLEANUP_IDLE",
-            "CLEANUP_DCACHE",
-            "CLEANUP_ICACHE",
+            "CLEANUP_REQ",
+            "CLEANUP_RSP_DCACHE",
+            "CLEANUP_RSP_ICACHE",
         };
     }
@@ -189,4 +268,6 @@
             const soclib::common::IntTab &initiator_index_c,
             const soclib::common::IntTab &target_index,
+            size_t nb_cpu,
+            size_t nb_dcache,
             size_t icache_ways,
             size_t icache_sets,
@@ -210,51 +291,26 @@
             m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()),
             m_segment(mtc.getSegment(target_index)),
-            m_iss(this->name(), proc_id),
             m_srcid_rw(mtp.indexForId(initiator_index_rw)),
             m_srcid_c(mtc.indexForId(initiator_index_c)),
 
+            m_nb_cpu(nb_cpu),
+#if   (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+            m_nb_icache(nb_dcache),
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+            m_nb_icache(m_nb_cpu),
+#endif
+            m_nb_dcache(nb_dcache),
+            m_nb_cache((m_nb_dcache>m_nb_icache)?m_nb_dcache:m_nb_icache),
             m_dcache_ways(dcache_ways),
             m_dcache_words(dcache_words),
-            m_dcache_words_shift(uint32_log2(dcache_words)+2),
+            m_dcache_words_shift(uint32_log2(dcache_words)+uint32_log2(sizeof(data_t))),
             m_dcache_yzmask((~0)<<m_dcache_words_shift),
             m_icache_ways(icache_ways),
             m_icache_words(icache_words),
-            m_icache_words_shift(uint32_log2(icache_words)+2),
+            m_icache_words_shift(uint32_log2(icache_words)+uint32_log2(sizeof(data_t))),
             m_icache_yzmask((~0)<<m_icache_words_shift),
             m_cache_words((dcache_words)?dcache_words:icache_words),
 
-            r_dcache_fsm("r_dcache_fsm"),
-            r_dcache_fsm_save("r_dcache_fsm_save"),
-            r_dcache_addr_save("r_dcache_addr_save"),
-            r_dcache_wdata_save("r_dcache_wdata_save"),
-            r_dcache_rdata_save("r_dcache_rdata_save"),
-            r_dcache_type_save("r_dcache_type_save"),
-            r_dcache_be_save("r_dcache_be_save"),
-            r_dcache_cached_save("r_dcache_cached_save"),
-            r_dcache_cleanup_req("r_dcache_cleanup_req"),
-            r_dcache_cleanup_line("r_dcache_cleanup_line"),
-            r_dcache_miss_req("r_dcache_miss_req"),
-            r_dcache_miss_way("r_dcache_miss_way"),
-            r_dcache_miss_set("r_dcache_miss_set"),
-            r_dcache_unc_req("r_dcache_unc_req"),
-            r_dcache_sc_req("r_dcache_sc_req"),
-            r_dcache_inval_rsp("r_dcache_inval_rsp"),
-            r_dcache_update_addr("r_dcache_update_addr"),
-            r_dcache_ll_data("r_dcache_ll_data"),
-            r_dcache_ll_addr("r_dcache_ll_addr"),
-            r_dcache_ll_valid("r_dcache_ll_valid"),
-            r_dcache_previous_unc("r_dcache_previous_unc"),
-
-            r_icache_fsm("r_icache_fsm"),
-            r_icache_fsm_save("r_icache_fsm_save"),
-            r_icache_addr_save("r_icache_addr_save"),
-            r_icache_miss_req("r_icache_miss_req"),
-            r_icache_miss_way("r_icache_miss_way"),
-            r_icache_miss_set("r_icache_miss_set"),
-            r_icache_unc_req("r_icache_unc_req"),
-            r_icache_cleanup_req("r_icache_cleanup_req"),
-            r_icache_cleanup_line("r_icache_cleanup_line"),
-            r_icache_inval_rsp("r_icache_inval_rsp"),
-            r_icache_update_addr("r_icache_update_addr"),
+            r_cpu_prior("r_cpu_prior"),
 
             r_vci_cmd_fsm("r_vci_cmd_fsm"),
@@ -263,12 +319,10 @@
             r_vci_cmd_cpt("r_vci_cmd_cpt"),
             r_vci_cmd_dcache_prior("r_vci_cmd_dcache_prior"),
+            r_vci_cmd_num_cache("r_vci_cmd_num_cache"),
 
             r_vci_rsp_fsm("r_vci_rsp_fsm"),
-            r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
-            r_vci_rsp_data_error("r_vci_rsp_data_error"),
             r_vci_rsp_cpt("r_vci_rsp_cpt"),
-            r_vci_rsp_ack("r_vci_rsp_ack"),
-
-            r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
+          //s_vci_rsp_ack("s_vci_rsp_ack"),
+            r_vci_rsp_num_cache("r_vci_rsp_num_cache"),
 
 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
@@ -277,5 +331,6 @@
 
             r_vci_tgt_fsm("r_vci_tgt_fsm"),
-            r_tgt_addr("r_tgt_addr"),
+            r_tgt_iaddr("r_tgt_iaddr"),
+            r_tgt_daddr("r_tgt_daddr"),
             r_tgt_word("r_tgt_word"),
             r_tgt_update("r_tgt_update"),
@@ -286,26 +341,236 @@
             r_tgt_trdid("r_tgt_trdid"),
          // r_tgt_plen("r_tgt_plen"),
-            r_tgt_icache_req("r_tgt_icache_req"),
-            r_tgt_dcache_req("r_tgt_dcache_req"),
-            r_tgt_icache_rsp("r_tgt_icache_rsp"),
-            r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
+            r_tgt_num_cache("r_tgt_num_cache"),
 
             r_cleanup_fsm("r_cleanup_fsm"),
-
-            r_wbuf("r_wbuf", wbuf_nwords, wbuf_nlines, wbuf_timeout, dcache_words),
-            r_icache("icache", icache_ways, icache_sets, icache_words),
-            r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+            r_cleanup_num_cache("r_cleanup_num_cache"),
+            r_cleanup_icache("r_cleanup_icache"),
+
+            m_num_cache_LSB(uint32_log2(icache_words) + uint32_log2(sizeof(data_t))),
+            m_num_cache_MSB(uint32_log2(nb_dcache) + m_num_cache_LSB)
             {
                 // Size of word is 32 bits
-                ASSERT( (icache_words*vci_param::B) < (1<<vci_param::K),
-                        "I need more PLEN bits");
-
-                ASSERT( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= wbuf_nlines),
-                        "I need more TRDID bits");
-
+                ASSERT((icache_words*vci_param::B) < (1<<vci_param::K),
+                       "Need more PLEN bits.");
+
+                ASSERT((vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines/m_nb_dcache)),
+                       "Need more TRDID bits.");
+
+                ASSERT(uint32_log2(nb_dcache) <= (1<<vci_param::P),
+                       "Need more PKTID bits.");
+                
+                ASSERT(IS_POW_OF_2(m_nb_dcache),
+                       "nb_dcache must be a power of 2.");
+
+                ASSERT(IS_POW_OF_2(m_nb_cpu) and (m_nb_cpu <= m_nb_dcache) and (m_nb_cpu > 0),
+                       "nb cpu must be a multiple of nb cache.");
+
+                ASSERT(IS_POW_OF_2(m_icache_ways) and (m_nb_icache <= m_icache_ways),
+                       "nb icache ways must be a multiple of nb cache.");
+
+                ASSERT(IS_POW_OF_2(m_dcache_ways) and (m_nb_dcache <= m_dcache_ways),
+                       "nb dcache ways must be a multiple of nb cache.");
+
+                ASSERT(icache_words == dcache_words,
+                       "icache_words must be equal at dcache_words.");
+
+                ASSERT(IS_POW_OF_2(wbuf_nlines) and (m_nb_dcache <= wbuf_nlines),
+                       "wbuf_nlines must be a multiple of nb cache.");
+
+                // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE
+                ASSERT((m_nb_dcache == 1) or (dcache_words >= 16),
+                       "When multi cache is activated, need 4 bits (16 word) to the cache set .");
+
+                p_irq = new sc_in<bool> * [m_nb_cpu];
+                for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                    p_irq [num_cpu] = new sc_in<bool> [iss_t::n_irq];
+
+                m_iss = new iss_t * [m_nb_cpu];
+                for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                {
+                    std::ostringstream iss_name("");
+                    iss_name << this->name() << "_" << num_cpu;
+
+                    m_iss[num_cpu] = new iss_t (iss_name.str().c_str(), proc_id+num_cpu);
+                }
+                
                 CACHE_MISS_BUF_ALLOC;
 
-                r_tgt_buf = new data_t[m_cache_words];
-                r_tgt_be  = new be_t  [m_cache_words];
+                r_icache_lock          = new sc_signal<uint32_t>[m_nb_icache];
+                r_dcache_lock          = new sc_signal<uint32_t>[m_nb_dcache];
+                r_dcache_sync          = new sc_signal<bool>    [m_nb_dcache];
+
+                r_icache_fsm           = new sc_signal<int>     [m_nb_icache];
+                r_icache_fsm_save      = new sc_signal<int>     [m_nb_icache];
+                r_icache_addr_save     = new sc_signal<addr_40> [m_nb_icache];
+                r_icache_miss_req      = new sc_signal<bool>    [m_nb_icache];
+                r_icache_miss_way      = new sc_signal<size_t>  [m_nb_icache];
+                r_icache_miss_set      = new sc_signal<size_t>  [m_nb_icache];
+                r_icache_unc_req       = new sc_signal<bool>    [m_nb_icache];
+                r_icache_cleanup_req   = new sc_signal<bool>    [m_nb_icache];
+                r_icache_cleanup_line  = new sc_signal<addr_40> [m_nb_icache];
+                r_icache_inval_rsp     = new sc_signal<bool>    [m_nb_icache];
+                r_icache_update_addr   = new sc_signal<size_t>  [m_nb_icache];
+                r_icache_buf_unc_valid = new sc_signal<bool>    [m_nb_icache];
+
+                r_dcache_fsm           = new sc_signal<int>     [m_nb_dcache];
+                r_dcache_fsm_save      = new sc_signal<int>     [m_nb_dcache];
+                r_dcache_addr_save     = new sc_signal<addr_40> [m_nb_dcache];
+                r_dcache_wdata_save    = new sc_signal<data_t>  [m_nb_dcache];
+                r_dcache_rdata_save    = new sc_signal<data_t>  [m_nb_dcache];
+                r_dcache_type_save     = new sc_signal<int>     [m_nb_dcache];
+                r_dcache_be_save       = new sc_signal<be_t>    [m_nb_dcache];
+                r_dcache_cached_save   = new sc_signal<bool>    [m_nb_dcache];
+                r_dcache_cleanup_req   = new sc_signal<bool>    [m_nb_dcache];
+                r_dcache_cleanup_line  = new sc_signal<addr_40> [m_nb_dcache];
+                r_dcache_miss_req      = new sc_signal<bool>    [m_nb_dcache];
+                r_dcache_miss_way      = new sc_signal<size_t>  [m_nb_dcache];
+                r_dcache_miss_set      = new sc_signal<size_t>  [m_nb_dcache];
+                r_dcache_unc_req       = new sc_signal<bool>    [m_nb_dcache];
+                r_dcache_sc_req        = new sc_signal<bool>    [m_nb_dcache];
+                r_dcache_inval_rsp     = new sc_signal<bool>    [m_nb_dcache];
+                r_dcache_update_addr   = new sc_signal<size_t>  [m_nb_dcache];
+                r_dcache_previous_unc  = new sc_signal<bool>    [m_nb_dcache];
+
+                r_dcache_num_cpu_save  = new sc_signal<uint32_t>   [m_nb_dcache];
+                r_dcache_ll_data       = new sc_signal<data_64>  * [m_nb_dcache];
+                r_dcache_ll_addr       = new sc_signal<addr_40>  * [m_nb_dcache];
+                r_dcache_ll_valid      = new sc_signal<bool>     * [m_nb_dcache];
+                for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+                {
+                    r_dcache_ll_data    [num_cache] = new sc_signal<data_64>  [m_nb_cpu];
+                    r_dcache_ll_addr    [num_cache] = new sc_signal<addr_40>  [m_nb_cpu];
+                    r_dcache_ll_valid   [num_cache] = new sc_signal<bool>     [m_nb_cpu];
+                }
+
+                r_tgt_icache_req       = new sc_signal<bool>    [m_nb_icache];
+                r_tgt_icache_rsp       = new sc_signal<bool>    [m_nb_icache];
+                r_tgt_dcache_req       = new sc_signal<bool>    [m_nb_dcache];
+                r_tgt_dcache_rsp       = new sc_signal<bool>    [m_nb_dcache];
+
+                r_tgt_buf              = new data_t             [m_cache_words];
+                r_tgt_be               = new be_t               [m_cache_words];
+
+                r_vci_rsp_ins_error    = new sc_signal<bool>    [m_nb_icache];
+                r_vci_rsp_data_error   = new sc_signal<bool>    [m_nb_dcache];
+
+                ireq                   = new typename iss_t::InstructionRequest  [m_nb_icache];
+                irsp                   = new typename iss_t::InstructionResponse [m_nb_icache];
+                ireq_cached            = new bool                                [m_nb_icache];
+                ireq_num_cpu           = new uint32_t                            [m_nb_dcache];
+
+                dreq                   = new typename iss_t::DataRequest         [m_nb_dcache];
+                drsp                   = new typename iss_t::DataResponse        [m_nb_dcache];
+                dreq_cached            = new bool                                [m_nb_dcache];
+                dreq_num_cpu           = new uint32_t                            [m_nb_dcache];
+
+                m_cpt_icache_access = new uint32_t [m_nb_icache];
+                m_cpt_dcache_access = new uint32_t [m_nb_dcache];
+
+               
+                m_cpt_fsm_dcache  = new uint32_t * [m_nb_dcache];
+                m_cpt_fsm_icache  = new uint32_t * [m_nb_icache];
+                for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+                    m_cpt_fsm_dcache[num_cache]  = new uint32_t [soclib::common::size(dcache_fsm_state_str )];
+                for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                    m_cpt_fsm_icache[num_cache]  = new uint32_t [soclib::common::size(icache_fsm_state_str )];
+                m_cpt_fsm_cmd     = new uint32_t [soclib::common::size(cmd_fsm_state_str    )];
+                m_cpt_fsm_rsp     = new uint32_t [soclib::common::size(rsp_fsm_state_str    )];
+                m_cpt_fsm_tgt     = new uint32_t [soclib::common::size(tgt_fsm_state_str    )];
+                m_cpt_fsm_cleanup = new uint32_t [soclib::common::size(cleanup_fsm_state_str)];
+
+                m_cpt_frz_cycles  = new uint32_t [m_nb_cpu];
+                // r_icache_fsm("r_icache_fsm"),
+                // r_icache_fsm_save("r_icache_fsm_save"),
+                // r_icache_addr_save("r_icache_addr_save"),
+                // r_icache_miss_req("r_icache_miss_req"),
+                // r_icache_miss_way("r_icache_miss_way"),
+                // r_icache_miss_set("r_icache_miss_set"),
+                // r_icache_unc_req("r_icache_unc_req"),
+                // r_icache_cleanup_req("r_icache_cleanup_req"),
+                // r_icache_cleanup_line("r_icache_cleanup_line"),
+                // r_icache_inval_rsp("r_icache_inval_rsp"),
+                // r_icache_update_addr("r_icache_update_addr"),
+                // r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
+
+                // r_dcache_fsm("r_dcache_fsm"),
+                // r_dcache_fsm_save("r_dcache_fsm_save"),
+                // r_dcache_addr_save("r_dcache_addr_save"),
+                // r_dcache_wdata_save("r_dcache_wdata_save"),
+                // r_dcache_rdata_save("r_dcache_rdata_save"),
+                // r_dcache_type_save("r_dcache_type_save"),
+                // r_dcache_be_save("r_dcache_be_save"),
+                // r_dcache_cached_save("r_dcache_cached_save"),
+                // r_dcache_cleanup_req("r_dcache_cleanup_req"),
+                // r_dcache_cleanup_line("r_dcache_cleanup_line"),
+                // r_dcache_miss_req("r_dcache_miss_req"),
+                // r_dcache_miss_way("r_dcache_miss_way"),
+                // r_dcache_miss_set("r_dcache_miss_set"),
+                // r_dcache_unc_req("r_dcache_unc_req"),
+                // r_dcache_sc_req("r_dcache_sc_req"),
+                // r_dcache_inval_rsp("r_dcache_inval_rsp"),
+                // r_dcache_update_addr("r_dcache_update_addr"),
+                // r_dcache_ll_data("r_dcache_ll_data"),
+                // r_dcache_ll_addr("r_dcache_ll_addr"),
+                // r_dcache_ll_valid("r_dcache_ll_valid"),
+                // r_dcache_previous_unc("r_dcache_previous_unc"),
+
+                // r_tgt_icache_req("r_tgt_icache_req"),
+                // r_tgt_icache_rsp("r_tgt_icache_rsp"),
+
+                // r_tgt_dcache_req("r_tgt_dcache_req"),
+                // r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
+
+                // r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+                // r_vci_rsp_data_error("r_vci_rsp_data_error"),
+
+                size_t _icache_ways  = icache_ways /m_nb_icache;
+                size_t _icache_sets  = icache_sets ;
+                size_t _dcache_ways  = dcache_ways /m_nb_dcache;
+                size_t _dcache_sets  = dcache_sets ;
+                size_t _icache_words = icache_words;
+                size_t _dcache_words = dcache_words;
+
+                size_t _wbuf_nwords  = wbuf_nwords ;
+                size_t _wbuf_nlines  = wbuf_nlines /m_nb_dcache;
+                size_t _wbuf_timeout = wbuf_timeout;
+
+
+                std::cout << "<VciCcXCacheWrapperV4> Parameters :" << std::endl;
+                std::cout << "  * nb_cpu             : " << nb_cpu << std::endl;
+                std::cout << "  * nb_cache           : " << m_nb_icache << " icache(s), " << m_nb_dcache << " dcache(s)" << std::endl;
+                std::cout << "  * icache (total)     : " <<  icache_ways << " way(s), " <<  icache_sets << " set(s), " <<  icache_words << " word(s)" << std::endl;
+                std::cout << "  * icache (per cache) : " << _icache_ways << " way(s), " << _icache_sets << " set(s), " << _icache_words << " word(s)" << std::endl;
+                std::cout << "  * dcache (total)     : " <<  dcache_ways << " way(s), " <<  dcache_sets << " set(s), " <<  dcache_words << " word(s)" << std::endl;
+                std::cout << "  * dcache (per cache) : " << _dcache_ways << " way(s), " << _dcache_sets << " set(s), " << _dcache_words << " word(s)" << std::endl;
+                std::cout << "  * wbuf   (total)     : " <<  wbuf_nlines << " line(s), " <<  wbuf_nwords << " word(s), timeout : " <<  wbuf_timeout << std::endl;
+                std::cout << "  * wbuf   (per cache) : " << _wbuf_nlines << " line(s), " << _wbuf_nwords << " word(s), timeout : " << _wbuf_timeout << std::endl;
+
+                r_icache = new GenericCache<vci_addr_t>  * [m_nb_icache];
+                r_dcache = new GenericCache<vci_addr_t>  * [m_nb_dcache];
+                r_wbuf   = new MultiWriteBuffer<addr_40> * [m_nb_dcache];
+
+               for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                {
+                    r_icache [num_cache] = new GenericCache<vci_addr_t>  ("icache", _icache_ways, _icache_sets, _icache_words);
+                }
+               for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+                {
+                    r_dcache [num_cache] = new GenericCache<vci_addr_t>  ("dcache", _dcache_ways, _dcache_sets, _dcache_words);
+                    r_wbuf   [num_cache] = new MultiWriteBuffer<addr_40> ("r_wbuf", _wbuf_nwords, _wbuf_nlines, _wbuf_timeout, _dcache_words);
+                }
+
+                m_num_cache_LSB_mask = 0;
+                for (uint32_t i=0; i<m_num_cache_LSB; ++i)
+                {
+                    m_num_cache_LSB_mask <<= 1;
+                    m_num_cache_LSB_mask  |= 1;
+                }
+                m_num_cache_mask = 0;
+                for (uint32_t i=0; i<(m_num_cache_MSB-m_num_cache_LSB); ++i)
+                {
+                    m_num_cache_mask <<= 1;
+                    m_num_cache_mask  |= 1;
+                }
 
                 SC_METHOD(transition);
@@ -316,5 +581,4 @@
                 dont_initialize();
                 sensitive << p_clk.neg();
-
 
                 typename iss_t::CacheInfo cache_info;
@@ -326,16 +590,47 @@
                 cache_info.dcache_assoc     = dcache_ways;
                 cache_info.dcache_n_lines   = dcache_sets;
-                m_iss.setCacheInfo(cache_info);
-
+
+                for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                    m_iss[num_cpu]->setCacheInfo(cache_info);
+                
 #if CC_XCACHE_WRAPPER_STOP_SIMULATION
                 m_stop_simulation               = false;
-                m_stop_simulation_nb_frz_cycles = 0;
+                m_stop_simulation_nb_frz_cycles = new uint32_t [m_nb_cpu];
+                for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                m_stop_simulation_nb_frz_cycles [num_cpu] = 0;
 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
 
-#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
-                std::ostringstream filename("");
-                filename << "Instruction_flow_" << proc_id << ".log";
-                
-                log_dcache_transaction_file.open(filename.str().c_str() ,std::ios::out | std::ios::trunc);
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                log_transaction_file_icache = new std::ofstream [m_nb_cpu];
+                log_transaction_file_dcache = new std::ofstream [m_nb_cpu];
+                for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                {
+                    {
+                        std::ostringstream filename("");
+                        filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_icache-" << proc_id << "_" << num_cpu << ".log";
+                        log_transaction_file_icache[num_cpu].open(filename.str().c_str() ,std::ios::out | std::ios::trunc);
+                    }
+                    {
+                        std::ostringstream filename("");
+                        filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_dcache-" << proc_id << "_" << num_cpu << ".log";
+                        log_transaction_file_dcache[num_cpu].open(filename.str().c_str() ,std::ios::out | std::ios::trunc);
+                    }
+                }
+
+                {
+                    std::ostringstream filename("");
+                    filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_cmd-" << proc_id << ".log";
+                    log_transaction_file_cmd.open(filename.str().c_str() ,std::ios::out | std::ios::trunc);
+                }
+                {
+                    std::ostringstream filename("");
+                    filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_tgt-" << proc_id << ".log";
+                    log_transaction_file_tgt.open(filename.str().c_str() ,std::ios::out | std::ios::trunc);
+                }
+                {
+                    std::ostringstream filename("");
+                    filename << CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH << "/Transaction_cleanup-" << proc_id << ".log";
+                    log_transaction_file_cleanup.open(filename.str().c_str() ,std::ios::out | std::ios::trunc);
+                }
 #endif
             } // end constructor
@@ -345,12 +640,127 @@
     ///////////////////////////////////
     {
-#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
-        log_dcache_transaction_file.close();
-#endif
-
+        delete [] m_stop_simulation_nb_frz_cycles;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+        for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+        {
+            log_transaction_file_dcache[num_cpu].close();
+            log_transaction_file_icache[num_cpu].close();
+        }
+        delete [] log_transaction_file_dcache;
+        delete [] log_transaction_file_icache;
+
+        log_transaction_file_cmd    .close();
+        log_transaction_file_tgt    .close();
+        log_transaction_file_cleanup.close();
+#endif
+
+        delete [] r_icache_lock         ;
+        delete [] r_dcache_lock         ;
+        delete [] r_dcache_sync         ;
+
+        delete [] r_icache_fsm          ;
+        delete [] r_icache_fsm_save     ;
+        delete [] r_icache_addr_save    ;
+        delete [] r_icache_miss_req     ;
+        delete [] r_icache_miss_way     ;
+        delete [] r_icache_miss_set     ;
+        delete [] r_icache_unc_req      ;
+        delete [] r_icache_cleanup_req  ;
+        delete [] r_icache_cleanup_line ;
+        delete [] r_icache_inval_rsp    ;
+        delete [] r_icache_update_addr  ;
+        delete [] r_icache_buf_unc_valid;
+
+        delete [] r_dcache_fsm          ;
+        delete [] r_dcache_fsm_save     ;
+        delete [] r_dcache_addr_save    ;
+        delete [] r_dcache_wdata_save   ;
+        delete [] r_dcache_rdata_save   ;
+        delete [] r_dcache_type_save    ;
+        delete [] r_dcache_be_save      ;
+        delete [] r_dcache_cached_save  ;
+        delete [] r_dcache_cleanup_req  ;
+        delete [] r_dcache_cleanup_line ;
+        delete [] r_dcache_miss_req     ;
+        delete [] r_dcache_miss_way     ;
+        delete [] r_dcache_miss_set     ;
+        delete [] r_dcache_unc_req      ;
+        delete [] r_dcache_sc_req       ;
+        delete [] r_dcache_inval_rsp    ;
+        delete [] r_dcache_update_addr  ;
+        delete [] r_dcache_previous_unc ;
+
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        {
+            delete [] r_dcache_ll_data    [num_cache];
+            delete [] r_dcache_ll_addr    [num_cache];
+            delete [] r_dcache_ll_valid   [num_cache];
+        }
+        delete [] r_dcache_num_cpu_save ;
+        delete [] r_dcache_ll_data      ;
+        delete [] r_dcache_ll_addr      ;
+        delete [] r_dcache_ll_valid     ;
+
+        delete [] r_tgt_icache_req      ;
+        delete [] r_tgt_icache_rsp      ;
+        delete [] r_tgt_dcache_req      ;
+        delete [] r_tgt_dcache_rsp      ;
+
+        delete [] r_tgt_be ;
         delete [] r_tgt_buf;
-        delete [] r_tgt_be ;
+
+        delete [] r_vci_rsp_ins_error   ;
+        delete [] r_vci_rsp_data_error  ;
+
+        delete [] ireq           ;
+        delete [] irsp           ;
+        delete [] ireq_cached    ;
+        delete [] ireq_num_cpu   ;
+        delete [] dreq           ;
+        delete [] drsp           ;
+        delete [] dreq_cached    ;
+        delete [] dreq_num_cpu   ;
+
+        delete [] m_cpt_frz_cycles;
+
+        delete [] m_cpt_icache_access   ;
+        delete [] m_cpt_dcache_access   ;
+
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        delete [] m_cpt_fsm_dcache [num_cache];
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+        delete [] m_cpt_fsm_icache [num_cache];
+        
+        delete [] m_cpt_fsm_dcache ;
+        delete [] m_cpt_fsm_icache ;
+        delete [] m_cpt_fsm_cmd    ;
+        delete [] m_cpt_fsm_rsp    ;
+        delete [] m_cpt_fsm_tgt    ;
+        delete [] m_cpt_fsm_cleanup;
+
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+        {
+            delete r_icache [num_cache];
+        }
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        {
+            delete r_wbuf   [num_cache];
+            delete r_dcache [num_cache];
+        }
+        delete [] r_wbuf;
+        delete [] r_icache;
+        delete [] r_dcache;
+
 
         CACHE_MISS_BUF_DEALLOC;
+
+        for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+        {
+            delete    m_iss [num_cpu];
+            delete [] p_irq [num_cpu];
+        }
+        delete [] m_iss;
+        delete [] p_irq;
     }
 
@@ -359,6 +769,7 @@
     ////////////////////////
     {
+        for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
         std::cout << "CPU " << m_srcid_rw << " : CPI = " 
-            << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+                  << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles[num_cpu]) << std::endl ;
     }
     ////////////////////////
@@ -366,12 +777,15 @@
     ////////////////////////
     {
-        float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
-
         uint32_t m_cpt_data_read_cached  = m_cpt_data_read-m_cpt_data_read_uncached;
         uint32_t m_cpt_data_write_cached = m_cpt_data_write-m_cpt_data_write_uncached;
         std::cout << "------------------------------------" << std:: dec << std::endl;
         std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
-        std::cout << "- CPI                            : " << (float)m_cpt_total_cycles/run_cycles << std::endl ;
-        std::cout << "- IPC                            : " << (float)run_cycles/m_cpt_total_cycles << std::endl ;
+        for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+        {
+            float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles[num_cpu]);
+
+            std::cout << "- CPI                            : [" << num_cpu << "] "<< (float)m_cpt_total_cycles/run_cycles << std::endl ;
+            std::cout << "- IPC                            : [" << num_cpu << "] "<< (float)run_cycles/m_cpt_total_cycles << std::endl ;
+        }
         std::cout << "- DATA READ *                    : " << m_cpt_data_read << std::endl ;
         std::cout << "  + Uncached                     : " << m_cpt_data_read_uncached << " (" << (float)m_cpt_data_read_uncached*100.0/(float)m_cpt_data_read << "%)" << std::endl ;
@@ -404,7 +818,54 @@
         std::cout << "  + DCACHE Only                  : " << (float)m_cpt_cc_inval_dcache   *100.0/(float)m_cpt_cc_inval << "%" << std::endl;
         std::cout << "  + BROADCAST                    : " << (float)m_cpt_cc_inval_broadcast*100.0/(float)m_cpt_cc_inval << "%" << std::endl;
+
+        uint32_t m_cpt_icache_access_all = 0;
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+            m_cpt_icache_access_all += m_cpt_icache_access [num_cache];
+
+        std::cout << "- ICACHE ACCESS                  : " << m_cpt_icache_access_all << std::endl;
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+            std::cout << "  + [" << num_cache << "] : " << m_cpt_icache_access [num_cache] << " (" << (float)m_cpt_icache_access [num_cache]*100.0/(float)m_cpt_icache_access_all << "%)" << std::endl;
+
+        uint32_t m_cpt_dcache_access_all = 0;
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            m_cpt_dcache_access_all += m_cpt_dcache_access [num_cache];
+
+        std::cout << "- DCACHE ACCESS                  : " << m_cpt_dcache_access_all << std::endl;
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            std::cout << "  + [" << num_cache << "] : " << m_cpt_dcache_access [num_cache] << " (" << (float)m_cpt_dcache_access [num_cache]*100.0/(float)m_cpt_dcache_access_all << "%)" << std::endl;
+
+        std::cout << "- DCACHE FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i)
+        {
+            std::cout << "  + "  << dcache_fsm_state_str[i] << " :\t ";
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+                std::cout << m_cpt_fsm_dcache [num_cache][i] << ", ";
+            std::cout << std::endl; 
+        }
+        std::cout << "- ICACHE FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i)
+        {
+            std::cout << "  + "  << icache_fsm_state_str[i] << " :\t ";
+            for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                std::cout << m_cpt_fsm_icache [num_cache][i] << ", ";
+            std::cout << std::endl; 
+        }
+        std::cout << "- CMD FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i)
+            std::cout << "  + " << cmd_fsm_state_str[i] << " :\t " << m_cpt_fsm_cmd [i] << std::endl;
+        std::cout << "- RSP FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i)
+            std::cout << "  + " << rsp_fsm_state_str[i] << " :\t " << m_cpt_fsm_rsp [i] << std::endl;
+        std::cout << "- TGT FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i)
+            std::cout << "  + "  << tgt_fsm_state_str[i] << " :\t " << m_cpt_fsm_tgt [i] << std::endl;
+        std::cout << "- CLEANUP FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str ); ++i)
+            std::cout << "  + "  << cleanup_fsm_state_str[i] << " :\t " << m_cpt_fsm_cleanup [i] << std::endl;
+
         std::cout << "* : accepted or not by the cache" << std::endl ;
 
-        r_wbuf.printStatistics();
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            r_wbuf[num_cache]->printStatistics();
     }
 
@@ -421,11 +882,18 @@
         typename iss_t::DataRequest         dreq;
 
-        m_iss.getRequests( ireq, dreq );
         std::cout << std::dec << "Proc \"" << name() << "\"" << std::endl;
-        std::cout << ireq << std::endl;
-        std::cout << dreq << std::endl;
-        std::cout << "  " << dcache_fsm_state_str[r_dcache_fsm]
-                  << "  " << icache_fsm_state_str[r_icache_fsm]
-                  << "  " << cmd_fsm_state_str[r_vci_cmd_fsm]
+
+        for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+        {
+            m_iss[num_cpu]->getRequests( ireq, dreq );
+            std::cout << ireq << std::endl;
+            std::cout << dreq << std::endl;
+        }
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+        std::cout << "  " << icache_fsm_state_str[r_icache_fsm[num_cache]] << std::endl;
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        std::cout << "  " << dcache_fsm_state_str[r_dcache_fsm[num_cache]] << std::endl;
+            
+        std::cout << "  " << cmd_fsm_state_str[r_vci_cmd_fsm]
                   << "  " << rsp_fsm_state_str[r_vci_rsp_fsm]
                   << "  " << tgt_fsm_state_str[r_vci_tgt_fsm]
@@ -434,27 +902,19 @@
         if(mode & 0x1)
         {
-            r_wbuf.printTrace((mode>>1)&1);
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+                r_wbuf[num_cache]->printTrace((mode>>1)&1);
         }
         if(mode & 0x4)
         {
             std::cout << "  Data cache" << std::endl;
-            r_dcache.printTrace();
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+                r_dcache[num_cache]->printTrace();
         }
         if(mode & 0x8)
         {
             std::cout << "  Instruction cache" << std::endl;
-            r_icache.printTrace();
+            for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                r_icache[num_cache]->printTrace();
         }
-
-        // if(mode & 0x10)
-        // {
-        //     std::cout << "  Icache miss buffer : ";
-        //     CACHE_MISS_BUF_RSP_PRINT(i);
-        //     std::cout << std::endl;
-
-        //     std::cout << "  Dcache miss buffer : ";
-        //     CACHE_MISS_BUF_RSP_PRINT(d);
-        //     std::cout << std::endl;
-        // }
     }
 
@@ -465,9 +925,24 @@
         if ( not p_resetn.read() ) {
 
-            m_iss.reset();
+            r_cpu_prior = 0;
+
+            for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                m_iss[num_cpu]->reset();
 
             // FSM states
-            r_dcache_fsm  = DCACHE_IDLE;
-            r_icache_fsm  = ICACHE_IDLE;
+            for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+            {
+                r_icache_fsm [num_cache] = ICACHE_IDLE;
+
+                r_icache_lock[num_cache] = m_nb_cpu;
+            }
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            {
+                r_dcache_fsm [num_cache] = DCACHE_IDLE;
+
+                r_dcache_lock[num_cache] = m_nb_cpu;
+                r_dcache_sync[num_cache] = false;
+            }
+
             r_vci_cmd_fsm = CMD_IDLE;
             r_vci_rsp_fsm = RSP_IDLE;
@@ -475,24 +950,53 @@
             r_cleanup_fsm = CLEANUP_IDLE;
 
+            for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+            {
             // write buffer & caches
-            r_wbuf.reset();
-            r_icache.reset();
-            r_dcache.reset();
+            r_icache[num_cache]->reset();
 
             // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI  FSMs
-            r_icache_miss_req    = false;
-            r_icache_unc_req     = false;
-            r_icache_cleanup_req = false;
-            r_dcache_miss_req    = false;
-            r_dcache_unc_req     = false;
-            r_dcache_sc_req      = false;
-            r_dcache_cleanup_req = false;
-            r_dcache_previous_unc= false;
+            r_icache_miss_req    [num_cache] = false;
+            r_icache_unc_req     [num_cache] = false;
+            r_icache_cleanup_req [num_cache] = false;
+
+            // internal messages in DCACHE et ICACHE FSMs
+            r_icache_inval_rsp   [num_cache] = false;
+
+            // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
+            r_icache_buf_unc_valid [num_cache] = false;
 
             // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
-            r_tgt_icache_req     = false;
-            r_tgt_dcache_req     = false;
-            r_tgt_icache_rsp     = false;
-            r_tgt_dcache_rsp     = false;
+            r_tgt_icache_req     [num_cache] = false;
+            r_tgt_icache_rsp     [num_cache] = false;
+
+            r_vci_rsp_ins_error  [num_cache] = false;
+            }// end for num_cache
+
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            {
+            // write buffer & caches
+            r_wbuf  [num_cache]->reset();
+            r_dcache[num_cache]->reset();
+
+            // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI  FSMs
+            r_dcache_miss_req    [num_cache] = false;
+            r_dcache_unc_req     [num_cache] = false;
+            r_dcache_sc_req      [num_cache] = false;
+            r_dcache_cleanup_req [num_cache] = false;
+            r_dcache_previous_unc[num_cache] = false;
+
+            // internal messages in DCACHE et ICACHE FSMs
+            r_dcache_inval_rsp   [num_cache] = false;
+
+            // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
+            for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                r_dcache_ll_valid      [num_cache][num_cpu] = false;
+
+            // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
+            r_tgt_dcache_req     [num_cache] = false;
+            r_tgt_dcache_rsp     [num_cache] = false;
+
+            r_vci_rsp_data_error [num_cache] = false;
+            }// end for num_cache
 
 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
@@ -500,17 +1004,5 @@
 #endif
 
-
-            // internal messages in DCACHE et ICACHE FSMs
-            r_icache_inval_rsp   = false;
-            r_dcache_inval_rsp   = false;
-
-            // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
-            r_dcache_ll_valid      = false;
-            r_icache_buf_unc_valid = false;
-
             r_vci_cmd_dcache_prior = false;
-
-            r_vci_rsp_data_error   = false;
-            r_vci_rsp_ins_error    = false;
 
             CACHE_MISS_BUF_RESET(i);
@@ -535,5 +1027,6 @@
             m_cpt_cc_update_dcache_word_useful = 0;
 
-            m_cpt_frz_cycles   = 0;
+            for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+            m_cpt_frz_cycles [num_cpu]  = 0;
             m_cpt_total_cycles = 0;
 
@@ -563,4 +1056,28 @@
             m_length_write_transaction = 0;
 
+            for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+            {
+                m_cpt_icache_access [num_cache] = 0;
+
+                for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i)
+                    m_cpt_fsm_icache  [num_cache][i] = 0;
+            }
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            {
+                m_cpt_dcache_access [num_cache] = 0;
+
+                for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i)
+                    m_cpt_fsm_dcache  [num_cache][i] = 0;
+            }
+
+            for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str    ); ++i)
+                m_cpt_fsm_cmd     [i] = 0;
+            for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str    ); ++i)
+                m_cpt_fsm_rsp     [i] = 0;
+            for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str    ); ++i)
+                m_cpt_fsm_tgt     [i] = 0;
+            for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str); ++i)
+                m_cpt_fsm_cleanup [i] = 0;
+
             return;
         }
@@ -569,22 +1086,43 @@
 
         PRINTF("--------------------------------------------\n");
-        PRINTF("  * CC_XCACHE_WRAPPER \"%s\" - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles);
-        PRINTF("    * fsm dcache          = %s\n",dcache_fsm_state_str[r_dcache_fsm]);
-        PRINTF("    * fsm icache          = %s\n",icache_fsm_state_str[r_icache_fsm]);
-        PRINTF("    * fsm cmd             = %s\n",cmd_fsm_state_str[r_vci_cmd_fsm]);
-        PRINTF("    * fsm rsp             = %s\n",rsp_fsm_state_str[r_vci_rsp_fsm]);
-        PRINTF("    * fsm tgt             = %s\n",tgt_fsm_state_str[r_vci_tgt_fsm]);
-        PRINTF("    * fsm cleanup         = %s\n",cleanup_fsm_state_str[r_cleanup_fsm]);
-        PRINTF("    * ll info             : %d %llx %llx\n",r_dcache_ll_valid.read(), (uint64_t)r_dcache_ll_addr.read(), (uint64_t)r_dcache_ll_data.read());
-        PRINTF("    * dcache_previous_unc : %d\n",r_dcache_previous_unc.read());
+        PRINTF("  * CC_XCACHE_WRAPPER \"%s\" Transition - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles);
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        PRINTF("    * fsm dcache              = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,dcache_fsm_state_str[r_dcache_fsm[num_cache]],r_dcache_lock[num_cache].read(),(uint64_t)r_dcache_addr_save[num_cache].read(),(uint64_t)set_num_dcache_only(r_dcache_addr_save[num_cache].read(),num_cache));
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+        PRINTF("    * fsm icache              = [%.2d] %s - (%.2d) %llx (%llx)\n",num_cache,icache_fsm_state_str[r_icache_fsm[num_cache]],r_icache_lock[num_cache].read(),(uint64_t)r_icache_addr_save[num_cache].read(),(uint64_t)set_num_icache_only(r_icache_addr_save[num_cache].read(),num_cache));
+        PRINTF("    * fsm cmd                 = (%.2d) %s\n",r_vci_cmd_num_cache.read(), cmd_fsm_state_str[r_vci_cmd_fsm]);
+        PRINTF("    * fsm rsp                 = (%.2d) %s\n",r_vci_rsp_num_cache.read(), rsp_fsm_state_str[r_vci_rsp_fsm]);
+        PRINTF("    * fsm tgt                 = (%.2d) %s - i %llx d %llx\n",r_tgt_num_cache.read(), tgt_fsm_state_str[r_vci_tgt_fsm],(uint64_t)r_tgt_iaddr.read(),(uint64_t)r_tgt_daddr.read());
+      //PRINTF("    * fsm tgt                 =      %s - %llx\n",tgt_fsm_state_str[r_vci_tgt_fsm],(uint64_t)r_tgt_addr.read());
+        PRINTF("    * fsm cleanup             = (%.2d) %s\n",r_cleanup_num_cache.read(), cleanup_fsm_state_str[r_cleanup_fsm]);
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        {
+            for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+                PRINTF("    * ll info                 : [%.2d][%.2d] %d %llx (%llx) %llx\n"
+                       ,num_cache
+                       ,num_cpu
+                       ,          r_dcache_ll_valid [num_cache][num_cpu].read()
+                       ,(uint64_t)r_dcache_ll_addr  [num_cache][num_cpu].read()
+                       ,(uint64_t)set_num_dcache_only(r_dcache_ll_addr [num_cache][num_cpu].read(),num_cache)
+                       ,(uint64_t)r_dcache_ll_data [num_cache][num_cpu].read());
+
+            PRINTF("    * dcache_previous_unc     : [%.2d] %d\n",num_cache,r_dcache_previous_unc[num_cache].read());
+
+#if CC_XCACHE_WRAPPER_DEBUG
+            if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
+                r_wbuf[num_cache]->printTrace(1);
+#endif
+        }
         // CACHE_MISS_BUF_RSP_PRINT(i);
         // CACHE_MISS_BUF_RSP_PRINT(d);
 
-#if CC_XCACHE_WRAPPER_DEBUG
-        if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
-            {
-                r_wbuf.printTrace(1);
-            }
-#endif
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        m_cpt_fsm_dcache  [num_cache][r_dcache_fsm[num_cache]] ++;
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+        m_cpt_fsm_icache  [num_cache][r_icache_fsm[num_cache]] ++;
+        m_cpt_fsm_cmd     [r_vci_cmd_fsm] ++;
+        m_cpt_fsm_rsp     [r_vci_rsp_fsm] ++;
+        m_cpt_fsm_tgt     [r_vci_tgt_fsm] ++;
+        m_cpt_fsm_cleanup [r_cleanup_fsm] ++;
 
         m_cpt_total_cycles++;
@@ -626,5 +1164,5 @@
                 if ( p_vci_tgt.cmdval.read() ) 
                 {
-                    PRINTF("    * <TGT> request\n");
+                    PRINTF("    * <TGT> Request\n");
 
                     addr_40 address = p_vci_tgt.address.read();
@@ -634,5 +1172,5 @@
                         std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
                         std::cout << "coherence request is not a write" << std::endl;
-                        std::cout << "oddress = " << std::hex << address << std::dec << std::endl;
+                        std::cout << "address = " << std::hex << address << std::dec << std::endl;
                         std::cout << "srcid   = " << p_vci_tgt.srcid.read() << std::endl;
                         exit(0);
@@ -644,20 +1182,26 @@
                         std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
                         std::cout << "out of segment coherence request" << std::endl;
-                        std::cout << "oddress = " << std::hex << address << std::dec << std::endl;
+                        std::cout << "address = " << std::hex << address << std::dec << std::endl;
                         std::cout << "srcid   = " << p_vci_tgt.srcid.read() << std::endl;
                         exit(0);
                     }
 
-                    r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 
-                                 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4;      
-                    r_tgt_srcid = p_vci_tgt.srcid.read();
-                    r_tgt_trdid = p_vci_tgt.trdid.read();
-                    r_tgt_pktid = p_vci_tgt.pktid.read();
-                 // r_tgt_plen  = p_vci_tgt.plen.read();
+                    addr_40 tgt_addr  = ((((addr_40)p_vci_tgt.be.read() & 0x3) << 32) | ((addr_40) p_vci_tgt.wdata.read())) << (addr_40)m_dcache_words_shift;
+                    // * m_dcache_words * 4;
+
+                    addr_40 tgt_iaddr = tgt_addr;
+                    addr_40 tgt_daddr = tgt_addr;
+
+                    PRINTF("    * <TGT> srcid            : %d\n",(uint32_t)p_vci_tgt.srcid.read());
+                    PRINTF("    * <TGT> trdid            : %d\n",(uint32_t)p_vci_tgt.trdid.read());
+                    PRINTF("    * <TGT> pktid            : %d\n",(uint32_t)p_vci_tgt.pktid.read());
+                    PRINTF("    * <TGT> address (before) : %llx\n",(uint64_t)tgt_iaddr);
+
+                    r_tgt_srcid     = p_vci_tgt.srcid.read();
+                    r_tgt_trdid     = p_vci_tgt.trdid.read();
+                    r_tgt_pktid     = p_vci_tgt.pktid.read();
+                 // r_tgt_plen      = p_vci_tgt.plen.read();
                     
-                    PRINTF("    * <TGT> address : %llx\n",(uint64_t)address);
-                    PRINTF("    * <TGT> address : %llx\n",(uint64_t)((((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 
-                                                                      ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4));
-
+                    // BROADCAST
                     if ( (address&0x3) == 0x3 )   // broadcast invalidate for data or instruction type
                     {
@@ -671,5 +1215,27 @@
                         // r_tgt_brdcast= true;
                         r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                        uint32_t tgt_num_cache;
+                        tgt_num_cache = get_num_icache(tgt_iaddr,0); // none effect (else CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+                        tgt_num_cache = get_num_dcache(tgt_daddr);
+                        r_tgt_num_cache = tgt_num_cache;
+
+                        PRINTF("    * <TGT> REQ_BROADCAST\n");
+                        PRINTF("    * <TGT> num_cache (data) : %d\n",tgt_num_cache);
+
                         m_cpt_cc_inval_broadcast++ ;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                        {
+                            log_transaction_file_tgt
+                                << "[" << m_cpt_total_cycles << "] "
+                                << "BROADCAST  "
+                                << std::hex
+                                << " L " << std::setw(10) << (uint64_t)tgt_addr
+                                << std::dec
+                                << " - " << tgt_num_cache
+                                << std::endl;
+                        }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
                     }
                     else                    // multi-update or multi-invalidate for data type
@@ -677,4 +1243,5 @@
                         uint32_t cell = address - m_segment.baseAddress(); // addr_40
                         // r_tgt_brdcast = false;
+
                         if (cell == 0) 
                         {                                       // invalidate data
@@ -687,5 +1254,25 @@
                             r_tgt_update = false; 
                             r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                            uint32_t tgt_num_cache = get_num_dcache(tgt_daddr); // static partionnement
+                            r_tgt_num_cache = tgt_num_cache;
+                            
+                            PRINTF("    * <TGT> REQ_DCACHE\n");
+                            PRINTF("    * <TGT> num_cache        : %d\n",tgt_num_cache);
+
                             m_cpt_cc_inval_dcache++ ;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                            {
+                                log_transaction_file_tgt
+                                    << "[" << m_cpt_total_cycles << "] "
+                                    << "INVAL DATA "
+                                    << std::hex
+                                    << " L " << std::setw(10) << (uint64_t)tgt_addr
+                                    << std::dec 
+                                    << " - " << tgt_num_cache
+                                    << std::endl;
+                            }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
                         } 
                         else if (cell == 4)                     // invalidate instruction
@@ -699,5 +1286,26 @@
                             r_tgt_update = false; 
                             r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                            uint32_t tgt_num_cpu   = p_vci_tgt.pktid.read();
+                            uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu);
+                            r_tgt_num_cache = tgt_num_cache;
+                            
+                            PRINTF("    * <TGT> REQ_ICACHE\n");
+                            PRINTF("    * <TGT> num_cache        : %d\n",tgt_num_cache);
+
                             m_cpt_cc_inval_icache++ ;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                            {
+                                log_transaction_file_tgt
+                                    << "[" << m_cpt_total_cycles << "] "
+                                    << "INVAL INS  "
+                                    << std::hex
+                                    << " L " << std::setw(10) << (uint64_t)tgt_addr
+                                    << std::dec
+                                    << " - " << tgt_num_cache
+                                    << std::endl;
+                            }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
                         } 
                         else if ( (cell == 8) or (cell==12) )    // update data or instruction
@@ -713,4 +1321,23 @@
                                 m_cpt_cc_update_dcache++;
                                 r_tgt_update_data = true;
+
+                                uint32_t tgt_num_cache = get_num_dcache(tgt_daddr);
+                                r_tgt_num_cache = tgt_num_cache;
+                                
+                                PRINTF("    * <TGT> UPDT_WORD DATA\n");
+                                PRINTF("    * <TGT> num_cache        : %d\n",tgt_num_cache);
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_tgt
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "UPT DATA   "
+                                        << std::hex
+                                        << " L " << std::setw(10) << (uint64_t)tgt_addr
+                                        << std::dec
+                                        << " - " << tgt_num_cache
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                             }
                             else
@@ -718,4 +1345,24 @@
                                 m_cpt_cc_update_icache++;
                                 r_tgt_update_data = false;
+
+                                uint32_t tgt_num_cpu   = p_vci_tgt.pktid.read();
+                                uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu);
+                                r_tgt_num_cache = tgt_num_cache;
+                                
+                                PRINTF("    * <TGT> UPDT_WORD INSTRUCTION\n");
+                                PRINTF("    * <TGT> num_cache        : %d\n",tgt_num_cache);
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_tgt
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "UPT INS    "
+                                        << std::hex
+                                        << " L " << std::setw(10) << (uint64_t)tgt_addr
+                                        << std::dec
+                                        << " - " << tgt_num_cache
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                             }
                             r_tgt_update = true; 
@@ -724,4 +1371,9 @@
 
                     } // end if address
+                    
+                    r_tgt_iaddr      = tgt_iaddr;
+                    r_tgt_daddr      = tgt_daddr;
+                    PRINTF("    * <TGT> address (after)  : i %llx, d %llx\n",(uint64_t)tgt_iaddr,(uint64_t)tgt_daddr);
+
                 } // end if cmdval
                 break;
@@ -739,5 +1391,5 @@
                     r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
 #ifdef COHERENCE_DEBUG
-                    std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_addr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl;
+                    std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_daddr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl;
 #endif
                     r_vci_tgt_fsm = TGT_UPDT_DATA;
@@ -789,9 +1441,27 @@
 
             case TGT_REQ_BROADCAST:
-                if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 
-                {
-                    r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
-                    r_tgt_icache_req = true;
-                    r_tgt_dcache_req = true;
+                {
+                    bool tgt_icache_req;
+
+#if   (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+                    tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read();
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+                    tgt_icache_req = false;
+                    for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                        tgt_icache_req |= r_tgt_icache_req[num_cache].read();
+#endif
+                    if (not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 
+                    {
+                        r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+
+#if   (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+                        r_tgt_icache_req[r_tgt_num_cache] = true;
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+                        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                        r_tgt_icache_req[      num_cache] = true;
+#endif
+
+                        r_tgt_dcache_req[r_tgt_num_cache] = true;
+                    }
                 }
                 break;
@@ -799,8 +1469,9 @@
             case TGT_REQ_ICACHE:
                 {
-                    if ( not r_tgt_icache_req.read() ) 
+                    // Request treated by the icache
+                    if ( not r_tgt_icache_req[r_tgt_num_cache].read() ) 
                     {
                         r_vci_tgt_fsm = TGT_RSP_ICACHE; 
-                        r_tgt_icache_req = true;
+                        r_tgt_icache_req[r_tgt_num_cache] = true;
                     }
                     break;
@@ -808,63 +1479,252 @@
 
             case TGT_REQ_DCACHE:
-                if ( not r_tgt_dcache_req.read() ) 
-                {
-                    r_vci_tgt_fsm = TGT_RSP_DCACHE; 
-                    r_tgt_dcache_req = true;
-                }
-                break;
-
+                {
+                    // Request treated by the dcache
+
+                    if ( not r_tgt_dcache_req[r_tgt_num_cache].read() ) 
+                    {
+                        r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+                        r_tgt_dcache_req[r_tgt_num_cache] = true;
+                    }
+                    break;
+                }
             case TGT_RSP_BROADCAST:
-                if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 
-                {
-                    // one response
-                    if ( not r_tgt_icache_rsp or not r_tgt_dcache_rsp )
+                {
+                    PRINTF("      * <TGT> dcache[%d] : %d - %d\n",(uint32_t)r_tgt_num_cache, (uint32_t)r_tgt_dcache_req[r_tgt_num_cache].read(),(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read());
+                    for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                        PRINTF("      * <TGT> icache[%d] : %d - %d\n",(uint32_t)num_cache, (uint32_t)r_tgt_icache_req[num_cache].read(),(uint32_t)r_tgt_icache_rsp[num_cache].read());
+
+                    bool tgt_icache_req;
+                    
+#if   (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+                    tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read();
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+                    tgt_icache_req = false;
+                    for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                        tgt_icache_req |= r_tgt_icache_req[num_cache].read();
+#endif
+                    if (not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 
                     {
-                        if ( p_vci_tgt.rspack.read() )
+                        bool     tgt_icache_rsp;
+                        uint32_t tgt_icache_rsp_num_cache;
+                        
+#if   (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+                        tgt_icache_rsp_num_cache = r_tgt_num_cache;
+                        tgt_icache_rsp = r_tgt_icache_rsp[r_tgt_num_cache].read();
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+                        tgt_icache_rsp_num_cache = 0;
+                        for (;tgt_icache_rsp_num_cache<m_nb_icache; ++tgt_icache_rsp_num_cache)
                         {
-                            r_vci_tgt_fsm = TGT_IDLE; 
-                            r_tgt_icache_rsp = false;
-                            r_tgt_dcache_rsp = false;
+                            PRINTF("      * <TGT> icache[%d] : %d\n",(uint32_t)tgt_icache_rsp_num_cache, (uint32_t)r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read());
+                            
+                            if (r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read())
+                                break;
                         }
-                    }
-
-                    // if data and instruction have the inval line, need two responses  
-                    if ( r_tgt_icache_rsp and r_tgt_dcache_rsp )
-                    {
-                        if ( p_vci_tgt.rspack.read() )
+
+                        tgt_icache_rsp = (tgt_icache_rsp_num_cache<m_nb_icache);
+#endif
+
+                        PRINTF("      * <TGT> icache_rsp [%d] : %d\n",tgt_icache_rsp_num_cache,(uint32_t) tgt_icache_rsp);
+                        PRINTF("      * <TGT> dcache_rsp [%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t) r_tgt_dcache_rsp[r_tgt_num_cache]);
+
+                        if (tgt_icache_rsp or r_tgt_dcache_rsp[r_tgt_num_cache])
                         {
-                            r_tgt_icache_rsp = false; // only reset one for respond the second time 
+                            // Have send one response
+                            if ( p_vci_tgt.rspack.read())
+                            {
+                                // reset dcache if activated
+                                if (r_tgt_dcache_rsp[r_tgt_num_cache])
+                                    r_tgt_dcache_rsp[r_tgt_num_cache] = false;
+                                else
+                                    // reset one icache
+                                    r_tgt_icache_rsp[tgt_icache_rsp_num_cache] = false;
+                            }
                         }
-                    }
-
-                    // if there is no need for a response
-                    if ( not r_tgt_icache_rsp and not r_tgt_dcache_rsp )
+
+                        // // one response
+                        // if ( not r_tgt_icache_rsp[r_tgt_num_cache] or not r_tgt_dcache_rsp[r_tgt_num_cache] )
+                        // {
+                        //     if ( p_vci_tgt.rspack.read() )
+                        //     {
+                        //         r_vci_tgt_fsm = TGT_IDLE; 
+                        //         r_tgt_icache_rsp[r_tgt_num_cache] = false;
+                        //         r_tgt_dcache_rsp[r_tgt_num_cache] = false;
+                        //     }
+                        // }
+                        
+                        // // if data and instruction have the inval line, need two responses  
+                        // if ( r_tgt_icache_rsp[r_tgt_num_cache] and r_tgt_dcache_rsp[r_tgt_num_cache] )
+                        // {
+                        //     if ( p_vci_tgt.rspack.read() )
+                        //     {
+                        //         r_tgt_icache_rsp[r_tgt_num_cache] = false; // only reset one for respond the second time 
+                        //     }
+                        // }
+
+                        PRINTF("      * <TGT> icache_rsp    : %d\n",(uint32_t) r_tgt_icache_rsp);
+                        PRINTF("      * <TGT> dcache_rsp[%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read());
+                        // if there is no need for a response
+                        if (not tgt_icache_rsp and not r_tgt_dcache_rsp[r_tgt_num_cache] )
+                        {
+                            r_vci_tgt_fsm = TGT_IDLE;
+                        }
+                        
+                    }
+                    break;
+                }
+                ////////////////////
+            case TGT_RSP_ICACHE:
+                {
+                    bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp[r_tgt_num_cache].read()) and not r_tgt_icache_req[r_tgt_num_cache].read();
+
+                    PRINTF("      * <TGT> RSP_ICACHE : transaction : %d ((%d or not %d) and not %d)\n",transaction_rsp
+                           ,(int)p_vci_tgt.rspack.read()
+                           ,(int)r_tgt_icache_rsp[r_tgt_num_cache].read()
+                           ,(int)r_tgt_icache_req[r_tgt_num_cache].read()
+                           );
+
+                    if (transaction_rsp) 
                     {
                         r_vci_tgt_fsm = TGT_IDLE;
-                    }
-
-                }
-                break;
-                ////////////////////
-            case TGT_RSP_ICACHE:
-                {
-                    if ( (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp.read()) and not r_tgt_icache_req.read() ) 
+                        r_tgt_icache_rsp[r_tgt_num_cache] = false; 
+                    }
+                    break;
+                }
+
+            case TGT_RSP_DCACHE:
+                {
+                    bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp[r_tgt_num_cache].read()) and not r_tgt_dcache_req[r_tgt_num_cache].read();
+
+                    PRINTF("      * <TGT> RSP_DCACHE : transaction : %d\n",transaction_rsp);
+
+                    if (transaction_rsp) 
                     {
                         r_vci_tgt_fsm = TGT_IDLE;
-                        r_tgt_icache_rsp = false; 
+                        r_tgt_dcache_rsp[r_tgt_num_cache] = false; 
                     }
                     break;
                 }
-
-            case TGT_RSP_DCACHE:
-                {
-                    if ( (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp.read()) and not r_tgt_dcache_req.read() ) 
-                    {
-                        r_vci_tgt_fsm = TGT_IDLE;
-                        r_tgt_dcache_rsp = false; 
-                    }
-                    break;
-                }
         } // end switch TGT_FSM
+
+        /////////////////////////////////////////////////////////////////////
+        // Interface between CPU and CACHE FSM
+        ///////////////////////////////////////////////////////////////////////
+
+        uint32_t ireq_num_cache [m_nb_cpu];
+        uint32_t dreq_num_cache [m_nb_cpu];
+        bool     have_sync = false;
+
+        {
+            typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER;
+            typename iss_t::DataRequest        _dreq = ISS_DREQ_INITIALIZER;
+
+            for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+            {
+                ireq [num_cache] = _ireq;
+              //irsp [num_cache] = _irsp;
+            }
+            for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+            {
+                dreq [num_cache] = _dreq;
+              //drsp [num_cache] = _drsp;
+                
+                have_sync |= r_dcache_sync [num_cache];
+            }
+        }
+
+        for (uint32_t _num_cpu=0; _num_cpu<m_nb_cpu; ++_num_cpu)
+        {
+            // round robin priority
+            uint32_t num_cpu = (r_cpu_prior+_num_cpu)%m_nb_cpu;
+
+            typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER;
+            typename iss_t::DataRequest        _dreq = ISS_DREQ_INITIALIZER;
+            
+            m_iss[num_cpu]->getRequests(_ireq, _dreq);
+
+            addr_40  addr;
+            uint32_t num_cache;
+
+            addr      = (addr_40)_ireq.addr;
+            num_cache = get_num_icache(addr,num_cpu);
+
+            // test if already used
+            if (not ireq[num_cache].valid and
+                (r_icache_lock [num_cache] == m_nb_cpu) or
+                (r_icache_lock [num_cache] == num_cpu))
+            {
+                bool valid = _ireq.valid;
+
+                if (valid)
+                {
+                    PRINTF("    * <CPU2CACHE> ICACHE :    Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache);
+                    ireq_num_cache [num_cpu  ] = num_cache;
+                    r_icache_lock [num_cache] = num_cpu;
+                }
+                else
+                {
+                    PRINTF("    * <CPU2CACHE> ICACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache);
+                    ireq_num_cache [num_cpu] = m_nb_icache;
+                }
+
+                ireq_cached    [num_cache] = m_cacheability_table[(vci_addr_t)_ireq.addr];
+                ireq_num_cpu   [num_cache] = num_cpu;
+                ireq           [num_cache] = _ireq;
+                ireq           [num_cache].addr = addr;
+            }
+            else
+            {
+                PRINTF("    * <CPU2CACHE> ICACHE : No transaction (cpu %d)\n",num_cpu);
+
+                ireq_num_cache [num_cpu] = m_nb_icache;
+            }
+
+            addr      = (addr_40)_dreq.addr;
+            num_cache = get_num_dcache(addr);
+
+            // test if already used
+            if (not dreq[num_cache].valid and
+                not have_sync and
+                (r_dcache_lock [num_cache] == m_nb_cpu) or
+                (r_dcache_lock [num_cache] == num_cpu))
+            {
+                bool valid = _dreq.valid;
+
+                if (valid)
+                {
+                    PRINTF("    * <CPU2CACHE> DCACHE :    Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache);
+                    dreq_num_cache [num_cpu  ] = num_cache;
+                    r_dcache_lock [num_cache] = num_cpu;
+                }
+                else
+                {
+                    PRINTF("    * <CPU2CACHE> DCACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache);
+                    dreq_num_cache [num_cpu] = m_nb_dcache;
+                }
+
+                dreq_cached    [num_cache] = m_cacheability_table[(vci_addr_t)_dreq.addr];
+                dreq_num_cpu   [num_cache] = num_cpu;
+                dreq           [num_cache] = _dreq;
+                dreq           [num_cache].addr = addr;
+            }
+            else
+            {
+                PRINTF("    * <CPU2CACHE> DCACHE : No transaction (cpu %d)\n",num_cpu);
+
+                dreq_num_cache [num_cpu] = m_nb_dcache;
+            }
+
+
+#if CC_XCACHE_WRAPPER_DEBUG
+        if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
+        {
+            std::cout << "    * <CPU2CACHE> Instruction Request   : " << ireq_num_cache[num_cpu] << " - " << _ireq << std::endl
+                      << "    * <CPU2CACHE> Data        Request   : " << dreq_num_cache[num_cpu] << " - " << _dreq << std::endl;
+        }
+#endif
+        }
+
+        // round robin priority
+        r_cpu_prior = (r_cpu_prior+1)%m_nb_cpu;
 
         /////////////////////////////////////////////////////////////////////
@@ -899,75 +1759,85 @@
         //    flip-flop. It is reset by the ICACHE FSM.
         ///////////////////////////////////////////////////////////////////////
-
-        typename iss_t::InstructionRequest  ireq = ISS_IREQ_INITIALIZER;
-        typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
-
-        typename iss_t::DataRequest         dreq = ISS_DREQ_INITIALIZER;
-        typename iss_t::DataResponse        drsp = ISS_DRSP_INITIALIZER;
-
-        m_iss.getRequests( ireq, dreq );
-
-#if CC_XCACHE_WRAPPER_DEBUG
-        if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
-            std::cout << "    * Instruction Request  : " << ireq << std::endl;
-#endif
-
-        switch(r_icache_fsm) {
+        
+        for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+        {
+            typename iss_t::InstructionRequest  _ireq = ireq [num_cache];
+            typename iss_t::InstructionResponse _irsp = ISS_IRSP_INITIALIZER;
+
+        switch(r_icache_fsm[num_cache]) {
             /////////////////
             case ICACHE_IDLE:
                 {
-                    if ( r_tgt_icache_req ) {   // external request
-                        if ( ireq.valid ) m_cost_ins_miss_frz++;
-                        r_icache_fsm = ICACHE_CC_CHECK;
-                        r_icache_fsm_save = r_icache_fsm.read();
+                    if ( r_tgt_icache_req[num_cache] ) {   // external request
+                        // if ( _ireq.valid ) m_cost_ins_miss_frz++;
+                        r_icache_fsm     [num_cache] = ICACHE_CC_CHECK;
+                        r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache];
                         break;
                     } 
-                    if ( ireq.valid ) {
-                        data_t  icache_ins = 0;
-                        bool    icache_hit = false;
-                        bool    icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr];
-                        bool    icache_cleanup_hit = r_icache_cleanup_req and (((addr_40)ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line.read());
+                    if ( _ireq.valid ) {
+                        data_t   icache_ins         = 0;
+                        bool     icache_hit         = false;
+                        bool     icache_cached      = ireq_cached  [num_cache];
+                        // uint32_t icache_num_cpu     = ireq_num_cpu [num_cache];
+                        bool     icache_cleanup_hit = r_icache_cleanup_req[num_cache] and (((addr_40)_ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line[num_cache].read());
 
                         // icache_hit & icache_ins evaluation
                         if ( icache_cached ) {
-                            icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins);
+                            icache_hit = r_icache[num_cache]->read((vci_addr_t) _ireq.addr, &icache_ins);
                         } else {
                             // if uncache, again in the icache_miss_buf
-                            icache_hit = ( r_icache_buf_unc_valid and ((addr_40) ireq.addr == (addr_40)r_icache_addr_save));
-                            icache_ins = CACHE_MISS_BUF_RSP_DATA(i,0);
-                            CACHE_MISS_BUF_RSP_POP(i);
+                            icache_hit = (r_icache_buf_unc_valid[num_cache] and ((addr_40) _ireq.addr == (addr_40)r_icache_addr_save[num_cache]));
+                            icache_ins = CACHE_MISS_BUF_RSP_DATA(i,num_cache,0);
+
+                            if (icache_hit)
+                                CACHE_MISS_BUF_RSP_POP(i,num_cache);
                         }
 
-                        PRINTF("    * <ICACHE> hit %d - cached %d - cleanup_hit %d\n",icache_hit, icache_cached, icache_cleanup_hit);
-
-                        ASSERT( not (icache_hit and icache_cleanup_hit),
-                                "Icache hit and icache_cleanup_hit");
-
-                        if ( not icache_hit and not icache_cleanup_hit) {
-                            m_cpt_ins_miss++;
-                            m_cost_ins_miss_frz++;
-                            r_icache_addr_save = (addr_40) ireq.addr;
-
-                            CACHE_MISS_BUF_REQ_INIT(i);
-
-                            if ( icache_cached ) {
+                        PRINTF("    * <ICACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache, icache_hit, icache_cached, icache_cleanup_hit);
+
+                        // ASSERT( not (icache_hit and icache_cleanup_hit),
+                        //         "Icache hit and icache_cleanup_hit");
+
+                        if (icache_hit and icache_cleanup_hit)
+                        {
+                            PRINTF("    * <ICACHE [%d]> Warning : icache hit and icache_cleanup_hit\n",num_cache);
+                            icache_hit = false;
+                        }
+                        else
+                        {
+                            if ( not icache_hit and not icache_cleanup_hit) 
+                            {
+                                m_cpt_ins_miss++;
+                                m_cost_ins_miss_frz++;
+                                r_icache_addr_save[num_cache] = (addr_40) _ireq.addr;
+                                
+                                CACHE_MISS_BUF_REQ_INIT(i,num_cache);
+                                
+                                if ( icache_cached )
+                                {
 #if CC_XCACHE_WRAPPER_SELECT_VICTIM
-                                r_icache_fsm = ICACHE_MISS_VICTIM;
+                                    r_icache_fsm     [num_cache] = ICACHE_MISS_VICTIM;
 #else
-                                r_icache_fsm = ICACHE_MISS_WAIT;
-#endif
-                                r_icache_miss_req = true;
-                               
-                            } else {
-                                r_icache_fsm = ICACHE_UNC_WAIT;
-                                r_icache_unc_req = true;
+                                    r_icache_fsm     [num_cache] = ICACHE_MISS_WAIT;
+#endif
+                                    r_icache_miss_req[num_cache] = true;
+                                    
+                                }
+                                else
+                                {
+                                    r_icache_fsm    [num_cache] = ICACHE_UNC_WAIT;
+                                    r_icache_unc_req[num_cache] = true;
+                                }
                             }
-                        } else {
-                            r_icache_buf_unc_valid = false;
+                            else
+                            {
+                                r_icache_buf_unc_valid[num_cache] = false;
+                            }
+                            m_cpt_icache_dir_read += m_icache_ways;
+                            m_cpt_icache_data_read += m_icache_ways;
                         }
-                        m_cpt_icache_dir_read += m_icache_ways;
-                        m_cpt_icache_data_read += m_icache_ways;
-                        irsp.valid          = icache_hit;
-                        irsp.instruction    = icache_ins;
+
+                        _irsp.valid          = icache_hit;
+                        _irsp.instruction    = icache_ins;
                     }
                     break;
@@ -977,17 +1847,17 @@
             case ICACHE_MISS_VICTIM:
                 {
-                    if (not r_icache_cleanup_req)
+                    if (not r_icache_cleanup_req[num_cache])
                     {
                         size_t     way;
                         size_t     set;
-                        vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read();
+                        vci_addr_t addr = (vci_addr_t) r_icache_addr_save[num_cache].read();
                         vci_addr_t victim;
                         
-                        r_icache_cleanup_req  = r_icache.victim_select(addr, &victim, &way, &set );
-                        r_icache_cleanup_line = (addr_40) victim;
-                        r_icache_miss_way     = way;
-                        r_icache_miss_set     = set;
+                        r_icache_cleanup_req [num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set );
+                        r_icache_cleanup_line[num_cache] = (addr_40) victim;
+                        r_icache_miss_way    [num_cache] = way;
+                        r_icache_miss_set    [num_cache] = set;
                         
-                        r_icache_fsm = ICACHE_MISS_WAIT;
+                        r_icache_fsm         [num_cache] = ICACHE_MISS_WAIT;
                     }
                     break;
@@ -998,45 +1868,32 @@
                 {
                     m_cost_ins_miss_frz++;
-                    if ( r_tgt_icache_req ) {   // external request
-                        r_icache_fsm = ICACHE_CC_CHECK;
-                        r_icache_fsm_save = r_icache_fsm.read();
+                    if ( r_tgt_icache_req[num_cache] ) {   // external request
+                        r_icache_fsm      [num_cache] = ICACHE_CC_CHECK;
+                        r_icache_fsm_save [num_cache] = r_icache_fsm[num_cache].read();
                         break;
                     }
 
-                    bool val = CACHE_MISS_BUF_RSP_VAL(i,0);
-
-                    PRINTF("    * <ICACHE> val                  : %d\n",val);
+                    bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0);
+
+                    PRINTF("    * <ICACHE [%d]> val                  : %d\n",num_cache,val);
 
                     if (val)
                     {
-                        PRINTF("    * <ICACHE> r_icache_inval_rsp   : %d\n",(int) r_icache_inval_rsp  );
-                        PRINTF("    * <ICACHE> r_vci_rsp_ins_error  : %d\n",(int) r_vci_rsp_ins_error );
-                        PRINTF("    * <ICACHE> r_icache_cleanup_req : %d\n",(int) r_icache_cleanup_req);
-
-                        // if (not r_icache_inval_rsp )
-                        // {
-                            // Miss read response and no invalidation
-                            if ( r_vci_rsp_ins_error ) {
-                                r_icache_fsm = ICACHE_ERROR;
-                            } else {
+                        PRINTF("    * <ICACHE [%d]> r_icache_inval_rsp   : %d\n",num_cache,(int) r_icache_inval_rsp  [num_cache]);
+                        PRINTF("    * <ICACHE [%d]> r_vci_rsp_ins_error  : %d\n",num_cache,(int) r_vci_rsp_ins_error [num_cache]);
+                        PRINTF("    * <ICACHE [%d]> r_icache_cleanup_req : %d\n",num_cache,(int) r_icache_cleanup_req[num_cache]);
+
+                        // Miss read response and no invalidation
+                        if ( r_vci_rsp_ins_error [num_cache]) {
+                            r_icache_fsm[num_cache] = ICACHE_ERROR;
+                        } else {
 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM
-                                if (not r_icache_cleanup_req.read())
-#endif
-                                {
-                                    r_icache_update_addr = 0;
-                                    r_icache_fsm         = ICACHE_MISS_UPDT;
-                                }
+                            if (not r_icache_cleanup_req[num_cache].read())
+#endif
+                            {
+                                r_icache_update_addr[num_cache] = 0;
+                                r_icache_fsm        [num_cache] = ICACHE_MISS_UPDT;
                             }
-                        // }
-                        // else
-                        // {
-                        //     r_icache_inval_rsp = false;
-                            
-                        //     // Miss read response and invalidation
-                        //     if ( r_vci_rsp_ins_error )
-                        //         r_icache_fsm = ICACHE_ERROR;
-                        //     else
-                        //         r_icache_fsm = ICACHE_CC_CLEANUP;
-                        // }
+                        }
                     }
                     break;
@@ -1046,19 +1903,22 @@
                 {
                     m_cost_ins_miss_frz++;
-                    if ( r_tgt_icache_req ) {   // external request
-                        r_icache_fsm = ICACHE_CC_CHECK;
-                        r_icache_fsm_save = r_icache_fsm.read();
+                    if ( r_tgt_icache_req[num_cache] ) {   // external request
+                        r_icache_fsm     [num_cache] = ICACHE_CC_CHECK;
+                        r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read();
                         break;
                     }
 
-                    bool ok = CACHE_MISS_BUF_RSP_VAL(i,0);
+                    bool ok = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0);
+
+                    PRINTF("    * <ICACHE [%d]> ok                   : %d\n",num_cache,ok);
+                    PRINTF("    * <ICACHE [%d]> error                : %d\n",num_cache,(uint32_t)r_vci_rsp_ins_error [num_cache]);
 
                     if (ok)
                     {
-                        if ( r_vci_rsp_ins_error ) {
-                            r_icache_fsm = ICACHE_ERROR;
+                        if ( r_vci_rsp_ins_error [num_cache]) {
+                            r_icache_fsm[num_cache] = ICACHE_ERROR;
                         } else {
-                            r_icache_fsm = ICACHE_IDLE;
-                            r_icache_buf_unc_valid = true;
+                            r_icache_fsm [num_cache] = ICACHE_IDLE;
+                            r_icache_buf_unc_valid[num_cache] = true;
                         }
                     }
@@ -1068,10 +1928,10 @@
             case ICACHE_ERROR:
                 {
-                    if ( (addr_40)ireq.addr == (addr_40)r_icache_addr_save ) {
-                        irsp.error          = true;
-                        irsp.valid          = true;
-                    }
-                    r_icache_fsm = ICACHE_IDLE;
-                    r_vci_rsp_ins_error = false;
+                    if ( (addr_40)_ireq.addr == (addr_40)r_icache_addr_save[num_cache] ) {
+                        _irsp.error          = true;
+                        _irsp.valid          = true;
+                    }
+                    r_icache_fsm        [num_cache] = ICACHE_IDLE;
+                    r_vci_rsp_ins_error [num_cache] = false;
                     break;
                 }
@@ -1079,17 +1939,16 @@
             case ICACHE_MISS_UPDT: 
                 {
-                    size_t     word = r_icache_update_addr.read();
-                    vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read();
+                    size_t     word =              r_icache_update_addr[num_cache].read();
+                    vci_addr_t addr = (vci_addr_t) r_icache_addr_save  [num_cache].read();
                     size_t     way  = 0;
                     size_t     set  = 0;
 
+#if CC_XCACHE_WRAPPER_SELECT_VICTIM
+                    way = r_icache_miss_way[num_cache].read();
+                    set = r_icache_miss_set[num_cache].read();
+#else
                     // need invalid rsp, don't select a victim
-                    if (not r_icache_inval_rsp )
+                    if (not r_icache_inval_rsp[num_cache])
                     {
-#if CC_XCACHE_WRAPPER_SELECT_VICTIM
-                        way = r_icache_miss_way.read();
-                        set = r_icache_miss_set.read();
-#else
-
                         // First word : select an victim !
                         if (word == 0)
@@ -1098,52 +1957,55 @@
                         
                             // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state
-                            r_icache_cleanup_req  = r_icache.victim_select(addr, &victim, &way, &set );
-                            r_icache.victim_update_tag(addr, way, set);
+                            r_icache_cleanup_req[num_cache]  = r_icache[num_cache]->victim_select(addr, &victim, &way, &set );
+                            r_icache[num_cache]->victim_update_tag(addr, way, set);
                         
-                            r_icache_cleanup_line = (addr_40) victim;
-                            r_icache_miss_way     = way;
-                            r_icache_miss_set     = set;
+                            r_icache_cleanup_line[num_cache] = (addr_40) victim;
+                            r_icache_miss_way    [num_cache] = way;
+                            r_icache_miss_set    [num_cache] = set;
                         }
                         else
                         {
-                            way = r_icache_miss_way.read();
-                            set = r_icache_miss_set.read();
+                            way = r_icache_miss_way[num_cache].read();
+                            set = r_icache_miss_set[num_cache].read();
                         }
-#endif
-                    }
-                    bool val = CACHE_MISS_BUF_RSP_VAL(i,word);
+                    }
+#endif
+                    bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,word);
 
                     if (val)
                     {
-                        PRINTF("    * <ICACHE> rsp_val            : %d/%d\n",(int)r_icache_update_addr,m_icache_words);
-                        PRINTF("    * <ICACHE> r_icache_inval_rsp : %d\n",(int)r_icache_inval_rsp);
-                        PRINTF("    * <ICACHE> ins : %x\n",(int)CACHE_MISS_BUF_RSP_DATA(i,word));
+                        PRINTF("    * <ICACHE [%d]> rsp_val            : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],m_icache_words);
+                        PRINTF("    * <ICACHE [%d]> r_icache_inval_rsp : %d\n"   ,num_cache,(int)r_icache_inval_rsp[num_cache]);
+                        PRINTF("    * <ICACHE [%d]> ins                : %x\n"   ,num_cache,(int)CACHE_MISS_BUF_RSP_DATA(i,num_cache,word));
 
                         // m_cpt_icache_dir_write++;
                         // m_cpt_icache_data_write++;
-                        // if ( ireq.valid ) m_cost_ins_miss_frz++;
+                        // if ( _ireq.valid ) m_cost_ins_miss_frz++;
 
                         // if need invalid rsp, don't modify the cache, but pop the buf_rsp
-                        if (not r_icache_inval_rsp )
-                            r_icache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,word));
-                        CACHE_MISS_BUF_RSP_POP(i);
-
-                        r_icache_update_addr = ++word;
+                        if (not r_icache_inval_rsp[num_cache])
+                            r_icache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,num_cache,word));
+
+                        CACHE_MISS_BUF_RSP_POP(i,num_cache);
+
+                        r_icache_update_addr[num_cache] = ++word;
                             
                         // if last word, finish the update
                         if (word >= m_icache_words)
                         {
+#if CC_XCACHE_WRAPPER_SELECT_VICTIM
+                            // in all case (inval_rsp or not), update the victim tag
+                            r_icache[num_cache]->victim_update_tag(addr, way, set);
+#endif
+
                             // Last word : if previous invalid_rsp, can cleanup, else update the TAG
-                            if (r_icache_inval_rsp)
+                            if (r_icache_inval_rsp[num_cache])
                             {
-                                r_icache_inval_rsp  = false;
-                                r_icache_fsm = ICACHE_CC_CLEANUP;
+                                r_icache_inval_rsp[num_cache] = false;
+                                r_icache_fsm      [num_cache] = ICACHE_CC_CLEANUP;
                             }
                             else
                             {
-#if CC_XCACHE_WRAPPER_SELECT_VICTIM
-                                r_icache.victim_update_tag(addr, way, set);
-#endif
-                                r_icache_fsm = ICACHE_IDLE;
+                                r_icache_fsm [num_cache] = ICACHE_IDLE;
                             }
                         }
@@ -1156,15 +2018,19 @@
                 {
                     // external cache invalidate request
-                    if ( r_tgt_icache_req )     
+                    if ( r_tgt_icache_req[num_cache])     
                     {
-                        r_icache_fsm = ICACHE_CC_CHECK;
-                        r_icache_fsm_save = r_icache_fsm.read();
+                        r_icache_fsm     [num_cache] = ICACHE_CC_CHECK;
+                        r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read();
                         break;
                     }
                     // cleanup
-                    if(not r_icache_cleanup_req){
-                        r_icache_cleanup_req = true;
-                        r_icache_cleanup_line = r_icache_addr_save.read() >> m_icache_words_shift;
-                        r_icache_fsm = ICACHE_IDLE;
+                    if(not r_icache_cleanup_req[num_cache]){
+                        r_icache_cleanup_req [num_cache] = true;
+                        r_icache_cleanup_line[num_cache] = r_icache_addr_save[num_cache].read() >> m_icache_words_shift;
+                        r_icache_fsm         [num_cache] = ICACHE_IDLE;
+
+                        // FIXME : too many access at the cache in this cycle
+                        m_cpt_icache_dir_read += m_icache_ways;
+                        r_icache[num_cache]->inval((addr_40)r_icache_addr_save[num_cache]);
                     }
                     break;
@@ -1176,20 +2042,29 @@
                     m_cpt_icache_dir_read  += m_icache_ways;
                     m_cpt_icache_data_read += m_icache_ways;
-                    addr_40 ad = r_tgt_addr;
+                    addr_40 ad = r_tgt_iaddr;
                     data_t  icache_rdata = 0;
 
-                    if((r_icache_fsm_save == ICACHE_MISS_WAIT) and 
-                            ( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) {
-                        r_icache_inval_rsp = true;
-                        r_tgt_icache_req = false;
+                    PRINTF("    * <ICACHE [%d]> CC_CHECK\n",num_cache);
+
+                    if((r_icache_fsm_save[num_cache] == ICACHE_MISS_WAIT) and 
+                       ((r_icache_addr_save[num_cache].read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) {
+                        PRINTF("    * <ICACHE [%d]> have request, need inval rsp\n",num_cache);
+
+                        r_icache_inval_rsp[num_cache] = true;
+                        r_tgt_icache_req  [num_cache] = false;
                         if(r_tgt_update){    // Also send a cleanup and answer
-                            r_tgt_icache_rsp     = true;
+                            PRINTF("    * <ICACHE [%d]> send a cleanup and answer\n",num_cache);
+                            r_tgt_icache_rsp[num_cache] = true;
                         } else {            // Also send a cleanup but don't answer
-                            r_tgt_icache_rsp     = false;
+                            PRINTF("    * <ICACHE [%d]> send a cleanup and but don't answer\n",num_cache);
+                            r_tgt_icache_rsp[num_cache] = false;
                         }
-                        r_icache_fsm = r_icache_fsm_save;
+                        r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache];
                     } else {
-                        bool    icache_hit   = r_icache.read(ad, &icache_rdata);
-                        if ( icache_hit and r_tgt_update ) 
+                        bool    icache_hit   = r_icache[num_cache]->read(ad, &icache_rdata);
+
+                        PRINTF("    * <ICACHE [%d]> have no request, hit cache : %d\n",num_cache,icache_hit);
+
+                        if ( icache_hit and r_tgt_update) 
                         {
 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
@@ -1198,5 +2073,5 @@
                             data_t   rdata = 0;
 
-                            r_icache.read(ad+word*4,&rdata);
+                            r_icache[num_cache]->read(ad+word*4,&rdata);
                             r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata);
                             
@@ -1210,5 +2085,5 @@
                             if (word==m_icache_words)
                             {
-                                r_icache_fsm = ICACHE_CC_UPDT;
+                                r_icache_fsm[num_cache] = ICACHE_CC_UPDT;
 
 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
@@ -1222,23 +2097,23 @@
                             r_cache_word = word;
 #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
-                            r_icache_fsm = ICACHE_CC_UPDT;
+                            r_icache_fsm[num_cache] = ICACHE_CC_UPDT;
                             // complete the line buffer in case of update
                             for(size_t i=0; i<m_icache_words; i++){
                                 data_t rdata = 0;
-                                r_icache.read(ad + i*4,&rdata);
+                                r_icache[num_cache]->read(ad + i*4,&rdata);
                                 data_t mask = vci_param::be2mask(r_tgt_be[i]);
                                 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata);
                             }
 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
-                        } else if ( icache_hit and not r_tgt_update ) {
-                            r_icache_fsm = ICACHE_CC_INVAL;
+                        } else if ( icache_hit and not r_tgt_update) {
+                            r_icache_fsm[num_cache] = ICACHE_CC_INVAL;
                         } else { // instruction not found (can happen)
-                            r_tgt_icache_req = false;
+                            r_tgt_icache_req[num_cache] = false;
                             if(r_tgt_update){
-                                r_tgt_icache_rsp = true;
+                                r_tgt_icache_rsp[num_cache] = true;
                             } else {
-                                r_tgt_icache_rsp = false;
+                                r_tgt_icache_rsp[num_cache] = false;
                             }
-                            r_icache_fsm = r_icache_fsm_save;
+                            r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache];
                         }
                     }
@@ -1248,11 +2123,11 @@
             case ICACHE_CC_INVAL:  
                 {                       
-                    addr_40    ad  = r_tgt_addr;
-                    if ( ireq.valid ) m_cost_ins_miss_frz++;
+                    addr_40 ad  = r_tgt_iaddr;
+                    // if ( _ireq.valid ) m_cost_ins_miss_frz++;
                     m_cpt_icache_dir_read += m_icache_ways;
-                    r_tgt_icache_rsp = true;
-                    r_icache.inval(ad);
-                    r_tgt_icache_req = false;
-                    r_icache_fsm = r_icache_fsm_save;
+                    r_tgt_icache_rsp[num_cache] = true;
+                    r_icache[num_cache]->inval(ad);
+                    r_tgt_icache_req[num_cache] = false;
+                    r_icache_fsm    [num_cache] = r_icache_fsm_save[num_cache];
                     break;
                 }    
@@ -1260,5 +2135,5 @@
             case ICACHE_CC_UPDT:
                 {                       
-                    addr_40 ad = r_tgt_addr.read();
+                    addr_40 ad = r_tgt_iaddr.read();
                     m_cpt_icache_dir_write++;
                     m_cpt_icache_data_write++;
@@ -1268,5 +2143,5 @@
 
                     if(r_tgt_be[word])
-                        r_icache.write(ad+word*4, r_tgt_buf[word]);
+                        r_icache[num_cache]->write(ad+word*4, r_tgt_buf[word]);
 
                     word ++;
@@ -1279,7 +2154,7 @@
                     if (word==m_icache_words)
                     {
-                        r_tgt_icache_req = false;
-                        r_tgt_icache_rsp = true;
-                        r_icache_fsm     = r_icache_fsm_save.read();
+                        r_tgt_icache_req[num_cache] = false;
+                        r_tgt_icache_rsp[num_cache] = true;
+                        r_icache_fsm    [num_cache] = r_icache_fsm_save[num_cache].read();
                         word = 0;
                     }
@@ -1288,9 +2163,9 @@
                     data_t* buf    = r_tgt_buf;
                     for(size_t i=0; i<m_icache_words;i++){
-                        if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]);
-                    }
-                    r_tgt_icache_req = false;
-                    r_tgt_icache_rsp = true;
-                    r_icache_fsm     = r_icache_fsm_save.read();
+                        if(r_tgt_be[i]) r_icache[num_cache]->write( ad + i*4, buf[i]);
+                    }
+                    r_tgt_icache_req [num_cache] = false;
+                    r_tgt_icache_rsp [num_cache] = true;
+                    r_icache_fsm     [num_cache] = r_icache_fsm_save[num_cache].read();
 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
 
@@ -1298,10 +2173,16 @@
                 }    
 
-        } // end switch r_icache_fsm
-
-#if CC_XCACHE_WRAPPER_DEBUG
-        if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
-            std::cout << "    * Instruction Response : " << irsp << std::endl;
-#endif
+        }// end switch r_icache_fsm
+
+        irsp [num_cache] = _irsp;
+        if (_ireq.valid and _irsp.valid)
+        {
+            PRINTF("    * <CPU2CACHE> Transaction between cpu %d and Icache %d (unlock)\n",r_icache_lock [num_cache].read(),num_cache);
+
+            r_icache_lock       [num_cache] = m_nb_cpu;
+            m_cpt_icache_access [num_cache] ++;
+        }
+
+        }// end for num_cache
 
         //////////////////////////////////////////////////////////////////////://///////////
@@ -1361,35 +2242,36 @@
         ///////////////////////////////////////////////////////////////////////////////////
 
-#if CC_XCACHE_WRAPPER_DEBUG
-        if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
-            std::cout << "    * Data        Request  : " << dreq << std::endl;
-#endif
-
-        switch ( r_dcache_fsm ) {
+        for (uint32_t num_cache=0; num_cache<m_nb_dcache; ++num_cache)
+        {
+            typename iss_t::DataRequest  _dreq = dreq [num_cache];
+            typename iss_t::DataResponse _drsp = ISS_DRSP_INITIALIZER;
+
+        switch ( r_dcache_fsm[num_cache]) {
 
                 /////////////////
             case DCACHE_IDLE:
                 {
-                    if ( r_tgt_dcache_req ) {   // external request
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                    if ( r_tgt_dcache_req[num_cache]) {   // external request
+                        r_dcache_fsm     [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache];
                         break;
                     } 
 
-                    if ( dreq.valid ) {
-                        PRINTF("    * <DCACHE> Have dreq\n");
+                    if ( _dreq.valid ) {
+                        PRINTF("    * <DCACHE [%d]> Have dreq\n",num_cache);
 
                         data_t      dcache_rdata       = 0;
-                        // dcache_cached and dcache_hit don't used with dreq.type == {DATA_SC, XTN_READ, XTN_WRITE}
-                        bool        dcache_cached      = m_cacheability_table[(vci_addr_t)dreq.addr];
-                        bool        dcache_hit         = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
-                        bool        dcache_cleanup_hit = r_dcache_cleanup_req and (((addr_40)dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line.read());
-
-                        PRINTF("    * <DCACHE> hit %d - cached %d - cleanup_hit %d\n",dcache_hit, dcache_cached, dcache_cleanup_hit);
+                        // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE}
+                        bool        dcache_cached      = dreq_cached  [num_cache];
+                        uint32_t    dcache_num_cpu     = dreq_num_cpu [num_cache];
+                        bool        dcache_hit         = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata);
+                        bool        dcache_cleanup_hit = r_dcache_cleanup_req[num_cache] and (((addr_40)_dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line[num_cache].read());
+
+                        PRINTF("    * <DCACHE [%d]> hit %d - cached %d - cleanup_hit %d\n",num_cache,dcache_hit, dcache_cached, dcache_cleanup_hit);
                         
                         m_cpt_dcache_data_read += m_dcache_ways;
                         m_cpt_dcache_dir_read  += m_dcache_ways;
 
-                        switch( dreq.type ) {
+                        switch( _dreq.type ) {
                             case iss_t::DATA_READ:
                             case iss_t::DATA_LL:
@@ -1400,20 +2282,21 @@
                                         {
                                             // address is in the cache : return the word
-                                            r_dcache_fsm = DCACHE_IDLE;
-                                            drsp.valid   = true;
-                                            drsp.rdata   = dcache_rdata; // return read data (cf dcache_hit)
+                                            r_dcache_fsm [num_cache] = DCACHE_IDLE;
+
+                                            _drsp.valid   = true;
+                                            _drsp.rdata   = dcache_rdata; // return read data (cf dcache_hit)
                                             
                                             // if the request is a Load Linked instruction, save request information
-                                            if(dreq.type == iss_t::DATA_LL)
+                                            if(_dreq.type == iss_t::DATA_LL)
                                                 {
-                                                    PRINTF("    * <DCACHE> ll_valid = true\n");
-
-                                                    r_dcache_ll_valid = true;
-                                                    r_dcache_ll_data = dcache_rdata;
-                                                    r_dcache_ll_addr = (vci_addr_t) dreq.addr;
+                                                    PRINTF("    * <DCACHE [%d]> ll_valid = true\n",num_cache);
+
+                                                    r_dcache_ll_valid  [num_cache][dcache_num_cpu] = true;
+                                                    r_dcache_ll_data   [num_cache][dcache_num_cpu] = dcache_rdata;
+                                                    r_dcache_ll_addr   [num_cache][dcache_num_cpu] = (vci_addr_t) _dreq.addr;
 #ifdef COHERENCE_DEBUG
-                                                    std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
-                                                    r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
-                                                    std::cout << "Value stored at this  address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
+                                                    std::cout << "Value returned for LL at address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
+                                                    r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata);
+                                                    std::cout << "Value stored at this  address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl;
 #endif
                                                 }
@@ -1423,5 +2306,5 @@
                                             if (not dcache_cleanup_hit)
                                             {
-                                                CACHE_MISS_BUF_REQ_INIT(d);
+                                                CACHE_MISS_BUF_REQ_INIT(d,num_cache);
                                                 
                                                 // Miss : send signal at the CMD_FSM (via r_dcache_miss_req or r_dcache_unc_req)
@@ -1429,20 +2312,20 @@
                                                     m_cpt_data_read_miss++;
                                                     m_cost_data_miss_frz++;
-                                                    r_dcache_miss_req = true;
+                                                    r_dcache_miss_req [num_cache] = true;
 #if CC_XCACHE_WRAPPER_SELECT_VICTIM
-                                                    r_dcache_fsm = DCACHE_MISS_VICTIM;
+                                                    r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM;
 #else
-                                                    r_dcache_fsm = DCACHE_MISS_WAIT;
+                                                    r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT;
 #endif
                                                     
                                                 } else {
-                                                    if (not r_dcache_previous_unc.read()) // strongly order to the uncached access
+                                                    if (not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access
                                                     {
-                                                        r_dcache_previous_unc = true;
+                                                        r_dcache_previous_unc[num_cache] = true;
                                                         
                                                         m_cpt_data_read_uncached++;
                                                         m_cost_unc_read_frz++;
-                                                        r_dcache_unc_req = true;
-                                                        r_dcache_fsm = DCACHE_UNC_WAIT;
+                                                        r_dcache_unc_req[num_cache] = true;
+                                                        r_dcache_fsm    [num_cache] = DCACHE_UNC_WAIT;
                                                     }
                                                 }
@@ -1453,7 +2336,7 @@
                             case iss_t::DATA_SC:
                             {
-                                PRINTF("    * <DCACHE> DATA_SC - ll_valid = %d\n",r_dcache_ll_valid.read());
-
-                                if (not r_dcache_previous_unc.read() and not dcache_cleanup_hit) // strongly order to the uncached access
+                                PRINTF("    * <DCACHE [%d]> DATA_SC - ll_valid = %d, num_cpu = %d\n",num_cache,r_dcache_ll_valid[num_cache][dcache_num_cpu].read(),dcache_num_cpu);
+
+                                if (not r_dcache_previous_unc[num_cache].read() and not dcache_cleanup_hit) // strongly order to the uncached access
                                 {
                                     //m_cpt_data_read_unc++; // instruction must read the memory in uncached mode
@@ -1462,20 +2345,20 @@
                                     // if previous load linked (with the same address), make a transaction
                                     // else, keep in IDLE state and return 1 (no OK)
-                                    if(r_dcache_ll_valid.read() and (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){
-                                        PRINTF("    * <DCACHE> have previous load linked\n");
+                                    if( r_dcache_ll_valid[num_cache][dcache_num_cpu].read() and 
+                                       (r_dcache_ll_addr [num_cache][dcache_num_cpu].read() == (vci_addr_t)_dreq.addr)){
+                                        PRINTF("    * <DCACHE [%d]> have previous load linked\n",num_cache);
                                         
-                                        r_dcache_previous_unc = true;
-
-                                        r_dcache_sc_req   = true;
-
-                                        CACHE_MISS_BUF_REQ_INIT(d);
-
-                                        r_dcache_fsm = DCACHE_SC_WAIT;
+                                        r_dcache_previous_unc[num_cache] = true;
+                                        r_dcache_sc_req      [num_cache] = true;
+
+                                        CACHE_MISS_BUF_REQ_INIT(d,num_cache);
+
+                                        r_dcache_fsm         [num_cache] = DCACHE_SC_WAIT;
                                     } else {
-                                        PRINTF("    * <DCACHE> don't have previous load linked\n");
+                                        PRINTF("    * <DCACHE [%d]> don't have previous load linked\n",num_cache);
                                         
-                                        drsp.valid = true;
-                                        drsp.rdata = 1; // SC rsp NOK
-                                        r_dcache_ll_valid = false;
+                                        _drsp.valid = true;
+                                        _drsp.rdata = 1; // SC rsp NOK
+                                        r_dcache_ll_valid[num_cache][dcache_num_cpu] = false;
                                     }
                                 }
@@ -1486,12 +2369,12 @@
                             case iss_t::XTN_WRITE:
                                 {
-                                    bool drsp_valid = false;
+                                    bool valid = false;
                                     // only DCACHE INVALIDATE and SYNC request are supported
-                                    switch (dreq.addr>>2)
+                                    switch (_dreq.addr>>2)
                                         {
                                         case iss_t::XTN_DCACHE_INVAL : 
                                             {
-                                                drsp_valid = true;
-                                                r_dcache_fsm = DCACHE_INVAL;
+                                                valid = true;
+                                                r_dcache_fsm[num_cache] = DCACHE_INVAL;
                                                 break;
                                             }
@@ -1501,13 +2384,19 @@
                                                 //  * gain : 1 cycle
                                                 //  * cost : can be on the critical path
-                                                if (r_wbuf.empty())
+
+                                                bool empty=true;
+                                                for (uint32_t i=0; i<m_nb_dcache; ++i)
+                                                    empty &= r_wbuf[i]->empty();
+
+                                                if (empty)
                                                     {
-                                                        drsp_valid = true;
-                                                        r_dcache_fsm = DCACHE_IDLE;
+                                                        valid = true;
+                                                        r_dcache_fsm [num_cache] = DCACHE_IDLE;
                                                     }
                                                 else
                                                     {
-                                                        drsp_valid = false;
-                                                        r_dcache_fsm = DCACHE_SYNC;
+                                                        valid = false;
+                                                        r_dcache_fsm [num_cache] = DCACHE_SYNC;
+                                                        r_dcache_sync[num_cache] = true;
                                                     }
                                                 break;
@@ -1516,23 +2405,30 @@
                                             {
                                                 // std::cout << "Warning in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
-                                                // std::cout << "Unsupported  external access : " << (dreq.addr>>2) << std::endl;
-
-                                                r_dcache_fsm = DCACHE_IDLE;
+                                                // std::cout << "Unsupported  external access : " << (_dreq.addr>>2) << std::endl;
+
+                                                r_dcache_fsm [num_cache] = DCACHE_IDLE;
                                             }
-                                        }//end switch (dreq.addr>>2)
-
-                                    drsp.valid = drsp_valid;
-                                    drsp.rdata = 0;
+                                        }//end switch (_dreq.addr>>2)
+
+                                    _drsp.valid = valid;
+                                    _drsp.rdata = 0;
                                     break;
                                 }
                             case iss_t::DATA_WRITE:
 
-                                if (dcache_cached or not r_dcache_previous_unc.read()) // strongly order to the uncached access
+                                PRINTF("    * <DCACHE [%d]> r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read());
+
+                                if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access
                                 {
-                                    bool drsp_valid;
-
-                                    drsp_valid = r_wbuf.write((addr_40) dreq.addr, dreq.be, dreq.wdata, dcache_cached);
-
-                                    if (drsp_valid)
+                                    bool valid;
+                                    addr_40 addr = _dreq.addr;
+                                    set_num_dcache(addr,num_cache);
+
+                                    // FIXME : virer le set_num_dcache !
+                                    valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached);
+
+                                    PRINTF("    * <DCACHE [%d]> r_wbuf valid          : %d\n",num_cache,valid);
+
+                                    if (valid)
                                     {
                                         m_cpt_data_write++;
@@ -1540,5 +2436,5 @@
                                         if (not dcache_cached)
                                         {
-                                            r_dcache_previous_unc = true;
+                                            r_dcache_previous_unc[num_cache] = true;
                                             m_cpt_data_write_uncached++;
                                         }
@@ -1546,26 +2442,29 @@
                                             m_cpt_data_write_miss++;
                                         
-                                        if ( dcache_hit) {
-                                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+                                        if (dcache_hit) {
+                                            // update data cache
+                                            r_dcache_fsm[num_cache] = DCACHE_WRITE_UPDT;
                                         } else {
-                                            r_dcache_fsm = DCACHE_IDLE;
+                                            // write accepted
+                                            r_dcache_fsm [num_cache] = DCACHE_IDLE;
                                         }
                                     }
 
-                                    drsp.valid = drsp_valid;
-                                    drsp.rdata = 0;
+                                    _drsp.valid = valid;
+                                    _drsp.rdata = 0;
                                 }
                                 break;
-                        } // end switch dreq.type
-
-                        r_dcache_addr_save      = (addr_40) dreq.addr;
-                        r_dcache_type_save      = dreq.type;
-                        r_dcache_wdata_save     = dreq.wdata;
-                        r_dcache_be_save        = dreq.be;
-                        r_dcache_rdata_save     = dcache_rdata;
-                        r_dcache_cached_save    = dcache_cached;
-                        
-                    } else {    // end if dreq.valid
-                        r_dcache_fsm = DCACHE_IDLE;
+                        } // end switch _dreq.type
+
+                        r_dcache_addr_save   [num_cache] = (addr_40) _dreq.addr;
+                        r_dcache_type_save   [num_cache] = _dreq.type;
+                        r_dcache_wdata_save  [num_cache] = _dreq.wdata;
+                        r_dcache_be_save     [num_cache] = _dreq.be;
+                        r_dcache_rdata_save  [num_cache] = dcache_rdata;
+                        r_dcache_cached_save [num_cache] = dcache_cached;
+                        r_dcache_num_cpu_save[num_cache] = dcache_num_cpu;
+    
+                    } else {    // end if _dreq.valid
+                        r_dcache_fsm [num_cache] = DCACHE_IDLE;
                     }
                     
@@ -1576,10 +2475,10 @@
                 {
                     m_cpt_dcache_data_write++;
-                    data_t mask = vci_param::be2mask(r_dcache_be_save);
-                    data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
-                    vci_addr_t ad = r_dcache_addr_save.read();
-                    r_dcache.write(ad, wdata);
-
-                    r_dcache_fsm = DCACHE_IDLE;
+                    data_t mask = vci_param::be2mask(r_dcache_be_save[num_cache]);
+                    data_t wdata = (mask & r_dcache_wdata_save[num_cache]) | (~mask & r_dcache_rdata_save[num_cache]);
+                    vci_addr_t ad = r_dcache_addr_save[num_cache].read();
+                    r_dcache[num_cache]->write(ad, wdata);
+
+                    r_dcache_fsm [num_cache] = DCACHE_IDLE;
 
                     break;
@@ -1589,17 +2488,20 @@
             case DCACHE_MISS_VICTIM:
                 {
-                    if (not r_dcache_cleanup_req.read())
+                    if (not r_dcache_cleanup_req[num_cache].read())
                      {
                          size_t     way;
                          size_t     set;
-                         vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read();
+                         vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read();
                          vci_addr_t victim;
+                         bool       victim_val = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set );
                          
-                         r_dcache_cleanup_req  = r_dcache.victim_select(addr, &victim, &way, &set );
-                         r_dcache_cleanup_line = (addr_40) victim;
-                         r_dcache_miss_way     = way;
-                         r_dcache_miss_set     = set;
-                         
-                         r_dcache_fsm = DCACHE_MISS_WAIT;
+                         r_dcache_cleanup_req  [num_cache] = victim_val;
+                         r_dcache_cleanup_line [num_cache] = (addr_40) victim;
+                         r_dcache_miss_way     [num_cache] = way;
+                         r_dcache_miss_set     [num_cache] = set;
+                 
+                         PRINTF("    * <DCACHE [%d]> MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (uint64_t)victim, way, set);
+        
+                         r_dcache_fsm          [num_cache] = DCACHE_MISS_WAIT;
                      }
                     
@@ -1611,44 +2513,29 @@
                 {
 
-                    if ( dreq.valid ) m_cost_data_miss_frz++;
-                    if ( r_tgt_dcache_req.read() ) {   // external request
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                    // if ( _dreq.valid ) m_cost_data_miss_frz++;
+                    if ( r_tgt_dcache_req[num_cache].read() ) {   // external request
+                        r_dcache_fsm      [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache];
                         break;
                     }
 
-                    bool val = CACHE_MISS_BUF_RSP_VAL(d,0);
+                    bool val = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0);
                     if (val)
                     {
-                        // if (not r_dcache_inval_rsp )
-                        //  {
-
                         // Miss read response and no invalidation
-                        if ( r_vci_rsp_data_error )
+                        if (r_vci_rsp_data_error[num_cache])
                         {
-                            r_dcache_fsm = DCACHE_ERROR;
+                            r_dcache_fsm [num_cache] = DCACHE_ERROR;
                         } 
                         else 
                         {
 #if not CC_XCACHE_WRAPPER_SELECT_VICTIM
-                            if (not r_dcache_cleanup_req.read())
+                            if (not r_dcache_cleanup_req[num_cache].read())
 #endif
                             {
-                                r_dcache_update_addr = 0;
-                                r_dcache_fsm         = DCACHE_MISS_UPDT;
+                                r_dcache_update_addr[num_cache] = 0;
+                                r_dcache_fsm        [num_cache] = DCACHE_MISS_UPDT;
                             }
                         }
-                        //  }
-                        // else
-                        // {
-                        //     r_dcache_inval_rsp  = false;
-
-                        //     // Miss read response and invalidation
-                        //     if ( r_vci_rsp_data_error ) {
-                        //         r_dcache_fsm = DCACHE_ERROR;
-                        //     } else {
-                        //         r_dcache_fsm = DCACHE_CC_CLEANUP;
-                        //     }
-                        // }
                     }
                     break;
@@ -1657,16 +2544,16 @@
             case DCACHE_MISS_UPDT:
                 {
-                    size_t     word = r_dcache_update_addr.read();
-                    vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read();
+                    size_t     word = r_dcache_update_addr[num_cache].read();
+                    vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read();
                     size_t     way  = 0;
                     size_t     set  = 0;
                     
                     // need invalid rsp, don't select a victim
-                    if (not r_dcache_inval_rsp )
+#if CC_XCACHE_WRAPPER_SELECT_VICTIM
+                    way = r_dcache_miss_way[num_cache].read();
+                    set = r_dcache_miss_set[num_cache].read();
+#else
+                    if (not r_dcache_inval_rsp[num_cache] )
                     {
-#if CC_XCACHE_WRAPPER_SELECT_VICTIM
-                        way = r_dcache_miss_way.read();
-                        set = r_dcache_miss_set.read();
-#else
                         // First word : select an victim !
                         if (word == 0)
@@ -1675,50 +2562,55 @@
                         
                             // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT
-                            r_dcache_cleanup_req  = r_dcache.victim_select(addr, &victim, &way, &set );
-                            r_dcache.victim_update_tag(addr, way, set);
-                            r_dcache_cleanup_line = (addr_40) victim;
-
-                            r_dcache_miss_way     = way;
-                            r_dcache_miss_set     = set;
+                            r_dcache_cleanup_req [num_cache]  = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set );
+                            r_dcache[num_cache]->victim_update_tag(addr, way, set);
+                            r_dcache_cleanup_line[num_cache] = (addr_40) victim;
+
+                            r_dcache_miss_way [num_cache] = way;
+                            r_dcache_miss_set [num_cache] = set;
                         }
                         else
                         {
-                            way = r_dcache_miss_way.read();
-                            set = r_dcache_miss_set.read();
+                            way = r_dcache_miss_way[num_cache].read();
+                            set = r_dcache_miss_set[num_cache].read();
                         }
-#endif
-                    }
-
-                    bool val = CACHE_MISS_BUF_RSP_VAL(d,word);
-                    if (val)
+                    }
+#endif
+
+                    PRINTF("    * <DCACHE [%d]> MISS_UPDT : Victim way %d, set %d\n",num_cache, way, set);
+
+                    if (CACHE_MISS_BUF_RSP_VAL(d,num_cache,word))
                     {
                         // m_cpt_dcache_dir_write++;
-                        // if ( ireq.valid ) m_cost_data_miss_frz++;
+                        // if ( _dreq.valid ) m_cost_data_miss_frz++;
 
                         // if need invalid rsp, don't modify the cache, but pop the buf_rsp
-                        if (not r_dcache_inval_rsp )
+                        // (power save)
+                        if (not r_dcache_inval_rsp[num_cache])
                         {
-                            r_dcache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,word));
+                            r_dcache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,num_cache,word));
                             m_cpt_dcache_data_write++;
                         }
 
-                        CACHE_MISS_BUF_RSP_POP(d);
-                        r_dcache_update_addr = ++word;
+                        CACHE_MISS_BUF_RSP_POP(d,num_cache);
+                        r_dcache_update_addr[num_cache] = ++word;
                             
                         // if last word, finish the update
                         if (word >= m_dcache_words)
                         {
+#if CC_XCACHE_WRAPPER_SELECT_VICTIM
+                            // in all case (inval_rsp or not), update the victim tag
+                            // because victim is already cleanup
+                            r_dcache[num_cache]->victim_update_tag(addr, way, set);
+#endif
+
                             // Last word : if previous invalid_rsp, can cleanup, else update the TAG
-                            if (r_dcache_inval_rsp)
+                            if (r_dcache_inval_rsp[num_cache])
                             {
-                                r_dcache_inval_rsp  = false;
-                                r_dcache_fsm = DCACHE_CC_CLEANUP;
+                                r_dcache_inval_rsp[num_cache] = false;
+                                r_dcache_fsm      [num_cache] = DCACHE_CC_CLEANUP;
                             }
                             else
                             {
-#if CC_XCACHE_WRAPPER_SELECT_VICTIM
-                                r_dcache.victim_update_tag(addr, way, set);
-#endif
-                                r_dcache_fsm = DCACHE_IDLE;
+                                r_dcache_fsm [num_cache] = DCACHE_IDLE;
                             }
                         }
@@ -1730,30 +2622,31 @@
             case DCACHE_UNC_WAIT:
                 {
-                    if ( dreq.valid ) m_cost_unc_read_frz++;
-                    if ( r_tgt_dcache_req ) {   // external request
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                    // if ( _dreq.valid ) m_cost_unc_read_frz++;
+                    if ( r_tgt_dcache_req[num_cache] ) {   // external request
+                        r_dcache_fsm     [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache];
                         break;
                     } 
 
-                    bool ok = CACHE_MISS_BUF_RSP_VAL(d,0);
+                    bool ok = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0);
 
                     if (ok) {
-                        if ( r_vci_rsp_data_error ) {
-                            r_dcache_fsm = DCACHE_ERROR;
+                        if (r_vci_rsp_data_error[num_cache]) {
+                            r_dcache_fsm[num_cache] = DCACHE_ERROR;
                         } else {
-                            data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,0);
-                            CACHE_MISS_BUF_RSP_POP(d);
-
-                            if(dreq.type == iss_t::DATA_LL){
-                                PRINTF("    * <DCACHE> ll_valid = true\n");
-
-                                r_dcache_ll_valid = true;
-                                r_dcache_ll_data = rdata;
-                                r_dcache_ll_addr = (vci_addr_t) dreq.addr;
+                            data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0);
+                            CACHE_MISS_BUF_RSP_POP(d,num_cache);
+
+                            if(_dreq.type == iss_t::DATA_LL){
+                                PRINTF("    * <DCACHE [%d]> ll_valid = true\n",num_cache);
+
+                                r_dcache_ll_valid  [num_cache][r_dcache_num_cpu_save[num_cache]] = true;
+                                r_dcache_ll_data   [num_cache][r_dcache_num_cpu_save[num_cache]] = rdata;
+                                r_dcache_ll_addr   [num_cache][r_dcache_num_cpu_save[num_cache]] = (vci_addr_t) _dreq.addr;
                             }
-                            r_dcache_fsm = DCACHE_IDLE;
-                            drsp.valid = true;
-                            drsp.rdata = rdata;
+                            r_dcache_fsm [num_cache] = DCACHE_IDLE;
+
+                            _drsp.valid = true;
+                            _drsp.rdata = rdata;
                         }
                     }
@@ -1763,22 +2656,23 @@
             case DCACHE_SC_WAIT:
                 {
-                    if ( dreq.valid ) m_cost_unc_read_frz++;
-                    if ( r_tgt_dcache_req ) {   // external request
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                    // if ( _dreq.valid ) m_cost_unc_read_frz++;
+                    if ( r_tgt_dcache_req[num_cache] ) {   // external request
+                        r_dcache_fsm      [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache];
                         break;
                     } 
 
-                    bool ok = CACHE_MISS_BUF_RSP_VAL(d,0);
+                    bool ok = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0);
 
                     if (ok) {
-                        if ( r_vci_rsp_data_error ) {
-                            r_dcache_fsm = DCACHE_ERROR;
+                        if (r_vci_rsp_data_error[num_cache]) {
+                            r_dcache_fsm [num_cache] = DCACHE_ERROR;
                         } else {
-                            r_dcache_fsm = DCACHE_IDLE;
-                            drsp.valid = true;
-                            drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,0);
-                            CACHE_MISS_BUF_RSP_POP(d);
-                            r_dcache_ll_valid = false;
+                            r_dcache_fsm [num_cache] = DCACHE_IDLE;
+
+                            _drsp.valid = true;
+                            _drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0);
+                            CACHE_MISS_BUF_RSP_POP(d,num_cache);
+                            r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]] = false;
                         }
                     }
@@ -1789,8 +2683,9 @@
             case DCACHE_ERROR:
                 {
-                    r_dcache_fsm = DCACHE_IDLE;
-                    r_vci_rsp_data_error = false;
-                    drsp.error = true;
-                    drsp.valid = true;
+                    r_dcache_fsm        [num_cache] = DCACHE_IDLE;
+
+                    r_vci_rsp_data_error[num_cache] = false;
+                    _drsp.error = true;
+                    _drsp.valid = true;
                     break;
                 }
@@ -1798,16 +2693,16 @@
             case DCACHE_INVAL:
                 {
-                    if ( r_tgt_dcache_req.read() ) {   // external request
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                    if ( r_tgt_dcache_req[num_cache].read() ) {   // external request
+                        r_dcache_fsm      [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache];
                         break;
                     }
-                    if( not r_dcache_cleanup_req.read() ){
+                    if( not r_dcache_cleanup_req [num_cache].read() ){
                         m_cpt_dcache_dir_read += m_dcache_ways;
-                        vci_addr_t  ad  = r_dcache_addr_save.read();
-                        r_dcache_cleanup_req = r_dcache.inval(ad);
-                        r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift;
-
-                        r_dcache_fsm = DCACHE_IDLE;
+                        vci_addr_t  ad  = r_dcache_addr_save [num_cache].read();
+                        r_dcache_cleanup_req  [num_cache] = r_dcache[num_cache]->inval(ad);
+                        r_dcache_cleanup_line [num_cache] = r_dcache_addr_save [num_cache].read() >> m_dcache_words_shift;
+
+                        r_dcache_fsm          [num_cache] = DCACHE_IDLE;
                     }
                     break;
@@ -1815,15 +2710,20 @@
             case DCACHE_SYNC :
                 {
-                    if ( r_tgt_dcache_req ) {   // external request
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                    if ( r_tgt_dcache_req[num_cache] ) {   // external request
+                        r_dcache_fsm     [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache];
                         break;
                     } 
 
-                    if (r_wbuf.empty())
-                        {
-                            drsp.valid = true; // end, can accept the sync request
-                            r_dcache_fsm = DCACHE_IDLE;
-                        }
+                    bool empty=true;
+                    for (uint32_t i=0; i<m_nb_dcache; ++i)
+                        empty &= r_wbuf[i]->empty();
+                    
+                    if (empty)
+                    {
+                        _drsp.valid = true; // end, can accept the sync request
+                        r_dcache_fsm [num_cache] = DCACHE_IDLE;
+                        r_dcache_sync[num_cache] = false;
+                    }
                     break;
                 }
@@ -1831,19 +2731,27 @@
             case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
                 {
-                    addr_40  ad          = r_tgt_addr;
+                    addr_40  ad          = r_tgt_daddr;
                     data_t  dcache_rdata = 0;
 
-                    if((r_dcache_fsm_save == DCACHE_MISS_WAIT) and 
-                            ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
-                        r_dcache_inval_rsp = true;
-                        r_tgt_dcache_req = false;
+                    PRINTF("    * <DCACHE [%d]> CC_CHECK\n",num_cache);
+
+                    if((r_dcache_fsm_save[num_cache] == DCACHE_MISS_WAIT) and 
+                       ((r_dcache_addr_save[num_cache].read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
+                        PRINTF("    * <DCACHE [%d]> have request, need inval rsp\n",num_cache);
+
+                        r_dcache_inval_rsp[num_cache] = true;
+                        r_tgt_dcache_req  [num_cache] = false;
                         if(r_tgt_update){    // Also send a cleanup and answer
-                            r_tgt_dcache_rsp     = true;
+                            PRINTF("    * <DCACHE [%d]> send a cleanup and answer\n",num_cache);
+                            r_tgt_dcache_rsp[num_cache]     = true;
                         } else {            // Also send a cleanup but don't answer
-                            r_tgt_dcache_rsp     = false;
+                            PRINTF("    * <DCACHE [%d]> send a cleanup and but don't answer\n",num_cache);
+                            r_tgt_dcache_rsp[num_cache]     = false;
                         }
-                        r_dcache_fsm = r_dcache_fsm_save;
+                        r_dcache_fsm[num_cache] = r_dcache_fsm_save[num_cache];
                     } else {
-                        bool    dcache_hit   = r_dcache.read(ad, &dcache_rdata);
+                        bool    dcache_hit   = r_dcache[num_cache]->read(ad, &dcache_rdata);
+
+                        PRINTF("    * <DCACHE [%d]> have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update);
 
                         m_cpt_dcache_data_read += m_dcache_ways;
@@ -1860,5 +2768,5 @@
                             data_t   rdata = 0;
 
-                            r_dcache.read(ad+word*4,&rdata);
+                            r_dcache[num_cache]->read(ad+word*4,&rdata);
                             
                             r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata);
@@ -1873,5 +2781,5 @@
                             if (word==m_dcache_words)
                             {
-                                r_dcache_fsm = DCACHE_CC_UPDT;
+                                r_dcache_fsm[num_cache] = DCACHE_CC_UPDT;
 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT
                                 for (word=0; word<m_dcache_words; ++word)
@@ -1887,20 +2795,20 @@
                             for(size_t i=0; i<m_dcache_words; i++){
                                 data_t rdata = 0;
-                                r_dcache.read(ad + i*4,&rdata);
+                                r_dcache[num_cache]->read(ad + i*4,&rdata);
                                 data_t mask = vci_param::be2mask(r_tgt_be[i]);
                                 r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata);
                             }
-                            r_dcache_fsm = DCACHE_CC_UPDT;
+                            r_dcache_fsm[num_cache] = DCACHE_CC_UPDT;
 #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
                         } else if ( dcache_hit and not r_tgt_update ) {
-                            r_dcache_fsm = DCACHE_CC_INVAL;
+                            r_dcache_fsm[num_cache] = DCACHE_CC_INVAL;
                         } else {
                             if(r_tgt_update){
-                                r_tgt_dcache_rsp = true;
+                                r_tgt_dcache_rsp[num_cache] = true;
                             } else {
-                                r_tgt_dcache_rsp = false;
+                                r_tgt_dcache_rsp[num_cache] = false;
                             }
-                            r_tgt_dcache_req = false;
-                            r_dcache_fsm = r_dcache_fsm_save;
+                            r_tgt_dcache_req[num_cache] = false;
+                            r_dcache_fsm    [num_cache] = r_dcache_fsm_save[num_cache];
                         }
                     }
@@ -1910,5 +2818,5 @@
             case DCACHE_CC_UPDT:    // update directory and data cache        
                 {
-                    addr_40 ad = r_tgt_addr;
+                    addr_40 ad = r_tgt_daddr;
 
                     m_cpt_dcache_dir_write++;
@@ -1923,9 +2831,9 @@
                     
                     if(r_tgt_be[word])
-                        r_dcache.write(ad+word*4, r_tgt_buf[word]);
+                        r_dcache[num_cache]->write(ad+word*4, r_tgt_buf[word]);
 # ifdef COHERENCE_DEBUG
                     std::cout << " address " << std::hex << ad+word*4 << " data " << std::dec << r_tgt_buf[word] << std::endl;
                     data_t rdata = 0xAAAAAAAA;
-                    r_dcache.read(ad+word*4,&rdata);
+                    r_dcache[num_cache]->read(ad+word*4,&rdata);
                     std::cout << "data written " << rdata << std::endl; 
 # endif
@@ -1940,7 +2848,7 @@
                     if (word==m_dcache_words)
                     {
-                        r_tgt_dcache_req = false;
-                        r_tgt_dcache_rsp = true;
-                        r_dcache_fsm = r_dcache_fsm_save;
+                        r_tgt_dcache_req[num_cache] = false;
+                        r_tgt_dcache_rsp[num_cache] = true;
+                        r_dcache_fsm    [num_cache] = r_dcache_fsm_save[num_cache];
                         word = 0;
                     }
@@ -1950,16 +2858,16 @@
                     for(size_t i=0; i<m_dcache_words; i++){
                         if(r_tgt_be[i]) {
-                            r_dcache.write( ad + i*4, buf[i]);
+                            r_dcache[num_cache]->write( ad + i*4, buf[i]);
 # ifdef COHERENCE_DEBUG
                             std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl;
                             data_t rdata = 0xAAAAAAAA;
-                            r_dcache.read(ad + i*4,&rdata);
+                            r_dcache[num_cache]->read(ad + i*4,&rdata);
                             std::cout << "data written " << rdata << std::endl; 
 # endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE
                         }
                     }
-                    r_tgt_dcache_req = false;
-                    r_tgt_dcache_rsp = true;
-                    r_dcache_fsm = r_dcache_fsm_save;
+                    r_tgt_dcache_req[num_cache] = false;
+                    r_tgt_dcache_rsp[num_cache] = true;
+                    r_dcache_fsm    [num_cache] = r_dcache_fsm_save[num_cache];
 #endif
                     break;
@@ -1968,9 +2876,9 @@
             case DCACHE_CC_INVAL:   // invalidate a cache line
                 {
-                    addr_40  ad      = r_tgt_addr;
-                    r_tgt_dcache_rsp = true;
-                    r_dcache.inval(ad);
-                    r_tgt_dcache_req = false;
-                    r_dcache_fsm = r_dcache_fsm_save;
+                    addr_40  ad      = r_tgt_daddr;
+                    r_tgt_dcache_rsp[num_cache] = true;
+                    r_dcache        [num_cache]->inval(ad);
+                    r_tgt_dcache_req[num_cache] = false;
+                    r_dcache_fsm    [num_cache] = r_dcache_fsm_save[num_cache];
                     break;
                 }
@@ -1979,15 +2887,19 @@
                 {
                     // external cache invalidate request
-                    if ( r_tgt_dcache_req )   
+                    if ( r_tgt_dcache_req[num_cache] )   
                     {
-                        r_dcache_fsm = DCACHE_CC_CHECK;
-                        r_dcache_fsm_save = r_dcache_fsm;
+                        r_dcache_fsm     [num_cache] = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache];
                         break;
                     }        
                     // cleanup
-                    if(not r_dcache_cleanup_req){
-                        r_dcache_cleanup_req = true;
-                        r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift;
-                        r_dcache_fsm = DCACHE_IDLE;
+                    if(not r_dcache_cleanup_req[num_cache]){
+                        r_dcache_cleanup_req  [num_cache] = true;
+                        r_dcache_cleanup_line [num_cache] = r_dcache_addr_save[num_cache].read() >> m_dcache_words_shift;
+                        r_dcache_fsm          [num_cache] = DCACHE_IDLE;
+
+                        // FIXME : too many access at the cache in this cycle
+                        m_cpt_dcache_dir_read += m_dcache_ways;
+                        r_dcache[num_cache]->inval((addr_40)r_dcache_addr_save[num_cache]);
                     }
                     break;
@@ -1999,94 +2911,135 @@
         // The update() method must be called at each cycle to update the internal state.
         // All pending write requests must be locked in case of SYNC
-        bool wbuf_flush=(r_dcache_fsm == DCACHE_SYNC);
+
+        // bool have_sync=(r_dcache_fsm[num_cache] == DCACHE_SYNC);
 #if   (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==1)
-        r_wbuf.update_multi_scan      (wbuf_flush);
+        r_wbuf[num_cache]->update_multi_scan      (have_sync);
 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==2)
-        r_wbuf.update_round_robin_scan(wbuf_flush);
+        r_wbuf[num_cache]->update_round_robin_scan(have_sync);
 #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==3)
-        r_wbuf.update_one_scan        (wbuf_flush);
+        r_wbuf[num_cache]->update_one_scan        (have_sync);
 #else
-        r_wbuf.update                 (wbuf_flush);
+        r_wbuf[num_cache]->update                 (have_sync);
+#endif
+
+        drsp [num_cache] = _drsp;
+        if (_dreq.valid and _drsp.valid)
+        {
+            PRINTF("    * <CPU2CACHE> Transaction between cpu %d and Dcache %d (unlock)\n",r_dcache_lock [num_cache].read(),num_cache);
+
+            r_dcache_lock       [num_cache] = m_nb_cpu;
+            m_cpt_dcache_access [num_cache] ++;
+        }
+
+        }// end for num_cache
+
+        /////////// execute one iss cycle /////////////////////////////////////////////
+
+        for (uint32_t num_cpu=0; num_cpu<m_nb_cpu; ++num_cpu)
+        {
+            // Test if the resquest is accepted
+            typename iss_t::InstructionResponse _irsp = ISS_IRSP_INITIALIZER;
+            typename iss_t::DataResponse        _drsp = ISS_DRSP_INITIALIZER;
+
+            if (ireq_num_cache[num_cpu]<m_nb_icache)
+                _irsp = irsp[ireq_num_cache[num_cpu]];
+            if (dreq_num_cache[num_cpu]<m_nb_dcache)
+                _drsp = drsp[dreq_num_cache[num_cpu]];
+
+#if CC_XCACHE_WRAPPER_STOP_SIMULATION  or CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+            typename iss_t::InstructionRequest  _ireq = ISS_IREQ_INITIALIZER;
+            typename iss_t::DataRequest         _dreq = ISS_DREQ_INITIALIZER;
+
+            if (ireq_num_cache[num_cpu]<m_nb_icache)
+                _ireq = ireq[ireq_num_cache[num_cpu]];
+            if (dreq_num_cache[num_cpu]<m_nb_dcache)
+                _dreq = dreq[dreq_num_cache[num_cpu]];
 #endif
 
 #if CC_XCACHE_WRAPPER_DEBUG
-        if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
-            std::cout << "    * Data        Response : " << drsp << std::endl;
-#endif
-
-        /////////// execute one iss cycle /////////////////////////////////////////////
-        {
-            uint32_t it = 0;
-            for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 
-                if(p_irq[i].read()) it |= (1<<i);
-            m_iss.executeNCycles(1, irsp, drsp, it);
-        }
-
-        if ( (ireq.valid and not irsp.valid) or 
-             (dreq.valid and not drsp.valid))
-        {
-            m_cpt_frz_cycles++;
+            if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
+            {
+
+                std::cout << "    * CPU                    : " << num_cpu << std::endl
+                          << "      * Instruction Cache    : " << ireq_num_cache[num_cpu] << ", valid : " << (ireq_num_cache[num_cpu]<m_nb_icache) << std::endl
+                          << "      * Instruction Request  : " << _ireq << std::endl
+                          << "      * Instruction Response : " << _irsp << std::endl
+                          << "      * Data        Cache    : " << dreq_num_cache[num_cpu] << ", valid : " << (dreq_num_cache[num_cpu]<m_nb_dcache) << std::endl
+                          << "      * Data        Request  : " << _dreq << std::endl
+                          << "      * Data        Response : " << _drsp << std::endl;
+            }
+#endif
+
+            if ((_ireq.valid and not _irsp.valid) or 
+                (_dreq.valid and not _drsp.valid))
+            {
+                m_cpt_frz_cycles [num_cpu]++;
 #if CC_XCACHE_WRAPPER_STOP_SIMULATION
-            m_stop_simulation_nb_frz_cycles ++;
+                m_stop_simulation_nb_frz_cycles [num_cpu]++;
+                
+                if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles [num_cpu]>= m_stop_simulation_nb_frz_cycles_max))
+                {
+                    std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" (" << num_cpu << ") : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles [num_cpu]<< " cycles." << std::endl;
+                    ASSERT(false,"CPU : anormal activity"); // exit
+                }
+            }
+            else
+            {
+                m_stop_simulation_nb_frz_cycles [num_cpu] = 0; // reinit counter
+#endif //CC_XCACHE_WRAPPER_STOP_SIMULATION
+            }
             
-            if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles >= m_stop_simulation_nb_frz_cycles_max))
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+            if (_ireq.valid and _irsp.valid)
             {
-                std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles << " cycles." << std::endl;
-                ASSERT(false,"CPU : anormal activity"); // exit
+                log_transaction_file_icache [num_cpu]
+                    << "[" << m_cpt_total_cycles << "]"
+                    << std::hex
+                    << " @ "     << std::setw(8) << (uint32_t)_ireq.addr
+                    << " ("      << std::setw(8) << (uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu]) 
+                    << " - L "     << std::setw(8) <<((uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu])&m_icache_yzmask) << ")"
+                    << " I "     << std::setw(8) << (uint32_t)_irsp.instruction
+                    << " error "                 << (uint32_t)_irsp.error
+                    << std::dec
+                    << std::endl;
             }
-        }
-        else
-        {
-            m_stop_simulation_nb_frz_cycles = 0; // reinit counter
-#endif //CC_XCACHE_WRAPPER_STOP_SIMULATION
-        }
-
-
-#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
-        if (dreq.valid and drsp.valid)
-        {
-            log_dcache_transaction_file 
-                << "[" << m_cpt_total_cycles << "]"
-                << std::hex
-                << " @ "     << std::setw(8) << (uint32_t)dreq.addr
-                << " be "    << std::setw(1) << (uint32_t)dreq.be
-                << " W "     << std::setw(8) << (uint32_t)dreq.wdata
-                << " R "     << std::setw(8) << (uint32_t)drsp.rdata
-                << " error "            << (uint32_t)drsp.error
-                << std::dec
-                << " "  << type_str(dreq.type);
-
-            if ((dreq.type == iss_t::XTN_READ) or 
-                (dreq.type == iss_t::XTN_WRITE))
-                //log_dcache_transaction_file << xtn_str(dreq.addr>>2);
-                switch (dreq.addr>>2)
-                {
-                case iss_t::XTN_DCACHE_INVAL : log_dcache_transaction_file << " INVAL"; break;
-                case iss_t::XTN_SYNC         : log_dcache_transaction_file << " SYNC"; break;
-                default                      : log_dcache_transaction_file << " invalid"; break;
-                }                                                                            
-
-            log_dcache_transaction_file << std::endl;
-
-            // printf("[%d] @ %.8x be %.1x W %.8x R %.8x error %d - %s"
-            //        ,(uint32_t)m_cpt_total_cycles
-            //        ,(uint32_t)dreq.addr
-            //        ,(uint32_t)dreq.be
-            //        ,(uint32_t)dreq.wdata
-            //        ,(uint32_t)drsp.rdata
-            //        ,(uint32_t)drsp.error
-            //        ,type_str(dreq.type));
-            // if ((dreq.type == iss_t::XTN_READ) or 
-            //     (dreq.type == iss_t::XTN_WRITE))
-            //     //     printf(" %s",xtn_str(dreq.addr>>2));
-            //     switch (dreq.addr>>2)
-            //     {
-            //     case iss_t::XTN_DCACHE_INVAL : printf(" INVAL"); break;
-            //     case iss_t::XTN_SYNC         : printf(" SYNC"); break;
-            //     default                      : printf(" invalid"); break;
-            //     }                                                                            
-            // printf("\n");
-        }
-#endif //CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION
+
+            if (_dreq.valid and _drsp.valid)
+            {
+                log_transaction_file_dcache [num_cpu]
+                    << "[" << m_cpt_total_cycles << "]"
+                    << std::hex
+                    << " @ "     << std::setw(8) << (uint32_t)_dreq.addr
+                    << " ("      << std::setw(8) << (uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu])
+                    << " - L "   << std::setw(8) <<((uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu])&m_dcache_yzmask) << ")"
+                    << " be "    << std::setw(1) << (uint32_t)_dreq.be
+                    << " W "     << std::setw(8) << (uint32_t)_dreq.wdata
+                    << " R "     << std::setw(8) << (uint32_t)_drsp.rdata
+                    << " error "                 << (uint32_t)_drsp.error
+                    << std::dec
+                    << " "  << type_str(_dreq.type);
+                
+                if ((_dreq.type == iss_t::XTN_READ) or 
+                    (_dreq.type == iss_t::XTN_WRITE))
+                    //log_transaction_file_dcache [num_cpu] << xtn_str(_dreq.addr>>2);
+                    switch (_dreq.addr>>2)
+                    {
+                    case iss_t::XTN_DCACHE_INVAL : log_transaction_file_dcache [num_cpu]<< " INVAL"; break;
+                    case iss_t::XTN_SYNC         : log_transaction_file_dcache [num_cpu]<< " SYNC"; break;
+                    default                      : log_transaction_file_dcache [num_cpu]<< " invalid"; break;
+                    }
+                
+                log_transaction_file_dcache [num_cpu]<< std::endl;
+            }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+            
+            {
+                uint32_t it = 0;
+                for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 
+                    if(p_irq[num_cpu][i].read()) it |= (1<<i);
+                
+                m_iss[num_cpu]->executeNCycles(1, _irsp, _drsp, it);
+            }
+        }//end num_cpu
 
         ////////////////////////////////////////////////////////////////////////////
@@ -2113,30 +3066,95 @@
 
             case CLEANUP_IDLE:
-            {    
-                if ( p_vci_ini_c.cmdack )
-                {
-                    if      (r_dcache_cleanup_req) 	r_cleanup_fsm = CLEANUP_DCACHE;
-                    else if (r_icache_cleanup_req) 	r_cleanup_fsm = CLEANUP_ICACHE;
+            {
+                uint32_t num_cache          = 0;
+                bool     cleanup_dcache_req = false;
+                bool     cleanup_icache_req = false;
+
+                // dcache is prior
+                for (uint32_t i=0; i<m_nb_dcache; ++i)
+                {
+                    PRINTF("      * <CLEANUP> dcache_cleanup_req : [%d] %d\n",i,(int)r_dcache_cleanup_req[i]);
+                    cleanup_dcache_req |= r_dcache_cleanup_req[i];
+                    if (cleanup_dcache_req)
+                    {
+                        PRINTF("      * <CLEANUP> ... find\n");
+                        num_cache=i;
+                        break;
+                    }
+                }
+ 
+                if (not cleanup_dcache_req)
+                for (uint32_t i=0; i<m_nb_icache; ++i)
+                {
+                    PRINTF("      * <CLEANUP> icache_cleanup_req : [%d] %d\n",i,(int)r_icache_cleanup_req[i]);
+
+                    cleanup_icache_req |= r_icache_cleanup_req[i];
+                    if (cleanup_icache_req)
+                    {
+                        PRINTF("      * <CLEANUP> ... find\n");
+                        num_cache=i;
+                        break;
+                    }
+                }
+
+                PRINTF("      * <CLEANUP> cleanup_icache_req : %d\n",cleanup_icache_req);
+                PRINTF("      * <CLEANUP> cleanup_dcache_req : %d\n",cleanup_dcache_req);
+                PRINTF("      * <CLEANUP> num_cache          : %d\n",num_cache);
+
+                if (cleanup_icache_req or cleanup_dcache_req)
+                {
+                    r_cleanup_fsm       = CLEANUP_REQ;
+                    r_cleanup_icache    = cleanup_icache_req;
+                    r_cleanup_num_cache = num_cache;
+
+                    PRINTF("      * <CLEANUP> address            : %llx\n",((cleanup_icache_req)?((uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((uint64_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache))));
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    log_transaction_file_cleanup
+                        << "[" << m_cpt_total_cycles << "] "
+                        << ((cleanup_icache_req)?("icache "):("dcache "))
+                        << num_cache << " : "
+                        << std::hex
+                        << " L "     << std::setw(10) << ((cleanup_icache_req)?((uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()<<m_icache_words_shift,num_cache)):((uint64_t)set_num_dcache_only(r_dcache_cleanup_line[num_cache].read()<<m_dcache_words_shift,num_cache)))
+                        // << " (" << std::setw(10) << addr << ")"
+                        << std::dec
+                        << std::endl;
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
                 }
                 break;
             }
-            case CLEANUP_DCACHE:
+            case CLEANUP_REQ:
+            {
+                if ( p_vci_ini_c.cmdack )
+                {
+                    if (r_cleanup_icache)
+                        r_cleanup_fsm = CLEANUP_RSP_ICACHE;
+                    else
+                        r_cleanup_fsm = CLEANUP_RSP_DCACHE;
+                }
+                break;
+            }
+            case CLEANUP_RSP_DCACHE:
             {
                 if ( p_vci_ini_c.rspval )
                 {
                     PRINTF("      * <CLEANUP> rerror : %d (%d)\n",(uint32_t)p_vci_ini_c.rerror.read(),0x2 & ( (1 << vci_param::E) - 1));
+                    PRINTF("      * <CLEANUP> rpktid : %d, r_cleanup_num_cache : %d\n",(uint32_t)p_vci_ini_c.rpktid.read(), (uint32_t)r_cleanup_num_cache);
 
                     ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_DATA_CLEANUP),
-                            "illegal response packet received for a cleanup transaction");
+                           "illegal response packet received for a cleanup transaction");
                     ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL,
                            "error signaled in a cleanup response" );
-                    
+                    ASSERT(p_vci_ini_c.rpktid.read() == (sc_dt::sc_uint<vci_param::P>)r_cleanup_num_cache,
+                           "invalid pktid in a cleanup response");
+
                     r_cleanup_fsm = CLEANUP_IDLE;
-                    r_dcache_cleanup_req = false;
-                    // m_cpt_cc_cleanup_data++; TODO
+                    r_dcache_cleanup_req[r_cleanup_num_cache] = false;
+                    // m_cpt_cc_cleanup_data++;
                 }
                 break;
             }
-            case CLEANUP_ICACHE:
+            case CLEANUP_RSP_ICACHE:
             {
                 if ( p_vci_ini_c.rspval )
@@ -2150,6 +3168,6 @@
                     
                     r_cleanup_fsm = CLEANUP_IDLE;
-                    r_icache_cleanup_req = false;
-                    // m_cpt_cc_cleanup_ins++; TODO
+                    r_icache_cleanup_req[r_cleanup_num_cache] = false;
+                    // m_cpt_cc_cleanup_ins++;
                 }
                 break;
@@ -2195,7 +3213,10 @@
                 // if (r_vci_rsp_fsm != RSP_IDLE) break;
 
-                size_t	min;
-                size_t	max;
-
+                size_t	wbuf_min   = 0;
+                size_t	wbuf_max   = 0;
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                addr_40 wbuf_addr  = 0;
+                size_t  wbuf_index = 0;
+#endif
                 r_vci_cmd_cpt = 0;
 
@@ -2204,74 +3225,254 @@
                 // multi_write_buffer access is conditionnal with dcache_miss_req and icache_miss_req
 
-#if   (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1)
-                //  1) two access authorized
-                bool dcache_miss_req =  r_dcache_miss_req;
-                bool icache_miss_req =  r_icache_miss_req;
-#elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2)
-                //  2) one access with static priority (dcache prior)
-                bool dcache_miss_req = r_dcache_miss_req; // dcache prior
-                bool icache_miss_req = not dcache_miss_req and r_icache_miss_req;
+                bool     dcache_miss_req      = false;
+                bool     icache_miss_req      = false;
+                uint32_t dcache_miss_num_cache = 0;
+                uint32_t icache_miss_num_cache = 0;
+                addr_40  addr = 0;
+
+                {
+                    for (; dcache_miss_num_cache<m_nb_dcache; ++dcache_miss_num_cache)
+                    {
+                        dcache_miss_req = r_dcache_miss_req[dcache_miss_num_cache];
+                        if (dcache_miss_req)
+                            break;
+                    }
+                    for (; icache_miss_num_cache<m_nb_icache; ++icache_miss_num_cache)
+                    {
+                        icache_miss_req = r_icache_miss_req[icache_miss_num_cache];
+                        if (icache_miss_req)
+                            break;
+                    }
+
+                    PRINTF("      * <CMD> icache_miss_req (before) : %d\n",icache_miss_req);
+                    PRINTF("      * <CMD> dcache_miss_req (before) : %d\n",dcache_miss_req);
+
+// #if   (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1)
+//                     //  1) two access authorized
+//                     dcache_miss_req =  r_dcache_miss_req[cache_miss_num_cache];
+//                     icache_miss_req =  r_icache_miss_req[cache_miss_num_cache];
+// #el
+#if   (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2)
+                    //  2) one access with static priority (dcache prior)
+                    icache_miss_req &= not dcache_miss_req;
 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3)
-                //  3) one access with static priority (icache prior)
-                bool icache_miss_req = r_icache_miss_req;
-                bool dcache_miss_req = not icache_miss_req and r_dcache_miss_req; // dcache prior
+                    //  3) one access with static priority (icache prior)
+                    dcache_miss_req &= not icache_miss_req;
 #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4)
-                //  4) one access with round robin priority
-                bool dcache_miss_req = ((r_dcache_miss_req and not r_icache_miss_req) or // only dcache
-                                        (r_dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior
-                bool icache_miss_req = not dcache_miss_req and r_icache_miss_req;
+                    //  4) one access with round robin priority
+                    dcache_miss_req = ((dcache_miss_req and not icache_miss_req) or // only dcache
+                                       (dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior
+                    icache_miss_req &= not dcache_miss_req;
 #else
 #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY"
 #endif
+
+                    PRINTF("      * <CMD> icache_miss_req (after ) : %d\n",icache_miss_req);
+                    PRINTF("      * <CMD> dcache_miss_req (after ) : %d\n",dcache_miss_req);
+
+                    PRINTF("      * <CMD> icache_miss_num_cache    : %d\n",icache_miss_num_cache);
+                    PRINTF("      * <CMD> dcache_miss_num_cache    : %d\n",dcache_miss_num_cache);
+
+                    if (icache_miss_req or dcache_miss_req)
+                    {
+                        addr = (icache_miss_req)?r_icache_addr_save[icache_miss_num_cache].read():r_dcache_addr_save[dcache_miss_num_cache].read();
+
+                        PRINTF("      * <CMD> addr                     : %llx\n",(uint64_t)addr);
+
+                        if (icache_miss_req)
+                        {
+                            // FIXME : 
+                            // si wbuf contient des addresses partionné, set_num_icache puis get_num_dcache
+                            // dcache_miss_num_cache = icache_miss_num_cache;
+                            set_num_icache(addr,icache_miss_num_cache);
+                            // get_num_dcache(addr,dcache_miss_num_cache);
+                        }
+                        else
+                            set_num_dcache(addr,dcache_miss_num_cache);
+
+                        PRINTF("      * <CMD> addr                     : %llx\n",(uint64_t)addr);
+                    }
+                }
+
+                uint32_t dcache_unc_num_cache = 0;
+                for (; dcache_unc_num_cache<m_nb_dcache; ++dcache_unc_num_cache)
+                    if (r_dcache_unc_req[dcache_unc_num_cache])
+                        break;
+                uint32_t icache_unc_num_cache = 0;
+                for (; icache_unc_num_cache<m_nb_icache; ++icache_unc_num_cache)
+                    if (r_icache_unc_req[icache_unc_num_cache])
+                        break;
+                uint32_t dcache_sc_num_cache = 0;
+                for (; dcache_sc_num_cache<m_nb_dcache; ++dcache_sc_num_cache)
+                    if (r_dcache_sc_req[dcache_sc_num_cache])
+                        break;
+                uint32_t dcache_write_num_cache = 0;
+                for (; dcache_write_num_cache<m_nb_dcache; ++dcache_write_num_cache)
+                {
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    if ( r_wbuf[dcache_write_num_cache]->debug_rok(&wbuf_min, &wbuf_max, &wbuf_addr, &wbuf_index))
+                        break;
+#else
+                    if ( r_wbuf[dcache_write_num_cache]->rok(&wbuf_min, &wbuf_max))
+                        break;
+#endif
+                }
+                
                 // 1 - Data Read
-                if (dcache_miss_req and r_wbuf.miss(r_dcache_addr_save))
+                if (dcache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr))
                 { 
-                    r_vci_cmd_fsm = CMD_DATA_MISS;
-                    r_dcache_miss_req = false;
+                    r_vci_cmd_fsm       = CMD_DATA_MISS;
+                    r_vci_cmd_num_cache = dcache_miss_num_cache;
+                    r_dcache_miss_req[dcache_miss_num_cache] = false;
                     m_cpt_dmiss_transaction++; 
+
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    {
+                        log_transaction_file_cmd
+                            << "[" << m_cpt_total_cycles << "] "
+                            << "CMD DATA MISS  "
+                            << "(" << dcache_miss_num_cache << ") "
+                            << std::hex
+                            << " @ " << std::setw(10) << (uint64_t)addr
+                            << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"
+                            << std::dec
+                            << std::endl;
+                    }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
                 } 
 
                 // 2 - Data Read Uncachable
-                else if ( r_dcache_unc_req )
+                else if (dcache_unc_num_cache < m_nb_dcache) // have r_dcache_unc_req
                 { 
-                    r_vci_cmd_fsm = CMD_DATA_UNC;
-                    r_dcache_unc_req = false;
-                 // m_cpt_data_unc_transaction++; 
+                    r_vci_cmd_fsm       = CMD_DATA_UNC;
+                    r_vci_cmd_num_cache = dcache_unc_num_cache;
+                    r_dcache_unc_req[dcache_unc_num_cache] = false;
+                    // m_cpt_data_unc_transaction++; 
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    {
+                        addr_40 addr = (addr_40) r_dcache_addr_save[dcache_unc_num_cache].read() & ~0x3;
+                        set_num_dcache(addr,dcache_unc_num_cache);
+                        
+                        log_transaction_file_cmd
+                            << "[" << m_cpt_total_cycles << "] "
+                            << "CMD DATA UNC   "
+                            << "(" << dcache_unc_num_cache << ") "
+                            << std::hex
+                            << " @ " << std::setw(10) << (uint64_t)addr
+                            << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"
+                            << std::dec
+                            << std::endl;
+                    }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                 }
 
                 // 3 - Instruction Miss
-                else if (icache_miss_req and r_wbuf.miss(r_icache_addr_save))
+                else if (icache_miss_req and r_wbuf[icache_miss_num_cache]->miss(addr))
+              //else if (icache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr))
                 { 
-                    r_vci_cmd_fsm = CMD_INS_MISS; 
-                    r_icache_miss_req = false;
+                    r_vci_cmd_fsm       = CMD_INS_MISS; 
+                    r_vci_cmd_num_cache = icache_miss_num_cache;
+                    r_icache_miss_req[icache_miss_num_cache] = false;
                     m_cpt_imiss_transaction++;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    {
+                        log_transaction_file_cmd
+                            << "[" << m_cpt_total_cycles << "] "
+                            << "CMD INS  MISS  "
+                            << "(" << icache_miss_num_cache << ") "
+                            << std::hex
+                            << " @ " << std::setw(10) << (uint64_t)addr
+                            << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_icache_yzmask) << ")"
+                            << std::dec
+                            << std::endl;
+                    }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                 } 
 
                 // 4 - Instruction Uncachable
-                else if ( r_icache_unc_req )
+                else if (icache_unc_num_cache < m_nb_icache) // have r_icache_unc_req
                 { 
-                    r_vci_cmd_fsm = CMD_INS_UNC; 
-                    r_icache_unc_req = false;
+                    r_vci_cmd_fsm       = CMD_INS_UNC; 
+                    r_vci_cmd_num_cache = icache_unc_num_cache;
+                    r_icache_unc_req[icache_unc_num_cache] = false;
                  // m_cpt_ins_unc_transaction++;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    {
+                        addr_40 addr = (addr_40) r_icache_addr_save[icache_unc_num_cache].read() & ~0x3;
+                        set_num_dcache(addr,icache_unc_num_cache);
+                        
+                        log_transaction_file_cmd
+                            << "[" << m_cpt_total_cycles << "] "
+                            << "CMD INS  UNC   "
+                            << "(" << icache_unc_num_cache << ") "
+                            << std::hex
+                            << " @ " << std::setw(10) << (uint64_t)addr
+                            << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_icache_yzmask) << ")"
+                            << std::dec
+                            << std::endl;
+                    }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                 }
 
                 // 5 - Data Write
-                else if ( r_wbuf.rok(&min, &max) ) 
+                else if (dcache_write_num_cache < m_nb_dcache) // have r_wbuf.rok(&wbuf_min, &wbuf_max)
                 { 
-                    r_vci_cmd_fsm = CMD_DATA_WRITE;
-                    r_vci_cmd_cpt = min;
-                    r_vci_cmd_min = min;
-                    r_vci_cmd_max = max;
+                    r_vci_cmd_num_cache = dcache_write_num_cache;
+                    r_vci_cmd_fsm       = CMD_DATA_WRITE;
+                    r_vci_cmd_cpt       = wbuf_min;
+                    r_vci_cmd_min       = wbuf_min;
+                    r_vci_cmd_max       = wbuf_max;
                     m_cpt_data_write_transaction++; 
-                    m_length_write_transaction += (max-min+1); 
+                    m_length_write_transaction += (wbuf_max-wbuf_min+1); 
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    {
+                        addr_40 addr = (addr_40) wbuf_addr&~0x3;
+                        
+                        log_transaction_file_cmd
+                            << "[" << m_cpt_total_cycles << "] "
+                            << "CMD DATA WRITE "
+                            << "(" << dcache_write_num_cache << ") "
+                            << std::hex
+                            << " @ " << std::setw(10) << (uint64_t)addr
+                            << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"
+                            << " [" << wbuf_min << ":" << wbuf_max << "]"
+                            << " {" << wbuf_index << "}"
+                            << std::dec
+                            << std::endl;
+                    }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                 } 
 
                 // 6 - Data Store Conditionnal
-                else if ( r_dcache_sc_req ) 
+                else if (dcache_sc_num_cache < m_nb_dcache) // have r_dcache_sc_req
                 { 
-                    r_vci_cmd_fsm = CMD_DATA_SC;
-                    r_vci_cmd_max = 1; 
+                    r_vci_cmd_fsm       = CMD_DATA_SC;
+                    r_vci_cmd_num_cache = dcache_sc_num_cache;
+                    r_vci_cmd_max       = 1; 
                     m_cpt_unc_transaction++; 
-                    r_dcache_sc_req = false;
+                    r_dcache_sc_req[dcache_sc_num_cache] = false;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    {
+                        addr_40 addr = (addr_40) r_dcache_addr_save[dcache_sc_num_cache].read() & ~0x3;
+                        set_num_dcache(addr,dcache_sc_num_cache);
+                        
+                        log_transaction_file_cmd
+                            << "[" << m_cpt_total_cycles << "] "
+                            << "CMD DATA SC    "
+                            << "(" << dcache_sc_num_cache << ") "
+                            << std::hex
+                            << " @ " << std::setw(10) << (uint64_t)addr
+                            << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")"
+                            << std::dec
+                            << std::endl;
+                    }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
                 }
 
@@ -2283,5 +3484,5 @@
                     if (r_vci_cmd_cpt == r_vci_cmd_max) {
                         r_vci_cmd_fsm = CMD_IDLE ;
-                        r_wbuf.sent() ;
+                        r_wbuf[r_vci_cmd_num_cache]->sent() ;
                     }
                 }
@@ -2339,19 +3540,110 @@
                 if( p_vci_ini_rw.rspval.read() )
                 {
-                    PRINTF("      * <RSP> have rsp - trdid : %x\n",(uint32_t)p_vci_ini_rw.rtrdid.read());
+                    PRINTF("      * <RSP> have rsp - trdid : %x - num_cache : %d\n",(uint32_t)p_vci_ini_rw.rtrdid.read(),(uint32_t)p_vci_ini_rw.rpktid.read());
+
+                    ASSERT(p_vci_ini_rw.rpktid.read() <= (1<<vci_param::P),
+                           "invalid pktid in a cleanup response");
 
                     r_vci_rsp_cpt = 0;
 
                     if ((p_vci_ini_rw.rtrdid.read()>>(vci_param::T-1)) != 0 )
+                    {
                         r_vci_rsp_fsm = RSP_DATA_WRITE;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                        {
+                            log_transaction_file_cmd
+                                << "[" << m_cpt_total_cycles << "] "
+                                << "RSP DATA WRITE "
+                                << "(" << p_vci_ini_rw.rpktid.read() << ") "
+                                << "{" << (p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1))) << "}"
+                                << std::endl;
+                        }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                    }
                     else
                     {
                         switch (p_vci_ini_rw.rtrdid.read())
                         {
-                        case TYPE_INS_MISS     : r_vci_rsp_fsm = RSP_INS_MISS;     break;
-                        case TYPE_INS_UNC      : r_vci_rsp_fsm = RSP_INS_UNC;      break;
-                        case TYPE_DATA_MISS    : r_vci_rsp_fsm = RSP_DATA_MISS;    break;
-                        case TYPE_DATA_UNC     : r_vci_rsp_fsm = RSP_DATA_UNC;     break;
-                        case TYPE_DATA_SC      : r_vci_rsp_fsm = RSP_DATA_SC;      break;
+                        case TYPE_INS_MISS     : 
+                            {
+                                r_vci_rsp_fsm = RSP_INS_MISS;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_cmd
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "RSP INS  MISS  "
+                                        << "(" << p_vci_ini_rw.rpktid.read() << ") "
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
+                                break;
+                            }
+                        case TYPE_INS_UNC      : 
+                            {
+                                r_vci_rsp_fsm = RSP_INS_UNC;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_cmd
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "RSP INS  UNC   "
+                                        << "(" << p_vci_ini_rw.rpktid.read() << ") "
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
+                                break;
+                            }
+                        case TYPE_DATA_MISS    : 
+                            {
+                                r_vci_rsp_fsm = RSP_DATA_MISS;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_cmd
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "RSP DATA MISS  "
+                                        << "(" << p_vci_ini_rw.rpktid.read() << ") "
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
+                                break;
+                            }
+                        case TYPE_DATA_UNC     : 
+                            {
+                                r_vci_rsp_fsm = RSP_DATA_UNC;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_cmd
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "RSP DATA UNC   "
+                                        << "(" << p_vci_ini_rw.rpktid.read() << ") "
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
+                                break;
+                            }
+                        case TYPE_DATA_SC      : 
+                            {
+                                r_vci_rsp_fsm = RSP_DATA_SC;
+
+#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+                                {
+                                    log_transaction_file_cmd
+                                        << "[" << m_cpt_total_cycles << "] "
+                                        << "RSP DATA SC    "
+                                        << "(" << p_vci_ini_rw.rpktid.read() << ") "
+                                        << std::endl;
+                                }
+#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
+
+                                break;
+                            }
                         default : 
                             {
@@ -2360,4 +3652,6 @@
                         }
                     }
+
+                    r_vci_rsp_num_cache = p_vci_ini_rw.rpktid.read();
                 }
                 break;
@@ -2366,7 +3660,7 @@
 
                 m_cost_imiss_transaction++;
-                PRINTF("      * <RSP> rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t)r_vci_rsp_ack);
-
-                if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)
+                PRINTF("      * <RSP> rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t)s_vci_rsp_ack);
+
+                if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack)
                 {
                     PRINTF("      * <RSP> have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words);
@@ -2376,5 +3670,5 @@
                             "The VCI response packet for instruction miss is too long" );
                     r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
-                    CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read());
+                    CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_num_cache,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read());
                     if ( p_vci_ini_rw.reop.read() ) 
                     {
@@ -2383,5 +3677,5 @@
                         ASSERT( ((r_vci_rsp_cpt == m_icache_words - 1) or
                                  p_vci_ini_rw.rerror.read() or
-                                 (r_vci_rsp_ins_error.read()&0x1)),
+                                 (r_vci_rsp_ins_error[r_vci_rsp_num_cache].read()&0x1)),
                                 "The VCI response packet for instruction miss is too short");
                         r_vci_rsp_cpt    = 0;
@@ -2389,5 +3683,5 @@
 
                     }
-                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error[r_vci_rsp_num_cache] = true;
                 }
                 break;
@@ -2396,14 +3690,14 @@
 
                 m_cost_imiss_transaction++;
-                if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)
+                if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack)
                 {
                     ASSERT(p_vci_ini_rw.reop.read(),
                            "illegal VCI response packet for uncached instruction");
 
-                    CACHE_MISS_BUF_RSP_PUSH(i,0,(data_t)p_vci_ini_rw.rdata.read());
+                    CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read());
 
                     r_vci_rsp_fsm = RSP_IDLE;
 
-                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error[r_vci_rsp_num_cache] = true;
                 }
                 break;
@@ -2412,5 +3706,5 @@
 
                 m_cost_dmiss_transaction++;
-                if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)
+                if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack)
                 {
                     PRINTF("      * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read());
@@ -2420,20 +3714,19 @@
                     r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
 
-                    CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read());
+                    CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read());
 
                     if ( p_vci_ini_rw.reop.read() ) {
                         ASSERT( ((r_vci_rsp_cpt == m_dcache_words - 1) 
                                  or (p_vci_ini_rw.rerror.read()&0x1)
-                                 or r_vci_rsp_data_error.read()),
+                                 or r_vci_rsp_data_error[r_vci_rsp_num_cache].read()),
                                 "illegal VCI response packet for data read miss");
                         r_vci_rsp_cpt     = 0;
                         r_vci_rsp_fsm     = RSP_IDLE;
                     }
-                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true;
                 }
                 break;
 
             case RSP_DATA_WRITE:
-
                 m_cost_write_transaction++;
                 if (p_vci_ini_rw.rspval.read())
@@ -2444,12 +3737,13 @@
                            "A VCI response packet must contain one flit for a write transaction");
                     r_vci_rsp_fsm = RSP_IDLE;
-                    bool cached = r_wbuf.completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)) );
+                    bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)));
 
                     PRINTF("      * <RSP> cached : %d\n",cached);
 
                     if (not cached)
-                        r_dcache_previous_unc = false;
-
-                    if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss.setWriteBerr();
+                        r_dcache_previous_unc[r_vci_rsp_num_cache] = false;
+
+                    // FIXME : r_vci_rsp_num_cache != num_cpu ! -> pktid
+                    if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss[r_vci_rsp_num_cache]->setWriteBerr();
                 }
                 break;
@@ -2457,15 +3751,15 @@
             case RSP_DATA_UNC:
                 m_cost_unc_transaction++;
-                if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)
+                if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack)
                 {
                     ASSERT(p_vci_ini_rw.reop.read(),
                            "illegal VCI response packet for data read uncached");
 
-                    CACHE_MISS_BUF_RSP_PUSH(d,0,(data_t)p_vci_ini_rw.rdata.read());
+                    CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read());
 
                     r_vci_rsp_fsm = RSP_IDLE;
-                    r_dcache_previous_unc = false;
-
-                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                    r_dcache_previous_unc[r_vci_rsp_num_cache] = false;
+
+                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true;
                 }
                 break;
@@ -2473,15 +3767,15 @@
             case RSP_DATA_SC:
                 m_cost_unc_transaction++;
-                if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack)
+                if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack)
                 {
                     ASSERT(p_vci_ini_rw.reop.read(),
                            "illegal VCI response packet for data SC");
 
-                    CACHE_MISS_BUF_RSP_PUSH(d,0,(data_t)p_vci_ini_rw.rdata.read());
+                    CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read());
 
                     r_vci_rsp_fsm = RSP_IDLE;
-                    r_dcache_previous_unc = false;
-
-                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                    r_dcache_previous_unc[r_vci_rsp_num_cache] = false;
+
+                    if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true;
                 }
                 break;
@@ -2489,5 +3783,5 @@
         } // end switch r_vci_rsp_fsm
 
-    } // end transition()
+   } // end transition()
 
     //////////////////////////////////////////////////////////////////////////////////
@@ -2495,36 +3789,67 @@
     //////////////////////////////////////////////////////////////////////////////////
     {
+        PRINTF("--------------------------------------------\n");
+        PRINTF("  * CC_XCACHE_WRAPPER \"%s\" genMoore - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles);
 
         // VCI initiator response
         switch ( r_cleanup_fsm.read() ) {
-
             case CLEANUP_IDLE:
                 p_vci_ini_c.rspack  = false;
-                p_vci_ini_c.cmdval  = r_icache_cleanup_req || r_dcache_cleanup_req;
-                if ( r_dcache_cleanup_req )
-                {
-                    p_vci_ini_c.address =  r_dcache_cleanup_line.read() * (m_dcache_words << 2);
-                    p_vci_ini_c.trdid   = TYPE_DATA_CLEANUP;
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata   = 0;
+                p_vci_ini_c.be      = 0;
+                p_vci_ini_c.plen    = 0;
+                p_vci_ini_c.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_c.trdid   = 0; 
+                p_vci_ini_c.pktid   = 0;
+                p_vci_ini_c.srcid   = 0;
+                p_vci_ini_c.cons    = false;
+                p_vci_ini_c.wrap    = false;
+                p_vci_ini_c.contig  = false;
+                p_vci_ini_c.clen    = 0;
+                p_vci_ini_c.cfixed  = false;
+                p_vci_ini_c.eop     = false;
+                break;
+
+            case CLEANUP_REQ:
+                {
+                addr_40 addr;
+                if (r_cleanup_icache)
+                {
+                    addr = r_icache_cleanup_line[r_cleanup_num_cache].read()<<m_icache_words_shift;
+                    set_num_icache(addr,r_cleanup_num_cache);
+
+                    PRINTF("      * <CLEANUP> icache             : %llx\n",(uint64_t)addr);
                 }
                 else
                 {
-                    p_vci_ini_c.address =  r_icache_cleanup_line.read() * (m_icache_words << 2); 
-                    p_vci_ini_c.trdid   = TYPE_INS_CLEANUP;
-                }
-                p_vci_ini_c.wdata  = 0;
-                p_vci_ini_c.be     = 0xF;
-                p_vci_ini_c.plen   = 4;
-                p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
-                p_vci_ini_c.pktid  = 0;
-                p_vci_ini_c.srcid  = m_srcid_c;
-                p_vci_ini_c.cons   = false;
-                p_vci_ini_c.wrap   = false;
-                p_vci_ini_c.contig = false;
-                p_vci_ini_c.clen   = 0;
-                p_vci_ini_c.cfixed = false;
-                p_vci_ini_c.eop    = true;
+                    addr = r_dcache_cleanup_line[r_cleanup_num_cache].read()<<m_dcache_words_shift;
+                    set_num_dcache(addr,r_cleanup_num_cache);
+
+                    PRINTF("      * <CLEANUP> dcache             : %llx\n",(uint64_t)addr);
+                }
+
+                p_vci_ini_c.rspack  = false;
+                p_vci_ini_c.cmdval  = true;
+                p_vci_ini_c.address = addr;
+                p_vci_ini_c.wdata   = 0;
+                p_vci_ini_c.be      = 0xF;
+                p_vci_ini_c.plen    = 4;
+                p_vci_ini_c.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_c.trdid   = (r_cleanup_icache)?TYPE_INS_CLEANUP:TYPE_DATA_CLEANUP;
+                p_vci_ini_c.pktid   = (sc_dt::sc_uint<vci_param::P>)r_cleanup_num_cache;
+                p_vci_ini_c.srcid   = m_srcid_c;
+                p_vci_ini_c.cons    = false;
+                p_vci_ini_c.wrap    = false;
+                p_vci_ini_c.contig  = false;
+                p_vci_ini_c.clen    = 0;
+                p_vci_ini_c.cfixed  = false;
+                p_vci_ini_c.eop     = true;
+
                 break;
-
-           case CLEANUP_DCACHE:
+                }
+
+           case CLEANUP_RSP_DCACHE:
                 p_vci_ini_c.rspack  = true;
                 p_vci_ini_c.cmdval  = false;
@@ -2545,5 +3870,5 @@
                 break;
 
-           case CLEANUP_ICACHE:
+           case CLEANUP_RSP_ICACHE:
                 p_vci_ini_c.rspack  = true;
                 p_vci_ini_c.cmdval  = false;
@@ -2568,6 +3893,6 @@
 
         switch (r_vci_cmd_fsm.read() ) {
-
             case CMD_IDLE:
+                {
                 p_vci_ini_rw.cmdval  = false;
                 p_vci_ini_rw.address = 0;
@@ -2587,12 +3912,19 @@
 
                 break;
-
+                }
             case CMD_DATA_UNC:
+                {
                 p_vci_ini_rw.cmdval = true;
-                p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
-                switch( r_dcache_type_save ) {
+
+                addr_40 addr = (addr_40) r_dcache_addr_save[r_vci_cmd_num_cache].read() & ~0x3;
+                set_num_dcache(addr,r_vci_cmd_num_cache);
+
+                PRINTF("      * <CMD> DATA_UNC   : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr));
+
+                p_vci_ini_rw.address = addr;
+                switch( r_dcache_type_save[r_vci_cmd_num_cache] ) {
                     case iss_t::DATA_READ:
                         p_vci_ini_rw.wdata = 0;
-                        p_vci_ini_rw.be  = r_dcache_be_save.read();
+                        p_vci_ini_rw.be  = r_dcache_be_save[r_vci_cmd_num_cache].read();
                         p_vci_ini_rw.cmd = vci_param::CMD_READ;
                         break;
@@ -2607,5 +3939,5 @@
                 p_vci_ini_rw.plen = 4;
                 p_vci_ini_rw.trdid  = TYPE_DATA_UNC;   // data cache uncached read
-                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.pktid  = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache;
                 p_vci_ini_rw.srcid  = m_srcid_rw;
                 p_vci_ini_rw.cons   = false;
@@ -2617,8 +3949,15 @@
 
                 break;
-
+                }
             case CMD_DATA_SC:
+                {
                 p_vci_ini_rw.cmdval = true;
-                p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
+
+                addr_40 addr = (addr_40) r_dcache_addr_save[r_vci_cmd_num_cache].read() & ~0x3;
+                set_num_dcache(addr,r_vci_cmd_num_cache);
+
+                PRINTF("      * <CMD> DATA_SC    : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr));
+
+                p_vci_ini_rw.address = addr;
                 if(r_vci_cmd_max.read() == 3){
                     ASSERT(false, "Not handled yet");
@@ -2626,8 +3965,8 @@
                     switch(r_vci_cmd_cpt.read()){
                         case 0:
-                            p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data.read() & 0xFFFFFFFF);
+                            p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data[r_vci_cmd_num_cache][r_dcache_num_cpu_save[r_vci_cmd_num_cache]].read() & 0xFFFFFFFF);
                             break;
                         case 1:
-                            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+                            p_vci_ini_rw.wdata = r_dcache_wdata_save[r_vci_cmd_num_cache].read();
                             break;
                     }
@@ -2637,5 +3976,5 @@
                 p_vci_ini_rw.plen   = 4*(r_vci_cmd_max.read()+1);
                 p_vci_ini_rw.trdid  = TYPE_DATA_SC;   // data cache uncached read
-                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.pktid  = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache;
                 p_vci_ini_rw.srcid  = m_srcid_rw;
                 p_vci_ini_rw.cons   = true;
@@ -2647,14 +3986,20 @@
 
                 break;
-
+                }
             case CMD_DATA_WRITE:
+                {
                 p_vci_ini_rw.cmdval  = true;
-                p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3;
-                p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
-                p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+
+                addr_40 addr       = (addr_40) r_wbuf[r_vci_cmd_num_cache]->getAddress(r_vci_cmd_cpt)&~0x3;
+
+                PRINTF("      * <CMD> DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr));
+
+                p_vci_ini_rw.address = addr;
+                p_vci_ini_rw.wdata   = r_wbuf[r_vci_cmd_num_cache]->getData(r_vci_cmd_cpt);
+                p_vci_ini_rw.be      = r_wbuf[r_vci_cmd_num_cache]->getBe(r_vci_cmd_cpt);
                 p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
                 p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
-                p_vci_ini_rw.trdid   = r_wbuf.getIndex() + (1<<(vci_param::T-1));
-                p_vci_ini_rw.pktid   = 0;
+                p_vci_ini_rw.trdid   = r_wbuf[r_vci_cmd_num_cache]->getIndex() + (1<<(vci_param::T-1));
+                p_vci_ini_rw.pktid   = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache;
                 p_vci_ini_rw.srcid   = m_srcid_rw;
                 p_vci_ini_rw.cons    = false;
@@ -2666,13 +4011,20 @@
 
                 break;
-
+                }
             case CMD_DATA_MISS:
+                {
                 p_vci_ini_rw.cmdval = true;
-                p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask;
+
+                addr_40 addr = r_dcache_addr_save[r_vci_cmd_num_cache].read() & (addr_40) m_dcache_yzmask;
+                set_num_dcache(addr,r_vci_cmd_num_cache);
+
+                PRINTF("      * <CMD> DATA_MISS  : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr));
+
+                p_vci_ini_rw.address = addr;
                 p_vci_ini_rw.be     = 0xF;
                 p_vci_ini_rw.plen   = m_dcache_words << 2;
                 p_vci_ini_rw.cmd    = vci_param::CMD_READ;
                 p_vci_ini_rw.trdid  = TYPE_DATA_MISS;   // data cache cached read
-                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.pktid  = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache;
                 p_vci_ini_rw.srcid  = m_srcid_rw;
                 p_vci_ini_rw.cons   = false;
@@ -2684,13 +4036,20 @@
 
                 break;
-
+                }
             case CMD_INS_MISS:
+                {
                 p_vci_ini_rw.cmdval = true;
-                p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask;
+
+                addr_40 addr = r_icache_addr_save[r_vci_cmd_num_cache].read() & (addr_40) m_icache_yzmask;
+                set_num_icache(addr,r_vci_cmd_num_cache);
+
+                PRINTF("      * <CMD> INS_MISS   : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr));
+
+                p_vci_ini_rw.address = addr;
                 p_vci_ini_rw.be     = 0xF;
                 p_vci_ini_rw.plen   = m_icache_words << 2;
                 p_vci_ini_rw.cmd    = vci_param::CMD_READ;
                 p_vci_ini_rw.trdid  = TYPE_INS_MISS;   // ins cache cached read
-                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.pktid  = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache;
                 p_vci_ini_rw.srcid  = m_srcid_rw;
                 p_vci_ini_rw.cons   = false;
@@ -2702,13 +4061,20 @@
 
                 break;
-
+                }
             case CMD_INS_UNC:
+                {
                 p_vci_ini_rw.cmdval = true;
-                p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3;
+
+                addr_40 addr = r_icache_addr_save[r_vci_cmd_num_cache].read() & ~0x3;
+                set_num_icache(addr,r_vci_cmd_num_cache);
+
+                PRINTF("      * <CMD> INS_UNC    : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr));
+
+                p_vci_ini_rw.address = addr;
                 p_vci_ini_rw.be     = 0xF;
                 p_vci_ini_rw.plen   = 4;
                 p_vci_ini_rw.cmd    = vci_param::CMD_READ;
                 p_vci_ini_rw.trdid  = TYPE_INS_UNC;   // ins cache uncached read
-                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.pktid  = (sc_dt::sc_uint<vci_param::P>)r_vci_cmd_num_cache;
                 p_vci_ini_rw.srcid  = m_srcid_rw;
                 p_vci_ini_rw.cons   = false;
@@ -2720,23 +4086,32 @@
 
                 break;
-
+                }
         } // end switch r_vci_cmd_fsm
 
-        bool ack;
-
-        switch (r_vci_rsp_fsm.read() ) {
-        case RSP_IDLE       : ack = false; break;
-        case RSP_DATA_WRITE : ack = true; break;
-        case RSP_INS_MISS   :
-        case RSP_INS_UNC    : ack = CACHE_MISS_BUF_RSP_ACK(i); break;
-        case RSP_DATA_MISS  :
-        case RSP_DATA_UNC   :
-        case RSP_DATA_SC    : ack = CACHE_MISS_BUF_RSP_ACK(d); break;
-        } // end switch r_vci_cmd_fsm
-
-        r_vci_rsp_ack       = ack;
-        p_vci_ini_rw.rspack = ack;
-        
+        {
+            bool ack;
+            
+            switch (r_vci_rsp_fsm.read() ) {
+            case RSP_DATA_WRITE : ack = true; break;
+            case RSP_INS_MISS   :
+            case RSP_INS_UNC    : ack = CACHE_MISS_BUF_RSP_ACK(i,r_vci_rsp_num_cache); break;
+            case RSP_DATA_MISS  :
+            case RSP_DATA_UNC   :
+            case RSP_DATA_SC    : ack = CACHE_MISS_BUF_RSP_ACK(d,r_vci_rsp_num_cache); break;
+                
+            case RSP_IDLE       :
+            default             : ack = false; break;
+                
+            } // end switch r_vci_cmd_fsm
+            
+            s_vci_rsp_ack       = ack;
+            p_vci_ini_rw.rspack = ack;
+
+            PRINTF("      * <RSP> rspack : %d\n", ack);
+        }
+
         // VCI_TGT
+
+        // PRINTF("      * <TGT> srcid : %d\n", r_tgt_srcid.read());
 
         switch ( r_vci_tgt_fsm.read() ) {
@@ -2750,36 +4125,68 @@
 
             case TGT_RSP_BROADCAST:
-                p_vci_tgt.cmdack  = false;
-                p_vci_tgt.rspval  = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() and ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
-                p_vci_tgt.rsrcid  = r_tgt_srcid.read();
-                p_vci_tgt.rpktid  = r_tgt_pktid.read();
-                p_vci_tgt.rtrdid  = r_tgt_trdid.read();
-                p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
-                p_vci_tgt.reop    = true;
-                break;
-
+                {
+                    bool tgt_icache_req;
+                    bool tgt_icache_rsp;
+
+#if   (CC_XCACHE_WRAPPER_MULTI_CACHE==1)
+                    tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read();
+                    tgt_icache_rsp = r_tgt_icache_rsp[r_tgt_num_cache].read();
+#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
+                    tgt_icache_req = false;
+                    tgt_icache_rsp = false;
+                    for (uint32_t num_cache=0; num_cache<m_nb_icache; ++num_cache)
+                    {
+                        tgt_icache_req |= r_tgt_icache_req[num_cache].read();
+                        tgt_icache_rsp |= r_tgt_icache_rsp[num_cache].read();
+                    }
+#endif
+
+                    bool rspval = ((not tgt_icache_req and not r_tgt_dcache_req[r_tgt_num_cache].read()) 
+                                   and (tgt_icache_rsp | r_tgt_dcache_rsp[r_tgt_num_cache]));
+
+                    PRINTF("      * <TGT> RSP_BROADCAST : rspval : %d (i %d %d, d %d %d)\n",rspval,tgt_icache_req,tgt_icache_rsp, r_tgt_dcache_req[r_tgt_num_cache].read(), r_tgt_dcache_rsp[r_tgt_num_cache].read());
+                    
+                    p_vci_tgt.cmdack  = false;
+                    p_vci_tgt.rspval  = rspval;
+                    p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+                    p_vci_tgt.rpktid  = r_tgt_pktid.read();
+                    p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+                    p_vci_tgt.rdata   = 0;
+                    p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+                    p_vci_tgt.reop    = true;
+                    break;
+                }
             case TGT_RSP_ICACHE:
-                p_vci_tgt.cmdack  = false;
-                p_vci_tgt.rspval  = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
-                p_vci_tgt.rsrcid  = r_tgt_srcid.read();
-                p_vci_tgt.rpktid  = r_tgt_pktid.read();
-                p_vci_tgt.rtrdid  = r_tgt_trdid.read();
-                p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
-                p_vci_tgt.reop    = true;
-                break;
-
+                {
+                    bool rspval = not r_tgt_icache_req[r_tgt_num_cache].read() and r_tgt_icache_rsp[r_tgt_num_cache].read();
+
+                    PRINTF("      * <TGT> RSP_ICACHE : rspval : %d\n",rspval);
+
+                    p_vci_tgt.cmdack  = false;
+                    p_vci_tgt.rspval  = rspval;
+                    p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+                    p_vci_tgt.rpktid  = r_tgt_pktid.read();
+                    p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+                    p_vci_tgt.rdata   = 0;
+                    p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+                    p_vci_tgt.reop    = true;
+                    break;
+                }
             case TGT_RSP_DCACHE:
-                p_vci_tgt.cmdack  = false;
-                p_vci_tgt.rspval  = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
-                p_vci_tgt.rsrcid  = r_tgt_srcid.read();
-                p_vci_tgt.rpktid  = r_tgt_pktid.read();
-                p_vci_tgt.rtrdid  = r_tgt_trdid.read();
-                p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
-                p_vci_tgt.reop    = true;
-                break;
-
+                {
+                    bool rspval = not r_tgt_dcache_req[r_tgt_num_cache].read() and r_tgt_dcache_rsp[r_tgt_num_cache].read();
+
+                    PRINTF("      * <TGT> RSP_DCACHE : rspval : %d\n",rspval);
+                    
+                    p_vci_tgt.cmdack  = false;
+                    p_vci_tgt.rspval  = rspval;
+                    p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+                    p_vci_tgt.rpktid  = r_tgt_pktid.read();
+                    p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+                    p_vci_tgt.rdata   = 0;
+                    p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+                    p_vci_tgt.reop    = true;
+                    break;
+                }
             case TGT_REQ_BROADCAST:
             case TGT_REQ_ICACHE:
@@ -2814,4 +4221,43 @@
     }
 
+    //////////////////////////////////////////////////////////////////////////////////
+    tmpl(uint32_t)::get_num_cache(addr_40 & addr)
+    //////////////////////////////////////////////////////////////////////////////////
+    {
+        uint32_t num_cache = get_num_cache_only(addr);
+
+        addr = ((addr&m_num_cache_LSB_mask) | // keep LSB
+                ((addr>>m_num_cache_MSB)<<m_num_cache_LSB)); // set MSB
+
+        return num_cache;
+    }
+
+    //////////////////////////////////////////////////////////////////////////////////
+    tmpl(uint32_t)::get_num_cache_only(addr_40 addr)
+    //////////////////////////////////////////////////////////////////////////////////
+    {
+        return (addr>>m_num_cache_LSB)&m_num_cache_mask;
+    }
+
+    //////////////////////////////////////////////////////////////////////////////////
+    tmpl(void)::set_num_cache(addr_40 & addr, uint32_t num_cache)
+    //////////////////////////////////////////////////////////////////////////////////
+    {
+        addr = ((addr&m_num_cache_LSB_mask) | // keep LSB
+                ((addr_40)num_cache << m_num_cache_LSB) |
+                ((addr>>m_num_cache_LSB)<<m_num_cache_MSB)); // set MSB
+    }
+
+    //////////////////////////////////////////////////////////////////////////////////
+    // fixme : mettre le type addr_40
+    tmpl(sc_dt::sc_uint<40>)::set_num_cache_only(addr_40 addr, uint32_t num_cache) 
+    //////////////////////////////////////////////////////////////////////////////////
+    {
+        return ((addr&m_num_cache_LSB_mask) | // keep LSB
+                ((addr_40)num_cache << m_num_cache_LSB) |
+                ((addr>>m_num_cache_LSB)<<m_num_cache_MSB)); // set MSB
+    }
+
+
 }} // end namespace
 
