Changeset 140 for trunk/modules/vci_mem_cache_v4/caba/source
- Timestamp:
- Mar 9, 2011, 4:11:43 PM (14 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source
- Files:
-
- 3 edited
-
include/mem_cache_directory_v4.h (modified) (10 diffs)
-
include/vci_mem_cache_v4.h (modified) (9 diffs)
-
src/vci_mem_cache_v4.cpp (modified) (93 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
r57 r140 6 6 #include <cassert> 7 7 #include "arithmetics.h" 8 9 #define L1_MULTI_CACHE 1 8 10 9 11 namespace soclib { namespace caba { … … 37 39 bool inst; // Is the owner an ICache ? 38 40 size_t srcid; // The SRCID of the owner 41 #if L1_MULTI_CACHE 42 size_t cache_id; // In multi_cache configuration 43 #endif 39 44 40 45 //////////////////////// 41 46 // Constructors 42 47 //////////////////////// 43 Owner(bool i_inst,size_t i_srcid){ 48 Owner(bool i_inst 49 ,size_t i_srcid 50 #if L1_MULTI_CACHE 51 ,size_t i_cache_id 52 #endif 53 ){ 44 54 inst = i_inst; 45 55 srcid = i_srcid; 56 #if L1_MULTI_CACHE 57 cache_id= i_cache_id; 58 #endif 46 59 } 47 60 … … 49 62 inst = a.inst; 50 63 srcid = a.srcid; 64 #if L1_MULTI_CACHE 65 cache_id= a.cache_id; 66 #endif 51 67 } 52 68 … … 54 70 inst = false; 55 71 srcid = 0; 72 #if L1_MULTI_CACHE 73 cache_id= 0; 74 #endif 56 75 } 57 76 // end constructors … … 89 108 owner.inst = 0; 90 109 owner.srcid = 0; 110 #if L1_MULTI_CACHE 111 owner.cache_id= 0; 112 #endif 91 113 ptr = 0; 92 114 } … … 137 159 { 138 160 std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 139 << lock << " ; Tag = " << std::hex << tag << std::dec << " ; Count = " << count << " ; Owner = " << owner.srcid << " " << owner.inst << " ; Pointer = " << ptr << std::endl; 161 << lock 162 << " ; Tag = " << std::hex << tag << std::dec 163 << " ; Count = " << count 164 << " ; Owner = " << owner.srcid 165 #if L1_MULTI_CACHE 166 << "." << owner.cache_id 167 #endif 168 << " " << owner.inst 169 << " ; Pointer = " << ptr << std::endl; 140 170 } 141 171 … … 346 376 //////////////////////// 347 377 HeapEntry() 348 :owner(false,0) 378 :owner(false,0 379 #if L1_MULTI_CACHE 380 ,0 381 #endif 382 ) 349 383 { 350 384 next = 0; … … 355 389 //////////////////////// 356 390 HeapEntry(const HeapEntry &entry){ 391 owner.inst = entry.owner.inst; 357 392 owner.srcid = entry.owner.srcid; 358 owner.inst = entry.owner.inst; 359 next = entry.next; 393 #if L1_MULTI_CACHE 394 owner.cache_id = entry.owner.cache_id; 395 #endif 396 next = entry.next; 360 397 } // end constructor 361 398 … … 364 401 ///////////////////////////////////////////////////////////////////// 365 402 void copy(const HeapEntry &entry){ 366 owner.srcid = entry.owner.srcid; 367 owner.inst = entry.owner.inst; 368 next = entry.next; 403 owner.inst = entry.owner.inst; 404 owner.srcid = entry.owner.srcid; 405 #if L1_MULTI_CACHE 406 owner.cache_id = entry.owner.cache_id; 407 #endif 408 next = entry.next; 369 409 } // end copy() 370 410 … … 374 414 void print(){ 375 415 std::cout 376 << " -- owner.srcid : " << std::dec << owner.srcid << std::endl 377 << " -- owner.inst : " << std::dec << owner.inst << std::endl 378 << " -- next : " << std::dec << next << std::endl; 416 << " -- owner.inst : " << std::dec << owner.inst << std::endl 417 << " -- owner.srcid : " << std::dec << owner.srcid << std::endl 418 #if L1_MULTI_CACHE 419 << " -- owner.cache_id : " << std::dec << owner.cache_id << std::endl 420 #endif 421 << " -- next : " << std::dec << next << std::endl; 379 422 380 423 } // end print() -
trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r138 r140 405 405 sc_signal<int> r_read_fsm; // FSM state 406 406 sc_signal<size_t> r_read_copy; // Srcid of the first copy 407 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 407 408 sc_signal<bool> r_read_copy_inst; // Type of the first copy 408 409 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) … … 450 451 sc_signal<tag_t> r_write_tag; // cache line tag (in directory) 451 452 sc_signal<size_t> r_write_copy; // first owner of the line 453 sc_signal<size_t> r_write_copy_cache; // first owner of the line 452 454 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? 453 455 sc_signal<size_t> r_write_count; // number of copies … … 483 485 GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type 484 486 GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids 487 GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids 485 488 486 489 // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) … … 516 519 517 520 sc_signal<copy_t> r_cleanup_copy; // first copy 521 sc_signal<copy_t> r_cleanup_copy_cache; // first copy 518 522 sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy 519 523 sc_signal<copy_t> r_cleanup_count; // number of copies … … 521 525 sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap 522 526 sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry 527 sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry 523 528 sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry 524 529 sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap … … 552 557 sc_signal<size_t> r_llsc_cpt; // size of command 553 558 sc_signal<copy_t> r_llsc_copy; // Srcid of the first copy 559 sc_signal<copy_t> r_llsc_copy_cache; // Srcid of the first copy 554 560 sc_signal<bool> r_llsc_copy_inst; // Type of the first copy 555 561 sc_signal<size_t> r_llsc_count; // number of copies … … 590 596 GenericFifo<bool> m_llsc_to_init_cmd_inst_fifo; // fifo for the L1 type 591 597 GenericFifo<size_t> m_llsc_to_init_cmd_srcid_fifo; // fifo for srcids 598 GenericFifo<size_t> m_llsc_to_init_cmd_cache_id_fifo;// fifo for srcids 592 599 593 600 // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry) … … 620 627 sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index 621 628 sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy 629 sc_signal<copy_t> r_xram_rsp_victim_copy_cache;// victim line first copy 622 630 sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy 623 631 sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies … … 644 652 GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type 645 653 GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids 654 GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids 646 655 647 656 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) -
trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
r138 r140 29 29 #include "../include/vci_mem_cache_v4.h" 30 30 31 //#define TDEBUG // Transaction tab debug 32 //#define IDEBUG // Update tab debug 33 //#define DDEBUG // Directory debug 34 //#define LOCK_DEBUG // Lock debug 31 // #define TDEBUG // Transaction tab debug 32 // #define IDEBUG // Update tab debug 33 // #define DDEBUG // Directory debug 34 // #define LOCK_DEBUG // Lock debug 35 35 36 #define DEBUG_VCI_MEM_CACHE 0 36 #define DEBUG_START_CYCLE 20000037 #define DEBUG_START_CYCLE 949900 37 38 #define RANDOMIZE_SC 38 39 40 #define ASSERT_VERBOSE 41 #define ASSERT_NCYCLES m_cpt_cycles 42 43 #include "debug.h" 44 39 45 #if DEBUG_VCI_MEM_CACHE 40 # define PRINTF(msg...) do { if (m_cpt_cycles > DEBUG_START_CYCLE) printf(msg); } while (0);46 # define PRINTF(msg...) PRINTF_COND(m_cpt_cycles > DEBUG_START_CYCLE,msg) 41 47 #else 42 48 # define PRINTF(msg...) … … 301 307 m_write_to_init_cmd_inst_fifo("m_write_to_init_cmd_inst_fifo",8), 302 308 m_write_to_init_cmd_srcid_fifo("m_write_to_init_cmd_srcid_fifo",8), 309 #if L1_MULTI_CACHE 310 m_write_to_init_cmd_cache_id_fifo("m_write_to_init_cmd_cache_id_fifo",8), 311 #endif 303 312 r_init_rsp_fsm("r_init_rsp_fsm"), 304 313 r_cleanup_fsm("r_cleanup_fsm"), … … 306 315 m_llsc_to_init_cmd_inst_fifo("m_llsc_to_init_cmd_inst_fifo",8), 307 316 m_llsc_to_init_cmd_srcid_fifo("m_llsc_to_init_cmd_srcid_fifo",8), 317 #if L1_MULTI_CACHE 318 m_llsc_to_init_cmd_cache_id_fifo("m_llsc_to_init_cmd_cache_id_fifo",8), 319 #endif 308 320 r_ixr_rsp_fsm("r_ixr_rsp_fsm"), 309 321 r_xram_rsp_fsm("r_xram_rsp_fsm"), 310 322 m_xram_rsp_to_init_cmd_inst_fifo("m_xram_rsp_to_init_cmd_inst_fifo",8), 311 323 m_xram_rsp_to_init_cmd_srcid_fifo("m_xram_rsp_to_init_cmd_srcid_fifo",8), 324 #if L1_MULTI_CACHE 325 m_xram_rsp_to_init_cmd_cache_id_fifo("m_xram_rsp_to_init_cmd_cache_id_fifo",8), 326 #endif 312 327 r_ixr_cmd_fsm("r_ixr_cmd_fsm"), 313 328 r_tgt_rsp_fsm("r_tgt_rsp_fsm"), … … 532 547 m_write_to_init_cmd_inst_fifo.init(); 533 548 m_write_to_init_cmd_srcid_fifo.init(); 549 #if L1_MULTI_CACHE 550 m_write_to_init_cmd_cache_id_fifo.init(); 551 #endif 534 552 535 553 r_cleanup_to_tgt_rsp_req = false; … … 545 563 m_llsc_to_init_cmd_inst_fifo.init(); 546 564 m_llsc_to_init_cmd_srcid_fifo.init(); 565 #if L1_MULTI_CACHE 566 m_llsc_to_init_cmd_cache_id_fifo.init(); 567 #endif 547 568 548 569 for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){ … … 557 578 m_xram_rsp_to_init_cmd_inst_fifo.init(); 558 579 m_xram_rsp_to_init_cmd_srcid_fifo.init(); 580 #if L1_MULTI_CACHE 581 m_xram_rsp_to_init_cmd_cache_id_fifo.init(); 582 #endif 559 583 560 584 r_ixr_cmd_cpt = 0; … … 591 615 bool cmd_llsc_fifo_get = false; 592 616 593 bool write_to_init_cmd_fifo_put = false; 594 bool write_to_init_cmd_fifo_get = false; 595 bool write_to_init_cmd_fifo_inst = false; 596 size_t write_to_init_cmd_fifo_srcid = 0; 597 598 bool xram_rsp_to_init_cmd_fifo_put = false; 599 bool xram_rsp_to_init_cmd_fifo_get = false; 600 bool xram_rsp_to_init_cmd_fifo_inst = false; 601 size_t xram_rsp_to_init_cmd_fifo_srcid = 0; 602 603 bool llsc_to_init_cmd_fifo_put = false; 604 bool llsc_to_init_cmd_fifo_get = false; 605 bool llsc_to_init_cmd_fifo_inst = false; 606 size_t llsc_to_init_cmd_fifo_srcid = 0; 617 bool write_to_init_cmd_fifo_put = false; 618 bool write_to_init_cmd_fifo_get = false; 619 bool write_to_init_cmd_fifo_inst = false; 620 size_t write_to_init_cmd_fifo_srcid = 0; 621 #if L1_MULTI_CACHE 622 size_t write_to_init_cmd_fifo_cache_id = 0; 623 #endif 624 625 bool xram_rsp_to_init_cmd_fifo_put = false; 626 bool xram_rsp_to_init_cmd_fifo_get = false; 627 bool xram_rsp_to_init_cmd_fifo_inst = false; 628 size_t xram_rsp_to_init_cmd_fifo_srcid = 0; 629 #if L1_MULTI_CACHE 630 size_t xram_rsp_to_init_cmd_fifo_cache_id = 0; 631 #endif 632 633 bool llsc_to_init_cmd_fifo_put = false; 634 bool llsc_to_init_cmd_fifo_get = false; 635 bool llsc_to_init_cmd_fifo_inst = false; 636 size_t llsc_to_init_cmd_fifo_srcid = 0; 637 #if L1_MULTI_CACHE 638 size_t llsc_to_init_cmd_fifo_cache_id = 0; 639 #endif 607 640 608 641 #if DEBUG_VCI_MEM_CACHE … … 628 661 #endif 629 662 663 #ifdef IDEBUG 664 if(m_cpt_cycles > DEBUG_START_CYCLE){ 665 std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl; 666 m_update_tab.print(); 667 } 668 #endif 669 630 670 //////////////////////////////////////////////////////////////////////////////////// 631 671 // TGT_CMD FSM … … 651 691 if ( p_vci_tgt.cmdval ) { 652 692 653 PRINTF(" * < TGT> Request from %d at address %llx\n",(uint32_t)p_vci_tgt.srcid.read(),(uint64_t)p_vci_tgt.address.read());693 PRINTF(" * <MEM_CACHE.TGT> Request from %d.%d (%d) at address %llx\n",(uint32_t)p_vci_tgt.srcid.read(),(uint32_t)p_vci_tgt.pktid.read(),(uint32_t)p_vci_tgt.trdid.read(),(uint64_t)p_vci_tgt.address.read()); 654 694 655 695 if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) … … 676 716 677 717 { 678 assert(((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2))<=16)679 &&"VCI_MEM_CACHE All read request to the MemCache must stay within a cache line");718 ASSERT(((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2))<=16), 719 "VCI_MEM_CACHE All read request to the MemCache must stay within a cache line"); 680 720 681 721 if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) { … … 744 784 745 785 if ( p_vci_ini.rspval ) { 746 747 assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() ) 748 && "VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" ); 749 assert ( p_vci_ini.reop 750 && "VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell" ); 786 PRINTF(" * <MEM_CACHE.INIT_RSP> rsp val - trdid %d\n",(uint32_t)p_vci_ini.rtrdid.read()); 787 788 ASSERT (( p_vci_ini.rtrdid.read() < m_update_tab.size()) 789 ,"VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" ); 790 ASSERT (p_vci_ini.reop 791 ,"VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell") ; 751 792 r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 752 793 r_init_rsp_fsm = INIT_RSP_UPT_LOCK; … … 772 813 #endif 773 814 while(!valid); 774 assert( valid775 &&"VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );815 ASSERT ( valid 816 ,"VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" ); 776 817 777 818 if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR; … … 830 871 //////////////////////////////////////////////////////////////////////////////////// 831 872 832 PRINTF(" * TOP : Request from %d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read());873 PRINTF(" * <MEM_CACHE.TOP> Request from %d.%d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint32_t)m_cmd_read_pktid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read()); 833 874 834 875 switch ( r_read_fsm.read() ) { … … 838 879 { 839 880 if (m_cmd_read_addr_fifo.rok()) { 840 PRINTF(" * < READ> Request from %d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read());881 PRINTF(" * <MEM_CACHE.READ> Request from %d.%d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint32_t)m_cmd_read_pktid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read()); 841 882 842 883 m_cpt_read++; … … 858 899 } 859 900 #endif 860 r_read_is_cnt = entry.is_cnt; 861 r_read_dirty = entry.dirty; 862 r_read_lock = entry.lock; 863 r_read_tag = entry.tag; 864 r_read_way = way; 865 r_read_count = entry.count; 866 r_read_copy = entry.owner.srcid; 867 r_read_copy_inst= entry.owner.inst; 868 r_read_ptr = entry.ptr; 901 r_read_is_cnt = entry.is_cnt; 902 r_read_dirty = entry.dirty; 903 r_read_lock = entry.lock; 904 r_read_tag = entry.tag; 905 r_read_way = way; 906 r_read_count = entry.count; 907 r_read_copy = entry.owner.srcid; 908 #if L1_MULTI_CACHE 909 r_read_copy_cache = entry.owner.cache_id; 910 #endif 911 r_read_copy_inst = entry.owner.inst; 912 r_read_ptr = entry.ptr; 869 913 870 914 bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1); … … 910 954 if(!is_cnt){ // Not counter mode 911 955 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 956 #if L1_MULTI_CACHE 957 entry.owner.cache_id= m_cmd_read_pktid_fifo.read(); 958 #endif 959 912 960 entry.owner.inst = inst_read; 913 961 entry.count = r_read_count.read() + 1; 914 962 } else { // Counter mode 915 963 entry.owner.srcid = 0; 964 #if L1_MULTI_CACHE 965 entry.owner.cache_id= 0; 966 #endif 916 967 entry.owner.inst = false; 917 968 entry.count = r_read_count.read() + 1; … … 919 970 } else { // Uncached read 920 971 entry.owner.srcid = r_read_copy.read(); 972 #if L1_MULTI_CACHE 973 entry.owner.cache_id = r_read_copy_cache.read(); 974 #endif 975 921 976 entry.owner.inst = r_read_copy_inst.read(); 922 977 entry.count = r_read_count.read(); … … 956 1011 if(!is_cnt){ // Not counter mode 957 1012 entry.owner.srcid = r_read_copy.read(); 1013 #if L1_MULTI_CACHE 1014 entry.owner.cache_id= r_read_copy_cache.read(); 1015 #endif 958 1016 entry.owner.inst = r_read_copy_inst.read(); 959 1017 entry.count = r_read_count.read() + 1; … … 961 1019 } else { // Counter mode 962 1020 entry.owner.srcid = 0; 1021 #if L1_MULTI_CACHE 1022 entry.owner.cache_id= 0; 1023 #endif 963 1024 entry.owner.inst = false; 964 1025 entry.count = r_read_count.read() + 1; … … 1008 1069 bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2); 1009 1070 HeapEntry new_heap_entry; 1010 new_heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 1011 new_heap_entry.owner.inst = inst_read; 1071 new_heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 1072 #if L1_MULTI_CACHE 1073 new_heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); 1074 #endif 1075 new_heap_entry.owner.inst = inst_read; 1012 1076 if(r_read_count.read() == 1){ // creation of a new list 1013 1077 new_heap_entry.next = m_heap_directory.next_free_ptr(); … … 1023 1087 r_read_fsm = READ_RSP; 1024 1088 } else { 1025 assert(false &&"MEMCACHE Error : Bad HEAP allocation");1089 ASSERT(false,"MEMCACHE Error : Bad HEAP allocation"); 1026 1090 } 1027 1091 break; … … 1039 1103 } 1040 1104 } else { 1041 assert(false &&"MEMCACHE Error : Bad HEAP allocation");1105 ASSERT(false,"MEMCACHE Error : Bad HEAP allocation"); 1042 1106 } 1043 1107 break; … … 1048 1112 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){ 1049 1113 HeapEntry last_entry; 1050 last_entry.owner.srcid = 0; 1051 last_entry.owner.inst = false; 1114 last_entry.owner.srcid = 0; 1115 #if L1_MULTI_CACHE 1116 last_entry.owner.cache_id = 0; 1117 #endif 1118 last_entry.owner.inst = false; 1052 1119 if(m_heap_directory.is_full()){ 1053 1120 last_entry.next = r_read_ptr.read(); … … 1059 1126 r_read_fsm = READ_RSP; 1060 1127 } else { 1061 assert(false &&"MEMCACHE Error : Bad HEAP allocation");1128 ASSERT(false,"MEMCACHE Error : Bad HEAP allocation"); 1062 1129 } 1063 1130 break; … … 1107 1174 { 1108 1175 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) { 1109 m_transaction_tab.set(r_read_trt_index.read(),1176 m_transaction_tab.set(r_read_trt_index.read(), 1110 1177 true, 1111 1178 m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], … … 1178 1245 { 1179 1246 if ( m_cmd_write_addr_fifo.rok()) { 1247 PRINTF(" * <MEM_CACHE.WRITE> KANE Request from %d.%d (%d) at address %llx\n",(uint32_t)m_cmd_write_srcid_fifo.read(),(uint32_t)m_cmd_write_pktid_fifo.read(),(uint32_t) m_cmd_write_trdid_fifo.read(), (uint64_t)m_cmd_write_addr_fifo.read()); 1248 1180 1249 m_cpt_write++; 1181 1250 m_cpt_write_cells++; … … 1212 1281 1213 1282 // check that the next word is in the same cache line 1214 assert( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())])1215 &&"VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" );1283 ASSERT( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())]) 1284 ,"VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" ); 1216 1285 // consume a word in the FIFO & write it in the local buffer 1217 1286 cmd_write_fifo_get=true; … … 1239 1308 r_write_tag = entry.tag; 1240 1309 r_write_copy = entry.owner.srcid; 1310 #if L1_MULTI_CACHE 1311 r_write_copy_cache= entry.owner.cache_id; 1312 #endif 1241 1313 r_write_copy_inst = entry.owner.inst; 1242 1314 r_write_count = entry.count; … … 1287 1359 // update directory with Dirty bit 1288 1360 DirectoryEntry entry; 1289 entry.valid = true; 1290 entry.dirty = true; 1291 entry.tag = r_write_tag.read(); 1292 entry.is_cnt = r_write_is_cnt.read(); 1293 entry.lock = r_write_lock.read(); 1294 entry.owner.srcid = r_write_copy.read(); 1295 entry.owner.inst = r_write_copy_inst.read(); 1296 entry.count = r_write_count.read(); 1297 entry.ptr = r_write_ptr.read(); 1298 size_t set = m_y[(vci_addr_t)(r_write_address.read())]; 1299 size_t way = r_write_way.read(); 1361 entry.valid = true; 1362 entry.dirty = true; 1363 entry.tag = r_write_tag.read(); 1364 entry.is_cnt = r_write_is_cnt.read(); 1365 entry.lock = r_write_lock.read(); 1366 entry.owner.srcid = r_write_copy.read(); 1367 #if L1_MULTI_CACHE 1368 entry.owner.cache_id= r_write_copy_cache.read(); 1369 #endif 1370 entry.owner.inst = r_write_copy_inst.read(); 1371 entry.count = r_write_count.read(); 1372 entry.ptr = r_write_ptr.read(); 1373 size_t set = m_y[(vci_addr_t)(r_write_address.read())]; 1374 size_t way = r_write_way.read(); 1300 1375 m_cache_directory.write(set, way, entry); 1301 1376 1302 bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read(); 1377 bool owner = (((r_write_copy.read()==r_write_srcid.read()) 1378 #if L1_MULTI_CACHE 1379 and (r_write_copy_cache.read()==r_write_pktid.read()) 1380 #endif 1381 ) and not r_write_copy_inst.read()); 1382 1303 1383 bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1)); 1304 1384 … … 1387 1467 case WRITE_UPT_REQ: 1388 1468 { 1389 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&1390 1469 ASSERT( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) 1470 ,"MemCache ERROR : bad HEAP allocation"); 1391 1471 if( !r_write_to_init_cmd_multi_req.read() && 1392 1472 !r_write_to_init_cmd_brdcast_req.read() ){ … … 1407 1487 } 1408 1488 1409 if( (r_write_copy.read() != r_write_srcid.read()) || r_write_copy_inst.read() ) { 1489 if((r_write_copy.read() != r_write_srcid.read()) or 1490 #if L1_MULTI_CACHE 1491 (r_write_copy_cache.read() != r_write_pktid.read()) or 1492 #endif 1493 r_write_copy_inst.read() ) { 1410 1494 // We put the first copy in the fifo 1411 1495 write_to_init_cmd_fifo_put = true; 1412 1496 write_to_init_cmd_fifo_inst = r_write_copy_inst.read(); 1413 1497 write_to_init_cmd_fifo_srcid = r_write_copy.read(); 1498 #if L1_MULTI_CACHE 1499 write_to_init_cmd_fifo_cache_id= r_write_copy_cache.read(); 1500 #endif 1414 1501 if(r_write_count.read() == 1){ 1415 1502 r_write_fsm = WRITE_IDLE; … … 1427 1514 case WRITE_UPDATE: // send a multi-update request to INIT_CMD fsm 1428 1515 { 1429 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&1430 1516 ASSERT( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) 1517 ,"MemCache ERROR : bad HEAP allocation"); 1431 1518 HeapEntry entry = m_heap_directory.read(r_write_ptr.read()); 1432 write_to_init_cmd_fifo_inst = entry.owner.inst; 1433 write_to_init_cmd_fifo_srcid = entry.owner.srcid; 1519 write_to_init_cmd_fifo_inst = entry.owner.inst; 1520 write_to_init_cmd_fifo_srcid = entry.owner.srcid; 1521 #if L1_MULTI_CACHE 1522 write_to_init_cmd_fifo_cache_id = entry.owner.cache_id; 1523 #endif 1524 1434 1525 bool dec_upt_counter = r_write_to_dec.read(); 1435 if( (entry.owner.srcid != r_write_srcid.read()) || entry.owner.inst ){ 1526 if( (entry.owner.srcid != r_write_srcid.read()) or 1527 #if L1_MULTI_CACHE 1528 (entry.owner.cache_id != r_write_pktid.read()) or 1529 #endif 1530 entry.owner.inst){ 1436 1531 write_to_init_cmd_fifo_put = true; 1437 1532 } else { … … 1471 1566 { 1472 1567 if ( !r_write_to_tgt_rsp_req.read() ) { 1568 1569 PRINTF(" * <MEM_CACHE.WRITE> YURI Request from %d.%d (%d)\n",(uint32_t)r_write_srcid.read(), (uint32_t)r_write_trdid.read(), (uint32_t)r_write_pktid.read()); 1570 1473 1571 r_write_to_tgt_rsp_req = true; 1474 1572 r_write_to_tgt_rsp_srcid = r_write_srcid.read(); … … 1644 1742 case WRITE_DIR_INVAL: 1645 1743 { 1646 assert(((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) &&1744 ASSERT(((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) && 1647 1745 (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) && 1648 (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE )) &&1649 1746 (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE )) 1747 ,"MemCache ERROR : bad TRT,DIR or UPT allocation error"); 1650 1748 m_transaction_tab.set(r_write_trt_index.read(), 1651 1749 false, // write request to XRAM … … 1675 1773 entry.lock = false; 1676 1774 entry.owner.srcid = 0; 1775 #if L1_MULTI_CACHE 1776 entry.owner.cache_id= 0; 1777 #endif 1677 1778 entry.owner.inst = false; 1678 1779 entry.ptr = 0; … … 1890 1991 data_t data = p_vci_ixr.rdata.read(); 1891 1992 size_t index = r_ixr_rsp_trt_index.read(); 1892 assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) ||1893 1894 &&"Error in VCI_MEM_CACHE : invalid length for a response from XRAM");1993 ASSERT(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || 1994 p_vci_ixr.rerror.read()) 1995 ,"Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); 1895 1996 m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data, p_vci_ixr.rerror.read()&0x1); 1896 1997 r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1; … … 1988 2089 1989 2090 r_xram_rsp_victim_copy = victim.owner.srcid; 2091 #if L1_MULTI_CACHE 2092 r_xram_rsp_victim_copy_cache= victim.owner.cache_id; 2093 #endif 1990 2094 r_xram_rsp_victim_copy_inst = victim.owner.inst; 1991 2095 r_xram_rsp_victim_count = victim.count; … … 2005 2109 if(m_cpt_cycles > DEBUG_START_CYCLE){ 2006 2110 std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl; 2007 std::cout << "Victim way : " << std::hex << way << " set " << s td::hex << set<< std::endl;2111 std::cout << "Victim way : " << std::hex << way << " set " << set << std::dec << std::endl; 2008 2112 victim.print(); 2009 2113 } … … 2093 2197 entry.ptr = 0; 2094 2198 if(cached_read) { 2095 if(inst_read) { 2096 entry.owner.srcid = r_xram_rsp_trt_buf.srcid; 2097 entry.owner.inst = true; 2098 entry.count = 1; 2099 } else { 2100 entry.owner.srcid = r_xram_rsp_trt_buf.srcid; 2101 entry.owner.inst = false; 2102 entry.count = 1; 2103 } 2199 entry.owner.srcid = r_xram_rsp_trt_buf.srcid; 2200 #if L1_MULTI_CACHE 2201 entry.owner.cache_id= r_xram_rsp_trt_buf.pktid; 2202 #endif 2203 entry.owner.inst = inst_read; 2204 entry.count = 1; 2104 2205 } else { 2105 entry.owner.srcid = 0; 2106 entry.owner.inst = 0; 2107 entry.count = 0; 2206 entry.owner.srcid = 0; 2207 #if L1_MULTI_CACHE 2208 entry.owner.cache_id = 0; 2209 #endif 2210 entry.owner.inst = 0; 2211 entry.count = 0; 2108 2212 } 2109 2213 m_cache_directory.write(set, way, entry); … … 2125 2229 2126 2230 if(r_xram_rsp_victim_inval.read()){ 2127 bool 2128 size_t index ;2231 bool brdcast = r_xram_rsp_victim_is_cnt.read(); 2232 size_t index = 0; 2129 2233 size_t count_copies = r_xram_rsp_victim_count.read(); 2130 2234 2235 //@@ 2131 2236 bool wok = m_update_tab.set(false, // it's an inval transaction 2132 2237 brdcast, // set brdcast bit 2133 2238 false, // it does not need a response 2134 0, 2135 0, 2136 0, 2239 0,//srcid 2240 0,//trdid 2241 0,//pktid 2137 2242 r_xram_rsp_victim_nline.read(), 2138 2243 count_copies, … … 2147 2252 r_xram_rsp_upt_index = index; 2148 2253 if(!wok) { 2149 assert(false &&"mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful");2254 ASSERT(false,"mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful"); 2150 2255 } 2151 2256 } … … 2234 2339 xram_rsp_to_init_cmd_fifo_srcid = r_xram_rsp_victim_copy.read(); 2235 2340 xram_rsp_to_init_cmd_fifo_inst = r_xram_rsp_victim_copy_inst.read(); 2341 #if L1_MULTI_CACHE 2342 xram_rsp_to_init_cmd_fifo_cache_id = r_xram_rsp_victim_copy_cache.read(); 2343 #endif 2236 2344 xram_rsp_to_init_cmd_fifo_put = multi_req; 2237 2345 … … 2277 2385 if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP ) { 2278 2386 HeapEntry entry = m_heap_directory.read(r_xram_rsp_next_ptr.read()); 2279 xram_rsp_to_init_cmd_fifo_srcid = entry.owner.srcid; 2387 xram_rsp_to_init_cmd_fifo_srcid = entry.owner.srcid; 2388 #if L1_MULTI_CACHE 2389 xram_rsp_to_init_cmd_fifo_cache_id = entry.owner.cache_id; 2390 #endif 2280 2391 xram_rsp_to_init_cmd_fifo_inst = entry.owner.inst; 2281 2392 xram_rsp_to_init_cmd_fifo_put = true; … … 2297 2408 case XRAM_RSP_HEAP_LAST: // last member of the list 2298 2409 { 2299 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) &&2300 2410 ASSERT((r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) 2411 ,"MemCache ERROR : bad HEAP allocation"); 2301 2412 size_t free_pointer = m_heap_directory.next_free_ptr(); 2302 2413 2303 2414 HeapEntry last_entry; 2304 last_entry.owner.srcid = 0; 2305 last_entry.owner.inst = false; 2415 last_entry.owner.srcid = 0; 2416 #if L1_MULTI_CACHE 2417 last_entry.owner.cache_id = 0; 2418 #endif 2419 last_entry.owner.inst = false; 2306 2420 if(m_heap_directory.is_full()){ 2307 2421 last_entry.next = r_xram_rsp_next_ptr.read(); … … 2377 2491 { 2378 2492 if ( p_vci_tgt_cleanup.cmdval.read() ) { 2379 assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&2380 "VCI_MEM_CACHE error in a cleanup request : received SRCID is larger than the number of initiators");2493 ASSERT((p_vci_tgt_cleanup.srcid.read() < m_initiators) 2494 ,"VCI_MEM_CACHE error in a cleanup request : received SRCID is larger than the number of initiators"); 2381 2495 2382 2496 bool reached = false; … … 2391 2505 reached) 2392 2506 { 2507 PRINTF(" * <MEM_CACHE.CLEANUP> Request from %d.%d at address %llx\n",(uint32_t)p_vci_tgt_cleanup.srcid.read(),(uint32_t)p_vci_tgt_cleanup.pktid.read(),(uint64_t)p_vci_tgt_cleanup.address.read()); 2508 2393 2509 m_cpt_cleanup++; 2394 2510 … … 2425 2541 r_cleanup_way = way; 2426 2542 r_cleanup_copy = entry.owner.srcid; 2543 #if L1_MULTI_CACHE 2544 r_cleanup_copy_cache= entry.owner.cache_id; 2545 #endif 2427 2546 r_cleanup_copy_inst = entry.owner.inst; 2428 2547 r_cleanup_count = entry.count; 2429 2548 r_cleanup_ptr = entry.ptr; 2430 2431 2549 2432 2550 // In case of hit, the copy must be cleaned in the copies bit-vector … … 2446 2564 case CLEANUP_DIR_WRITE: 2447 2565 { 2448 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) &&2449 "MemCache ERROR : Bad DIR allocation");2566 ASSERT((r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) 2567 ,"MemCache ERROR : Bad DIR allocation"); 2450 2568 size_t way = r_cleanup_way.read(); 2451 2569 #define L2 soclib::common::uint32_log2 … … 2453 2571 #undef L2 2454 2572 bool cleanup_inst = r_cleanup_trdid.read() & 0x1; 2455 bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); 2573 bool match_srcid = ((r_cleanup_copy.read() == r_cleanup_srcid.read()) 2574 #if L1_MULTI_CACHE 2575 and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()) 2576 #endif 2577 ); 2456 2578 bool match_inst = (r_cleanup_copy_inst.read() == cleanup_inst); 2457 2579 bool match = match_srcid && match_inst; … … 2467 2589 if(r_cleanup_is_cnt.read()) { // Directory is a counter 2468 2590 entry.count = r_cleanup_count.read() -1; 2469 entry.owner.srcid = 0; 2470 entry.owner.inst = 0; 2591 entry.owner.srcid = 0; 2592 #if L1_MULTI_CACHE 2593 entry.owner.cache_id= 0; 2594 #endif 2595 entry.owner.inst = 0; 2471 2596 // response to the cache 2472 2597 r_cleanup_fsm = CLEANUP_RSP; … … 2474 2599 else{ // Directory is a list 2475 2600 if(match) { // hit 2476 entry.count = 0; // no more copy 2477 entry.owner.srcid = 0; 2478 entry.owner.inst = 0; 2479 r_cleanup_fsm = CLEANUP_RSP; 2601 entry.count = 0; // no more copy 2602 entry.owner.srcid = 0; 2603 #if L1_MULTI_CACHE 2604 entry.owner.cache_id=0; 2605 #endif 2606 entry.owner.inst = 0; 2607 r_cleanup_fsm = CLEANUP_RSP; 2480 2608 } else { // miss 2481 entry.count = r_cleanup_count.read(); 2482 entry.owner.srcid = r_cleanup_copy.read(); 2483 entry.owner.inst = r_cleanup_copy_inst.read(); 2484 r_cleanup_fsm = CLEANUP_UPT_LOCK; 2609 entry.count = r_cleanup_count.read(); 2610 entry.owner.srcid = r_cleanup_copy.read(); 2611 #if L1_MULTI_CACHE 2612 entry.owner.cache_id = r_cleanup_copy_cache.read(); 2613 #endif 2614 entry.owner.inst = r_cleanup_copy_inst.read(); 2615 r_cleanup_fsm = CLEANUP_UPT_LOCK; 2485 2616 } 2486 2617 } … … 2501 2632 bool cleanup_inst = r_cleanup_trdid.read() & 0x1; 2502 2633 bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); 2634 #if L1_MULTI_CACHE 2635 bool match_dir_cache_id = (r_cleanup_copy_cache.read() == r_cleanup_pktid.read()); 2636 #endif 2503 2637 bool match_dir_inst = (r_cleanup_copy_inst.read() == cleanup_inst); 2504 bool match_dir = match_dir_srcid &&match_dir_inst;2638 bool match_dir = match_dir_srcid and match_dir_cache_id and match_dir_inst; 2505 2639 bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); 2640 #if L1_MULTI_CACHE 2641 bool match_heap_cache_id= (heap_entry.owner.cache_id == r_cleanup_pktid.read()); 2642 #endif 2506 2643 bool match_heap_inst = (heap_entry.owner.inst == cleanup_inst); 2507 bool match_heap = match_heap_srcid && match_heap_inst; 2508 2509 r_cleanup_prev_ptr = r_cleanup_ptr.read(); 2510 r_cleanup_prev_srcid = heap_entry.owner.srcid; 2511 r_cleanup_prev_inst = heap_entry.owner.inst; 2644 bool match_heap = match_heap_srcid and match_heap_cache_id and match_heap_inst; 2645 2646 #if L1_MULTI_CACHE 2647 PRINTF(" * <MEM_CACHE.CLEANUP> match_dir %d (match_dir_srcid %d, match_dir_cache_id %d, match_dir_inst %d)\n", 2648 match_dir , match_dir_srcid , match_dir_cache_id , match_dir_inst); 2649 PRINTF(" * <MEM_CACHE.CLEANUP> match_heap %d (match_heap_srcid %d, match_heap_cache_id %d, match_heap_inst %d)\n", 2650 match_heap, match_heap_srcid, match_heap_cache_id, match_heap_inst); 2651 #else 2652 PRINTF(" * <MEM_CACHE.CLEANUP> match_dir %d (match_dir_srcid %d, match_dir_inst %d)\n", 2653 match_dir , match_dir_srcid , match_dir_inst); 2654 PRINTF(" * <MEM_CACHE.CLEANUP> match_heap %d (match_heap_srcid %d, match_heap_inst %d)\n", 2655 match_heap, match_heap_srcid, match_heap_inst); 2656 #endif 2657 PRINTF(" * <MEM_CACHE.CLEANUP> last %d\n",last); 2658 2659 r_cleanup_prev_ptr = r_cleanup_ptr.read(); 2660 r_cleanup_prev_srcid = heap_entry.owner.srcid; 2661 #if L1_MULTI_CACHE 2662 r_cleanup_prev_cache_id = heap_entry.owner.cache_id; 2663 #endif 2664 2665 r_cleanup_prev_inst = heap_entry.owner.inst; 2512 2666 2513 2667 if(match_dir){ 2514 2668 DirectoryEntry dir_entry; 2515 dir_entry.valid = true; 2516 dir_entry.is_cnt = r_cleanup_is_cnt.read(); 2517 dir_entry.dirty = r_cleanup_dirty.read(); 2518 dir_entry.tag = r_cleanup_tag.read(); 2519 dir_entry.lock = r_cleanup_lock.read(); 2520 dir_entry.ptr = heap_entry.next; 2521 dir_entry.count = r_cleanup_count.read()-1; 2522 dir_entry.owner.srcid = heap_entry.owner.srcid; 2523 dir_entry.owner.inst = heap_entry.owner.inst; 2669 dir_entry.valid = true; 2670 dir_entry.is_cnt = r_cleanup_is_cnt.read(); 2671 dir_entry.dirty = r_cleanup_dirty.read(); 2672 dir_entry.tag = r_cleanup_tag.read(); 2673 dir_entry.lock = r_cleanup_lock.read(); 2674 dir_entry.ptr = heap_entry.next; 2675 dir_entry.count = r_cleanup_count.read()-1; 2676 dir_entry.owner.srcid = heap_entry.owner.srcid; 2677 #if L1_MULTI_CACHE 2678 dir_entry.owner.cache_id = heap_entry.owner.cache_id; 2679 #endif 2680 dir_entry.owner.inst = heap_entry.owner.inst; 2524 2681 m_cache_directory.write(set,way,dir_entry); 2525 r_cleanup_next_ptr = r_cleanup_ptr.read();2526 r_cleanup_fsm = CLEANUP_HEAP_FREE;2682 r_cleanup_next_ptr = r_cleanup_ptr.read(); 2683 r_cleanup_fsm = CLEANUP_HEAP_FREE; 2527 2684 } 2528 2685 else if(match_heap){ 2529 2686 DirectoryEntry dir_entry; 2530 dir_entry.valid = true; 2531 dir_entry.is_cnt = r_cleanup_is_cnt.read(); 2532 dir_entry.dirty = r_cleanup_dirty.read(); 2533 dir_entry.tag = r_cleanup_tag.read(); 2534 dir_entry.lock = r_cleanup_lock.read(); 2535 dir_entry.ptr = heap_entry.next; 2536 dir_entry.count = r_cleanup_count.read()-1; 2537 dir_entry.owner.srcid = r_cleanup_copy.read(); 2538 dir_entry.owner.inst = r_cleanup_copy_inst.read(); 2687 dir_entry.valid = true; 2688 dir_entry.is_cnt = r_cleanup_is_cnt.read(); 2689 dir_entry.dirty = r_cleanup_dirty.read(); 2690 dir_entry.tag = r_cleanup_tag.read(); 2691 dir_entry.lock = r_cleanup_lock.read(); 2692 dir_entry.ptr = heap_entry.next; 2693 dir_entry.count = r_cleanup_count.read()-1; 2694 dir_entry.owner.srcid = r_cleanup_copy.read(); 2695 #if L1_MULTI_CACHE 2696 dir_entry.owner.cache_id = r_cleanup_copy_cache.read(); 2697 #endif 2698 dir_entry.owner.inst = r_cleanup_copy_inst.read(); 2539 2699 m_cache_directory.write(set,way,dir_entry); 2540 r_cleanup_next_ptr = r_cleanup_ptr.read();2541 r_cleanup_fsm = CLEANUP_HEAP_FREE;2700 r_cleanup_next_ptr = r_cleanup_ptr.read(); 2701 r_cleanup_fsm = CLEANUP_HEAP_FREE; 2542 2702 } 2543 2703 else{ … … 2552 2712 dir_entry.count = r_cleanup_count.read()-1; 2553 2713 dir_entry.owner.srcid = r_cleanup_copy.read(); 2714 #if L1_MULTI_CACHE 2715 dir_entry.owner.cache_id= r_cleanup_copy_cache.read(); 2716 #endif 2554 2717 dir_entry.owner.inst = r_cleanup_copy_inst.read(); 2555 2718 m_cache_directory.write(set,way,dir_entry); … … 2559 2722 2560 2723 } else{ 2561 assert(false &&"MemCache ERROR : CLEANUP hit but line not shared");2724 ASSERT(false,"MemCache ERROR : CLEANUP hit but line not shared"); 2562 2725 } 2563 2726 } … … 2568 2731 case CLEANUP_HEAP_SEARCH: 2569 2732 { 2570 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&2571 2733 ASSERT((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) 2734 ,"MemCache ERROR : bad HEAP allocation"); 2572 2735 HeapEntry heap_entry = m_heap_directory.read(r_cleanup_next_ptr.read()); 2573 2736 bool last = (heap_entry.next == r_cleanup_next_ptr.read()); 2574 2737 bool cleanup_inst = r_cleanup_trdid.read() & 0x1; 2575 bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); 2738 bool match_heap_srcid = ((heap_entry.owner.srcid == r_cleanup_srcid.read()) 2739 #if L1_MULTI_CACHE 2740 and (heap_entry.owner.cache_id == r_cleanup_pktid.read()) 2741 #endif 2742 ); 2576 2743 bool match_heap_inst = (heap_entry.owner.inst == cleanup_inst); 2577 2744 bool match_heap = match_heap_srcid && match_heap_inst; … … 2583 2750 else{ 2584 2751 if(last) { 2585 assert(false &&"MemCache ERROR : CLEANUP hit but line not shared");2752 ASSERT(false,"MemCache ERROR : CLEANUP hit but line not shared"); 2586 2753 } else { 2587 r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); 2588 r_cleanup_prev_srcid = heap_entry.owner.srcid; 2589 r_cleanup_prev_inst = heap_entry.owner.inst; 2754 r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); 2755 r_cleanup_prev_srcid = heap_entry.owner.srcid; 2756 #if L1_MULTI_CACHE 2757 r_cleanup_prev_cache_id = heap_entry.owner.cache_id; 2758 #endif 2759 r_cleanup_prev_inst = heap_entry.owner.inst; 2590 2760 r_cleanup_next_ptr = heap_entry.next; 2591 2761 r_cleanup_fsm = CLEANUP_HEAP_SEARCH; … … 2598 2768 case CLEANUP_HEAP_CLEAN: 2599 2769 { 2600 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&2601 2770 ASSERT((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) 2771 ,"MemCache ERROR : bad HEAP allocation"); 2602 2772 bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); 2603 2773 HeapEntry heap_entry; 2604 heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); 2605 heap_entry.owner.inst = r_cleanup_prev_inst.read(); 2774 heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); 2775 #if L1_MULTI_CACHE 2776 heap_entry.owner.cache_id = r_cleanup_prev_cache_id.read(); 2777 #endif 2778 heap_entry.owner.inst = r_cleanup_prev_inst.read(); 2606 2779 if(last){ // this is the last entry of the list of copies 2607 2780 heap_entry.next = r_cleanup_prev_ptr.read(); … … 2616 2789 case CLEANUP_HEAP_FREE: 2617 2790 { 2618 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&2619 2791 ASSERT((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) 2792 ,"MemCache ERROR : bad HEAP allocation"); 2620 2793 HeapEntry heap_entry; 2621 heap_entry.owner.srcid = 0; 2622 heap_entry.owner.inst = false; 2794 heap_entry.owner.srcid = 0; 2795 #if L1_MULTI_CACHE 2796 heap_entry.owner.cache_id = 0; 2797 #endif 2798 heap_entry.owner.inst = false; 2623 2799 if(m_heap_directory.is_full()){ 2624 2800 heap_entry.next = r_cleanup_next_ptr.read(); … … 2760 2936 r_llsc_wdata = m_cmd_llsc_wdata_fifo.read(); 2761 2937 if(r_llsc_cpt.read()>3) 2762 assert(false &&"MEMCACHE error : SC too long");2938 ASSERT(false,"MEMCACHE error : SC too long"); 2763 2939 if(r_llsc_cpt.read()==2){ 2764 2940 r_llsc_wdata = m_cmd_llsc_wdata_fifo.read(); … … 2774 2950 size_t way = 0; 2775 2951 DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way)); 2776 r_llsc_is_cnt = entry.is_cnt; 2777 r_llsc_dirty = entry.dirty; 2778 r_llsc_tag = entry.tag; 2779 r_llsc_way = way; 2780 r_llsc_copy = entry.owner.srcid; 2781 r_llsc_copy_inst= entry.owner.inst; 2782 r_llsc_ptr = entry.ptr; 2783 r_llsc_count = entry.count; 2952 r_llsc_is_cnt = entry.is_cnt; 2953 r_llsc_dirty = entry.dirty; 2954 r_llsc_tag = entry.tag; 2955 r_llsc_way = way; 2956 r_llsc_copy = entry.owner.srcid; 2957 #if L1_MULTI_CACHE 2958 r_llsc_copy_cache = entry.owner.cache_id; 2959 #endif 2960 2961 r_llsc_copy_inst = entry.owner.inst; 2962 r_llsc_ptr = entry.ptr; 2963 r_llsc_count = entry.count; 2784 2964 if ( entry.valid ){ 2785 2965 r_llsc_fsm = SC_DIR_HIT_READ; … … 2798 2978 // update directory (lock & dirty bits 2799 2979 DirectoryEntry entry; 2800 entry.valid = true; 2801 entry.is_cnt = r_llsc_is_cnt.read(); 2802 entry.dirty = true; 2803 entry.lock = true; 2804 entry.tag = r_llsc_tag.read(); 2805 entry.owner.srcid = r_llsc_copy.read(); 2806 entry.owner.inst = r_llsc_copy_inst.read(); 2807 entry.count = r_llsc_count.read(); 2808 entry.ptr = r_llsc_ptr.read(); 2980 entry.valid = true; 2981 entry.is_cnt = r_llsc_is_cnt.read(); 2982 entry.dirty = true; 2983 entry.lock = true; 2984 entry.tag = r_llsc_tag.read(); 2985 entry.owner.srcid = r_llsc_copy.read(); 2986 #if L1_MULTI_CACHE 2987 entry.owner.cache_id = r_llsc_copy_cache.read(); 2988 #endif 2989 entry.owner.inst = r_llsc_copy_inst.read(); 2990 entry.count = r_llsc_count.read(); 2991 entry.ptr = r_llsc_ptr.read(); 2809 2992 m_cache_directory.write(set, way, entry); 2810 2993 … … 2938 3121 case SC_UPT_REQ: // Request the update 2939 3122 { 2940 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&2941 3123 ASSERT((r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) 3124 ,"MemCache ERROR : bad HEAP allocation"); 2942 3125 if( !r_llsc_to_init_cmd_multi_req.read() && 2943 3126 !r_llsc_to_init_cmd_brdcast_req.read() ){ … … 2959 3142 llsc_to_init_cmd_fifo_inst = r_llsc_copy_inst.read(); 2960 3143 llsc_to_init_cmd_fifo_srcid = r_llsc_copy.read(); 3144 #if L1_MULTI_CACHE 3145 llsc_to_init_cmd_fifo_cache_id= r_llsc_copy_cache.read(); 3146 #endif 2961 3147 if(r_llsc_count.read() == 1){ 2962 3148 #ifdef LOCK_DEBUG … … 2978 3164 case SC_UPDATE: // send a multi-update request to INIT_CMD fsm 2979 3165 { 2980 assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&2981 3166 ASSERT((r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) 3167 ,"MemCache ERROR : bad HEAP allocation"); 2982 3168 HeapEntry entry = m_heap_directory.read(r_llsc_ptr.read()); 2983 llsc_to_init_cmd_fifo_inst = entry.owner.inst; 2984 llsc_to_init_cmd_fifo_srcid = entry.owner.srcid; 3169 llsc_to_init_cmd_fifo_srcid = entry.owner.srcid; 3170 #if L1_MULTI_CACHE 3171 llsc_to_init_cmd_fifo_cache_id = entry.owner.cache_id; 3172 #endif 3173 llsc_to_init_cmd_fifo_inst = entry.owner.inst; 2985 3174 llsc_to_init_cmd_fifo_put = true; 2986 3175 … … 3106 3295 entry.count = 0; 3107 3296 entry.owner.srcid = 0; 3297 #if L1_MULTI_CACHE 3298 entry.owner.cache_id= 0; 3299 #endif 3108 3300 entry.owner.inst = false; 3109 3301 entry.ptr = 0; … … 3114 3306 r_llsc_fsm = SC_INVAL; 3115 3307 } else { 3116 assert(false &&"LOCK ERROR in LLSC_FSM, STATE = LLSC_DIR_INVAL");3308 ASSERT(false,"LOCK ERROR in LLSC_FSM, STATE = LLSC_DIR_INVAL"); 3117 3309 } 3118 3310 … … 3150 3342 r_llsc_cpt = 0; 3151 3343 } else { 3152 assert( false &&"MEM_CACHE, LLSC FSM : SC_XRAM_SEND state : the request should not have been previously set");3344 ASSERT(false,"MEM_CACHE, LLSC FSM : SC_XRAM_SEND state : the request should not have been previously set"); 3153 3345 } 3154 3346 break; … … 4109 4301 m_write_to_init_cmd_inst_fifo.put_and_get(write_to_init_cmd_fifo_inst); 4110 4302 m_write_to_init_cmd_srcid_fifo.put_and_get(write_to_init_cmd_fifo_srcid); 4303 #if L1_MULTI_CACHE 4304 m_write_to_init_cmd_cache_id_fifo.put_and_get(write_to_init_cmd_fifo_cache_id); 4305 #endif 4111 4306 } else { 4112 4307 m_write_to_init_cmd_inst_fifo.simple_put(write_to_init_cmd_fifo_inst); 4113 4308 m_write_to_init_cmd_srcid_fifo.simple_put(write_to_init_cmd_fifo_srcid); 4309 #if L1_MULTI_CACHE 4310 m_write_to_init_cmd_cache_id_fifo.simple_put(write_to_init_cmd_fifo_cache_id); 4311 #endif 4114 4312 } 4115 4313 } else { … … 4117 4315 m_write_to_init_cmd_inst_fifo.simple_get(); 4118 4316 m_write_to_init_cmd_srcid_fifo.simple_get(); 4317 #if L1_MULTI_CACHE 4318 m_write_to_init_cmd_cache_id_fifo.simple_get(); 4319 #endif 4119 4320 } 4120 4321 } … … 4127 4328 m_xram_rsp_to_init_cmd_inst_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_inst); 4128 4329 m_xram_rsp_to_init_cmd_srcid_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_srcid); 4330 #if L1_MULTI_CACHE 4331 m_xram_rsp_to_init_cmd_cache_id_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_cache_id); 4332 #endif 4129 4333 } else { 4130 4334 m_xram_rsp_to_init_cmd_inst_fifo.simple_put(xram_rsp_to_init_cmd_fifo_inst); 4131 4335 m_xram_rsp_to_init_cmd_srcid_fifo.simple_put(xram_rsp_to_init_cmd_fifo_srcid); 4336 #if L1_MULTI_CACHE 4337 m_xram_rsp_to_init_cmd_cache_id_fifo.simple_put(xram_rsp_to_init_cmd_fifo_cache_id); 4338 #endif 4132 4339 } 4133 4340 } else { … … 4135 4342 m_xram_rsp_to_init_cmd_inst_fifo.simple_get(); 4136 4343 m_xram_rsp_to_init_cmd_srcid_fifo.simple_get(); 4344 #if L1_MULTI_CACHE 4345 m_xram_rsp_to_init_cmd_cache_id_fifo.simple_get(); 4346 #endif 4137 4347 } 4138 4348 } … … 4145 4355 m_llsc_to_init_cmd_inst_fifo.put_and_get(llsc_to_init_cmd_fifo_inst); 4146 4356 m_llsc_to_init_cmd_srcid_fifo.put_and_get(llsc_to_init_cmd_fifo_srcid); 4357 #if L1_MULTI_CACHE 4358 m_llsc_to_init_cmd_cache_id_fifo.put_and_get(llsc_to_init_cmd_fifo_cache_id); 4359 #endif 4147 4360 } else { 4148 m_llsc_to_init_cmd_inst_fifo.simple_put(llsc_to_init_cmd_fifo_inst); 4149 m_llsc_to_init_cmd_srcid_fifo.simple_put(llsc_to_init_cmd_fifo_srcid); 4361 m_llsc_to_init_cmd_inst_fifo.simple_put(llsc_to_init_cmd_fifo_inst); 4362 m_llsc_to_init_cmd_srcid_fifo.simple_put(llsc_to_init_cmd_fifo_srcid); 4363 #if L1_MULTI_CACHE 4364 m_llsc_to_init_cmd_cache_id_fifo.simple_put(llsc_to_init_cmd_fifo_cache_id); 4365 #endif 4150 4366 } 4151 4367 } else { 4152 if ( llsc_to_init_cmd_fifo_get ) { 4153 m_llsc_to_init_cmd_inst_fifo.simple_get(); 4154 m_llsc_to_init_cmd_srcid_fifo.simple_get(); 4368 if ( llsc_to_init_cmd_fifo_get ) { 4369 m_llsc_to_init_cmd_inst_fifo.simple_get(); 4370 m_llsc_to_init_cmd_srcid_fifo.simple_get(); 4371 #if L1_MULTI_CACHE 4372 m_llsc_to_init_cmd_cache_id_fifo.simple_get(); 4373 #endif 4155 4374 } 4156 4375 } … … 4160 4379 m_cpt_cycles++; 4161 4380 4162 } // end transition()4381 } // end transition() 4163 4382 4164 4383 ///////////////////////////// … … 4297 4516 break; 4298 4517 case TGT_RSP_READ: 4518 PRINTF(" * <MEM_CACHE.TGT> RSP_READ : srcid %d, trdid %d, pktid %d\n" 4519 ,(uint32_t)r_read_to_tgt_rsp_srcid.read() 4520 ,(uint32_t)r_read_to_tgt_rsp_trdid.read() 4521 ,(uint32_t)r_read_to_tgt_rsp_pktid.read() 4522 ); 4523 4299 4524 p_vci_tgt.rspval = true; 4300 4525 p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); … … 4306 4531 break; 4307 4532 case TGT_RSP_WRITE: 4533 PRINTF(" * <MEM_CACHE.TGT> RSP_WRITE : BURP srcid %d, trdid %d, pktid %d\n" 4534 ,(uint32_t)r_write_to_tgt_rsp_srcid.read() 4535 ,(uint32_t)r_write_to_tgt_rsp_trdid.read() 4536 ,(uint32_t)r_write_to_tgt_rsp_pktid.read() 4537 ); 4538 4308 4539 p_vci_tgt.rspval = true; 4309 4540 p_vci_tgt.rdata = 0; … … 4315 4546 break; 4316 4547 case TGT_RSP_CLEANUP: 4548 PRINTF(" * <MEM_CACHE.TGT> RSP_CLEANUP : srcid %d, trdid %d, pktid %d\n" 4549 ,(uint32_t)r_cleanup_to_tgt_rsp_srcid.read() 4550 ,(uint32_t)r_cleanup_to_tgt_rsp_trdid.read() 4551 ,(uint32_t)r_cleanup_to_tgt_rsp_pktid.read() 4552 ); 4553 4317 4554 p_vci_tgt.rspval = true; 4318 4555 p_vci_tgt.rdata = 0; … … 4324 4561 break; 4325 4562 case TGT_RSP_LLSC: 4563 PRINTF(" * <MEM_CACHE.TGT> RSP_LLSC : srcid %d, trdid %d, pktid %d\n" 4564 ,(uint32_t)r_llsc_to_tgt_rsp_srcid.read() 4565 ,(uint32_t)r_llsc_to_tgt_rsp_trdid.read() 4566 ,(uint32_t)r_llsc_to_tgt_rsp_pktid.read() 4567 ); 4568 4326 4569 p_vci_tgt.rspval = true; 4327 4570 p_vci_tgt.rdata = r_llsc_to_tgt_rsp_data.read(); … … 4333 4576 break; 4334 4577 case TGT_RSP_XRAM: 4578 PRINTF(" * <MEM_CACHE.TGT> RSP_XRAM : srcid %d, trdid %d, pktid %d\n" 4579 ,(uint32_t)r_xram_rsp_to_tgt_rsp_srcid.read() 4580 ,(uint32_t)r_xram_rsp_to_tgt_rsp_trdid.read() 4581 ,(uint32_t)r_xram_rsp_to_tgt_rsp_pktid.read() 4582 ); 4583 4335 4584 p_vci_tgt.rspval = true; 4336 4585 p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); … … 4343 4592 break; 4344 4593 case TGT_RSP_INIT: 4594 PRINTF(" * <MEM_CACHE.TGT> RSP_INIT : srcid %d, trdid %d, pktid %d\n" 4595 ,(uint32_t)r_init_rsp_to_tgt_rsp_srcid.read() 4596 ,(uint32_t)r_init_rsp_to_tgt_rsp_trdid.read() 4597 ,(uint32_t)r_init_rsp_to_tgt_rsp_pktid.read() 4598 ); 4599 4345 4600 p_vci_tgt.rspval = true; 4346 4601 p_vci_tgt.rdata = 0; … … 4359 4614 p_vci_ini.cmd = vci_param::CMD_WRITE; 4360 4615 p_vci_ini.srcid = m_srcid_ini; 4361 p_vci_ini.pktid = 0;4362 4616 p_vci_ini.cons = true; 4363 4617 p_vci_ini.wrap = false; … … 4377 4631 p_vci_ini.plen = 0; 4378 4632 p_vci_ini.trdid = 0; 4633 p_vci_ini.pktid = 0; 4379 4634 p_vci_ini.eop = false; 4380 4635 break; 4381 4636 case INIT_CMD_INVAL_NLINE: 4637 { 4638 PRINTF(" * <MEM_CACHE.INIT_CMD> INVAL_NLINE : trdid %d, pktid %d\n" 4639 ,(uint32_t)r_xram_rsp_to_init_cmd_trdid.read() 4640 ,(uint32_t)m_xram_rsp_to_init_cmd_cache_id_fifo.read() 4641 ); 4642 4382 4643 p_vci_ini.cmdval = m_xram_rsp_to_init_cmd_inst_fifo.rok(); 4383 4644 if(m_xram_rsp_to_init_cmd_inst_fifo.rok()){ … … 4392 4653 p_vci_ini.plen = 4; 4393 4654 p_vci_ini.trdid = r_xram_rsp_to_init_cmd_trdid.read(); 4655 p_vci_ini.pktid = m_xram_rsp_to_init_cmd_cache_id_fifo.read(); 4394 4656 p_vci_ini.eop = true; 4395 4657 break; 4658 } 4396 4659 case INIT_CMD_XRAM_BRDCAST: 4397 4660 p_vci_ini.cmdval = true; … … 4401 4664 p_vci_ini.plen = 4; 4402 4665 p_vci_ini.trdid = r_xram_rsp_to_init_cmd_trdid.read(); 4666 p_vci_ini.pktid = 0; 4403 4667 p_vci_ini.eop = true; 4404 4668 break; … … 4412 4676 p_vci_ini.eop = true; 4413 4677 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 4678 p_vci_ini.pktid = 0; 4414 4679 break; 4415 4680 case INIT_CMD_UPDT_NLINE: … … 4429 4694 p_vci_ini.eop = false; 4430 4695 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 4696 p_vci_ini.pktid = m_write_to_init_cmd_cache_id_fifo.read(); 4431 4697 break; 4432 4698 case INIT_CMD_UPDT_INDEX: … … 4441 4707 p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); 4442 4708 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 4709 p_vci_ini.pktid = m_write_to_init_cmd_cache_id_fifo.read(); 4443 4710 p_vci_ini.eop = false; 4444 4711 break; … … 4456 4723 p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); 4457 4724 p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); 4725 p_vci_ini.pktid = m_write_to_init_cmd_cache_id_fifo.read(); 4458 4726 p_vci_ini.eop = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ); 4459 4727 break; … … 4467 4735 p_vci_ini.eop = true; 4468 4736 p_vci_ini.trdid = r_llsc_to_init_cmd_trdid.read(); 4737 p_vci_ini.pktid = 0; 4469 4738 break; 4470 4739 case INIT_CMD_SC_UPDT_NLINE: … … 4488 4757 p_vci_ini.eop = false; 4489 4758 p_vci_ini.trdid = r_llsc_to_init_cmd_trdid.read(); 4759 p_vci_ini.pktid = m_llsc_to_init_cmd_cache_id_fifo.read(); 4490 4760 break; 4491 4761 case INIT_CMD_SC_UPDT_INDEX: … … 4504 4774 } 4505 4775 p_vci_ini.trdid = r_llsc_to_init_cmd_trdid.read(); 4776 p_vci_ini.pktid = m_llsc_to_init_cmd_cache_id_fifo.read(); 4506 4777 p_vci_ini.eop = false; 4507 4778 break; … … 4516 4787 p_vci_ini.be = 0xF; 4517 4788 p_vci_ini.trdid = r_llsc_to_init_cmd_trdid.read(); 4789 p_vci_ini.pktid = m_llsc_to_init_cmd_cache_id_fifo.read(); 4518 4790 if(r_llsc_to_init_cmd_is_long.read()){ 4519 4791 p_vci_ini.plen = 4 * 4; … … 4535 4807 p_vci_ini.plen = 4 * 4; 4536 4808 p_vci_ini.trdid = r_llsc_to_init_cmd_trdid.read(); 4809 p_vci_ini.pktid = m_llsc_to_init_cmd_cache_id_fifo.read(); 4537 4810 p_vci_ini.eop = true; 4538 4811 break; … … 4567 4840 case CLEANUP_RSP: 4568 4841 { 4842 PRINTF(" * <MEM_CACHE.CLEANUP_RSP> Respons to %d.%d\n",(uint32_t)r_cleanup_srcid.read(),(uint32_t)r_cleanup_pktid.read()); 4843 4569 4844 p_vci_tgt_cleanup.rspval = true; 4570 4845 p_vci_tgt_cleanup.rdata = 0;
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