Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 140) +++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (revision 141) @@ -287,4 +287,6 @@ uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions uint32_t m_cpt_update; // Number of UPDATE transactions + uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt + uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt uint32_t m_cpt_update_mult; // Number of targets for UPDATE uint32_t m_cpt_inval; // Number of INVAL transactions @@ -319,5 +321,8 @@ size_t nsets, // Number of sets size_t nwords, // Number of words per line - size_t heap_size=1024); // Size of the heap + size_t heap_size=1024, // Size of the heap + size_t transaction_tab_lines=TRANSACTION_TAB_LINES,// Size of the TRT + size_t update_tab_lines=UPDATE_TAB_LINES // Size of the UPT + ); ~VciMemCacheV4(); @@ -343,8 +348,10 @@ std::list m_seglist; // memory cached into the cache std::list m_cseglist; // coherence segment for the cache - vci_addr_t *m_coherence_table; // address(srcid) - TransactionTab m_transaction_tab; // xram transaction table + vci_addr_t *m_coherence_table; // address(srcid) + TransactionTab m_transaction_tab; // xram transaction table + uint32_t m_transaction_tab_lines; UpdateTab m_update_tab; // pending update & invalidate - CacheDirectory m_cache_directory; // data cache directory + uint32_t m_update_tab_lines; + CacheDirectory m_cache_directory; // data cache directory HeapDirectory m_heap_directory; // heap directory @@ -713,6 +720,6 @@ // Local Variables: -// tab-width: 4 -// c-basic-offset: 4 +// tab-width: 2 +// c-basic-offset: 2 // c-file-offsets:((innamespace . 0)(inline-open . 0)) // indent-tabs-mode: nil Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 140) +++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 141) @@ -244,5 +244,7 @@ size_t nsets, size_t nwords, - size_t heap_size) + size_t heap_size, + size_t transaction_tab_lines, + size_t update_tab_lines) : soclib::caba::BaseModule(name), @@ -265,6 +267,8 @@ m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)), m_coherence_table( mtc.getCoherenceTable() ), - m_transaction_tab( TRANSACTION_TAB_LINES, nwords ), - m_update_tab( UPDATE_TAB_LINES ), + m_transaction_tab_lines(transaction_tab_lines), + m_transaction_tab( transaction_tab_lines, nwords ), + m_update_tab_lines( update_tab_lines), + m_update_tab( update_tab_lines ), m_cache_directory( nways, nsets, nwords, vci_param::N ), m_heap_directory( m_heap_size ), @@ -338,7 +342,4 @@ assert(nwords); assert(nways); - assert(nsets <= 1024); - assert(nwords <= 32); - assert(nways <= 32); // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum @@ -383,5 +384,5 @@ // Allocation for IXR_RSP FSM - r_ixr_rsp_to_xram_rsp_rok = new sc_signal[TRANSACTION_TAB_LINES]; + r_ixr_rsp_to_xram_rsp_rok = new sc_signal[m_transaction_tab_lines]; // Allocation for XRAM_RSP FSM @@ -441,18 +442,23 @@ std::cout << "----------------------------------" << std::dec << std::endl; std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl - << "- READ RATE = " << (double)m_cpt_read/m_cpt_cycles << std::endl - << "- READ MISS RATE = " << (double)m_cpt_read_miss/m_cpt_read << std::endl - << "- WRITE RATE = " << (double)m_cpt_write/m_cpt_cycles << std::endl - << "- WRITE MISS RATE = " << (double)m_cpt_write_miss/m_cpt_write << std::endl - << "- WRITE BURST LENGTH = " << (double)m_cpt_write_cells/m_cpt_write << std::endl - << "- UPDATE RATE = " << (double)m_cpt_update/m_cpt_cycles << std::endl - << "- UPDATE ARITY = " << (double)m_cpt_update_mult/m_cpt_update << std::endl - << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl - << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl - << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl - << "- SAVE DIRTY RATE = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl - << "- CLEANUP RATE = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl - << "- LL RATE = " << (double)m_cpt_ll/m_cpt_cycles << std::endl - << "- SC RATE = " << (double)m_cpt_sc/m_cpt_cycles << std::endl; + << "- READ RATE = " << (double)m_cpt_read/m_cpt_cycles << std::endl + << "- READ TOTAL = " << m_cpt_read << std::endl + << "- READ MISS RATE = " << (double)m_cpt_read_miss/m_cpt_read << std::endl + << "- WRITE RATE = " << (double)m_cpt_write/m_cpt_cycles << std::endl + << "- WRITE TOTAL = " << m_cpt_write << std::endl + << "- WRITE MISS RATE = " << (double)m_cpt_write_miss/m_cpt_write << std::endl + << "- WRITE BURST LENGTH = " << (double)m_cpt_write_cells/m_cpt_write << std::endl + << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl + << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl + << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl + << "- UPDATE RATE = " << (double)m_cpt_update/m_cpt_cycles << std::endl + << "- UPDATE ARITY = " << (double)m_cpt_update_mult/m_cpt_update << std::endl + << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl + << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl + << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl + << "- SAVE DIRTY RATE = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl + << "- CLEANUP RATE = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl + << "- LL RATE = " << (double)m_cpt_ll/m_cpt_cycles << std::endl + << "- SC RATE = " << (double)m_cpt_sc/m_cpt_cycles << std::endl; } @@ -567,5 +573,5 @@ #endif - for(size_t i=0; i Request from %d.%d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint32_t)m_cmd_read_pktid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read()); - m_cpt_read++; r_read_fsm = READ_DIR_LOCK; } @@ -922,5 +932,4 @@ } else { r_read_fsm = READ_TRT_LOCK; - m_cpt_read_miss++; } } @@ -1162,6 +1171,11 @@ bool wok = !m_transaction_tab.full(index); if( hit_read || !wok || hit_write ) { // missing line already requested or no space + if(!wok) + m_cpt_trt_full++; + if(hit_read || hit_write) + m_cpt_trt_rb++; r_read_fsm = READ_IDLE; } else { // missing line is requested to the XRAM + m_cpt_read_miss++; r_read_trt_index = index; r_read_fsm = READ_TRT_SET; @@ -1324,5 +1338,4 @@ } else { r_write_fsm = WRITE_TRT_LOCK; - m_cpt_write_miss++; } } @@ -1594,9 +1607,12 @@ r_write_trt_index = hit_index; r_write_fsm = WRITE_TRT_DATA; + m_cpt_write_miss++; } else if ( wok && !hit_write ) { // set a new entry in TRT r_write_trt_index = wok_index; r_write_fsm = WRITE_TRT_SET; + m_cpt_write_miss++; } else { // wait an empty entry in TRT r_write_fsm = WRITE_WAIT; + m_cpt_trt_full++; } } @@ -2040,5 +2056,5 @@ { size_t ptr = r_xram_rsp_trt_index.read(); - size_t lines = TRANSACTION_TAB_LINES; + size_t lines = m_transaction_tab_lines; for(size_t i=0; i