Index: /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h =================================================================== --- /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (revision 142) +++ /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (revision 143) @@ -43,12 +43,10 @@ /* - * CC_XCACHE_WRAPPER_SELECT_VICTIM : - * The selection and the update of cache (after a read miss) - * are separated in two step - * Also, the cleanup can be send in parallel at the read miss. - * * CC_XCACHE_WRAPPER_FIFO_RSP * Two simple fifo (each 2x32 depth) receive the cache line from * RAM. Instead of two buffers (m_icache_words and m_dcache_words) + * 1 - nb_icache+nb_dcache simple fifo + * 2 - 2 simple fifo + * else - two buffers (m_icache_words and m_dcache_words) * * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE @@ -67,8 +65,8 @@ * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req - * 1 - two access authorized - * 2 - one access with static priority (dcache prior) - * 3 - one access with static priority (icache prior) - * 4 - one access with round robin priority + * 1 - one access with static priority (dcache prior) + * 2 - one access with static priority (icache prior) + * 3 - one access with round robin priority + * 4 - two access authorized * * CC_XCACHE_WRAPPER_MULTI_CACHE : @@ -95,7 +93,4 @@ // implementation -#ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM -#define CC_XCACHE_WRAPPER_SELECT_VICTIM 1 -#endif #ifndef CC_XCACHE_WRAPPER_FIFO_RSP #define CC_XCACHE_WRAPPER_FIFO_RSP 1 @@ -111,10 +106,17 @@ #endif #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY -#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 4 +#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 #endif #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 -#endif +// if multi_cache : +// /modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 +// /soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 +#endif + // debugging +#ifndef CC_XCACHE_WRAPPER_VERBOSE +#define CC_XCACHE_WRAPPER_VERBOSE 1 +#endif #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 @@ -124,5 +126,5 @@ #endif #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN -#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 949900 +#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500 #endif #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION @@ -158,7 +160,5 @@ DCACHE_IDLE, DCACHE_WRITE_UPDT, -#if CC_XCACHE_WRAPPER_SELECT_VICTIM DCACHE_MISS_VICTIM, -#endif DCACHE_MISS_WAIT, DCACHE_MISS_UPDT, @@ -176,7 +176,5 @@ enum icache_fsm_state_e { ICACHE_IDLE, -#if CC_XCACHE_WRAPPER_SELECT_VICTIM ICACHE_MISS_VICTIM, -#endif ICACHE_MISS_WAIT, ICACHE_MISS_UPDT, @@ -341,7 +339,16 @@ sc_signal * r_vci_rsp_data_error; //[m_nb_dcache] -#if CC_XCACHE_WRAPPER_FIFO_RSP +#if (CC_XCACHE_WRAPPER_FIFO_RSP==1) std::queue * r_icache_miss_buf; //[m_nb_icache] std::queue * r_dcache_miss_buf; //[m_nb_dcache] +#elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) + typedef struct + { + data_t data; + uint32_t num_cache; + } miss_buf_t; + + std::queue r_icache_miss_buf; + std::queue r_dcache_miss_buf; #else bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] Index: /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp =================================================================== --- /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (revision 142) +++ /trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (revision 143) @@ -75,6 +75,5 @@ // =====[ FIFO_RSP ]================================= -// FIXME : une FIFO avec le numéro du cache ! -#if CC_XCACHE_WRAPPER_FIFO_RSP +#if (CC_XCACHE_WRAPPER_FIFO_RSP==1) # define CACHE_MISS_BUF_ALLOC do { \ r_icache_miss_buf = new std::queue [m_nb_icache]; \ @@ -106,4 +105,28 @@ PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf[x].size()); \ } \ + } while (0) +#elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) +# define CACHE_MISS_BUF_ALLOC +# define CACHE_MISS_BUF_DEALLOC +# define CACHE_MISS_BUF_RESET(c) do { \ + while (r_##c##cache_miss_buf.size()>0) { \ + r_##c##cache_miss_buf.pop(); \ + } \ + } while (0) +# define CACHE_MISS_BUF_REQ_INIT(c,x) +# define CACHE_MISS_BUF_RSP_VAL(c,x,n) ((r_##c##cache_miss_buf.size()>0) and (r_##c##cache_miss_buf.front().num_cache==x)) +# define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf.size()<2) +# define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf.front().data +# define CACHE_MISS_BUF_RSP_POP(c,x) do { \ + r_##c##cache_miss_buf.pop(); \ + } while (0) +# define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ + miss_buf_t miss_buf; \ + miss_buf.data = d; \ + miss_buf.num_cache = x; \ + r_##c##cache_miss_buf.push(miss_buf); \ + } while (0) +# define CACHE_MISS_BUF_RSP_PRINT(c) do { \ + PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size()); \ } while (0) #else @@ -187,7 +210,5 @@ "DCACHE_IDLE", "DCACHE_WRITE_UPDT", -#if CC_XCACHE_WRAPPER_SELECT_VICTIM "DCACHE_MISS_VICTIM", -#endif "DCACHE_MISS_WAIT", "DCACHE_MISS_UPDT", @@ -204,7 +225,5 @@ const char *icache_fsm_state_str[] = { "ICACHE_IDLE", -#if CC_XCACHE_WRAPPER_SELECT_VICTIM "ICACHE_MISS_VICTIM", -#endif "ICACHE_MISS_WAIT", "ICACHE_MISS_UPDT", @@ -254,4 +273,6 @@ } +typedef long long unsigned int blob_t; + #define tmpl(...) template __VA_ARGS__ VciCcXCacheWrapperV4 @@ -382,4 +403,8 @@ "When multi cache is activated, need 4 bits (16 word) to the cache set ."); + if (m_nb_cpu > 1) + ASSERT(CC_XCACHE_MULTI_CPU!=0, + "Macro CC_XCACHE_MULTI_CPU in wbuf must be set at 1."); + p_irq = new sc_in * [m_nb_cpu]; for (uint32_t num_cpu=0; num_cpu Parameters :" << std::endl; std::cout << " * nb_cpu : " << nb_cpu << std::endl; @@ -546,4 +572,5 @@ std::cout << " * wbuf (total) : " << wbuf_nlines << " line(s), " << wbuf_nwords << " word(s), timeout : " << wbuf_timeout << std::endl; std::cout << " * wbuf (per cache) : " << _wbuf_nlines << " line(s), " << _wbuf_nwords << " word(s), timeout : " << _wbuf_timeout << std::endl; +#endif r_icache = new GenericCache * [m_nb_icache]; @@ -1088,11 +1115,11 @@ PRINTF(" * CC_XCACHE_WRAPPER \"%s\" Transition - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); for (uint32_t num_cache=0; num_cache trdid : %d\n",(uint32_t)p_vci_tgt.trdid.read()); PRINTF(" * pktid : %d\n",(uint32_t)p_vci_tgt.pktid.read()); - PRINTF(" * address (before) : %llx\n",(uint64_t)tgt_iaddr); + PRINTF(" * address (before) : %llx\n",(blob_t)tgt_iaddr); r_tgt_srcid = p_vci_tgt.srcid.read(); @@ -1231,5 +1258,5 @@ << "BROADCAST " << std::hex - << " L " << std::setw(10) << (uint64_t)tgt_addr + << " L " << std::setw(10) << (blob_t)tgt_addr << std::dec << " - " << tgt_num_cache @@ -1268,5 +1295,5 @@ << "INVAL DATA " << std::hex - << " L " << std::setw(10) << (uint64_t)tgt_addr + << " L " << std::setw(10) << (blob_t)tgt_addr << std::dec << " - " << tgt_num_cache @@ -1301,5 +1328,5 @@ << "INVAL INS " << std::hex - << " L " << std::setw(10) << (uint64_t)tgt_addr + << " L " << std::setw(10) << (blob_t)tgt_addr << std::dec << " - " << tgt_num_cache @@ -1334,5 +1361,5 @@ << "UPT DATA " << std::hex - << " L " << std::setw(10) << (uint64_t)tgt_addr + << " L " << std::setw(10) << (blob_t)tgt_addr << std::dec << " - " << tgt_num_cache @@ -1359,5 +1386,5 @@ << "UPT INS " << std::hex - << " L " << std::setw(10) << (uint64_t)tgt_addr + << " L " << std::setw(10) << (blob_t)tgt_addr << std::dec << " - " << tgt_num_cache @@ -1374,5 +1401,5 @@ r_tgt_iaddr = tgt_iaddr; r_tgt_daddr = tgt_daddr; - PRINTF(" * address (after) : i %llx, d %llx\n",(uint64_t)tgt_iaddr,(uint64_t)tgt_daddr); + PRINTF(" * address (after) : i %llx, d %llx\n",(blob_t)tgt_iaddr,(blob_t)tgt_daddr); } // end if cmdval @@ -1562,5 +1589,5 @@ // } - PRINTF(" * icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp); + PRINTF(" * icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp[r_tgt_num_cache]); PRINTF(" * dcache_rsp[%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); // if there is no need for a response @@ -1816,9 +1843,5 @@ if ( icache_cached ) { -#if CC_XCACHE_WRAPPER_SELECT_VICTIM r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; -#else - r_icache_fsm [num_cache] = ICACHE_MISS_WAIT; -#endif r_icache_miss_req[num_cache] = true; @@ -1844,5 +1867,4 @@ } ////////////////////// -#if CC_XCACHE_WRAPPER_SELECT_VICTIM case ICACHE_MISS_VICTIM: { @@ -1863,5 +1885,4 @@ break; } -#endif ////////////////////// case ICACHE_MISS_WAIT: @@ -1888,11 +1909,6 @@ r_icache_fsm[num_cache] = ICACHE_ERROR; } else { -#if not CC_XCACHE_WRAPPER_SELECT_VICTIM - if (not r_icache_cleanup_req[num_cache].read()) -#endif - { - r_icache_update_addr[num_cache] = 0; - r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; - } + r_icache_update_addr[num_cache] = 0; + r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; } } @@ -1941,39 +1957,12 @@ size_t word = r_icache_update_addr[num_cache].read(); vci_addr_t addr = (vci_addr_t) r_icache_addr_save [num_cache].read(); - size_t way = 0; - size_t set = 0; - -#if CC_XCACHE_WRAPPER_SELECT_VICTIM - way = r_icache_miss_way[num_cache].read(); - set = r_icache_miss_set[num_cache].read(); -#else - // need invalid rsp, don't select a victim - if (not r_icache_inval_rsp[num_cache]) - { - // First word : select an victim ! - if (word == 0) - { - vci_addr_t victim; - - // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state - r_icache_cleanup_req[num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set ); - r_icache[num_cache]->victim_update_tag(addr, way, set); - - r_icache_cleanup_line[num_cache] = (addr_40) victim; - r_icache_miss_way [num_cache] = way; - r_icache_miss_set [num_cache] = set; - } - else - { - way = r_icache_miss_way[num_cache].read(); - set = r_icache_miss_set[num_cache].read(); - } - } -#endif + size_t way = r_icache_miss_way[num_cache].read(); + size_t set = r_icache_miss_set[num_cache].read(); + bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,word); if (val) { - PRINTF(" * rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],m_icache_words); + PRINTF(" * rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],(int)m_icache_words); PRINTF(" * r_icache_inval_rsp : %d\n" ,num_cache,(int)r_icache_inval_rsp[num_cache]); PRINTF(" * ins : %x\n" ,num_cache,(int)CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); @@ -1994,8 +1983,6 @@ if (word >= m_icache_words) { -#if CC_XCACHE_WRAPPER_SELECT_VICTIM // in all case (inval_rsp or not), update the victim tag r_icache[num_cache]->victim_update_tag(addr, way, set); -#endif // Last word : if previous invalid_rsp, can cleanup, else update the TAG @@ -2017,11 +2004,4 @@ case ICACHE_CC_CLEANUP: { - // external cache invalidate request - if ( r_tgt_icache_req[num_cache]) - { - r_icache_fsm [num_cache] = ICACHE_CC_CHECK; - r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read(); - break; - } // cleanup if(not r_icache_cleanup_req[num_cache]){ @@ -2030,5 +2010,4 @@ r_icache_fsm [num_cache] = ICACHE_IDLE; - // FIXME : too many access at the cache in this cycle m_cpt_icache_dir_read += m_icache_ways; r_icache[num_cache]->inval((addr_40)r_icache_addr_save[num_cache]); @@ -2313,9 +2292,5 @@ m_cost_data_miss_frz++; r_dcache_miss_req [num_cache] = true; -#if CC_XCACHE_WRAPPER_SELECT_VICTIM r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; -#else - r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; -#endif } else { @@ -2425,7 +2400,8 @@ set_num_dcache(addr,num_cache); - // FIXME : virer le set_num_dcache ! - valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached); - + // FIXME : + // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) + // * pour cela, virer le set_num_dcache ! + valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); PRINTF(" * r_wbuf valid : %d\n",num_cache,valid); @@ -2485,5 +2461,4 @@ } ////////////////////// -#if CC_XCACHE_WRAPPER_SELECT_VICTIM case DCACHE_MISS_VICTIM: { @@ -2501,5 +2476,5 @@ r_dcache_miss_set [num_cache] = set; - PRINTF(" * MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (uint64_t)victim, way, set); + PRINTF(" * MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (blob_t)victim, (int)way, (int)set); r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; @@ -2508,5 +2483,4 @@ break; } -#endif ////////////////////// case DCACHE_MISS_WAIT: @@ -2530,11 +2504,6 @@ else { -#if not CC_XCACHE_WRAPPER_SELECT_VICTIM - if (not r_dcache_cleanup_req[num_cache].read()) -#endif - { - r_dcache_update_addr[num_cache] = 0; - r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; - } + r_dcache_update_addr[num_cache] = 0; + r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; } } @@ -2546,36 +2515,8 @@ size_t word = r_dcache_update_addr[num_cache].read(); vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read(); - size_t way = 0; - size_t set = 0; + size_t way = r_dcache_miss_way[num_cache].read(); + size_t set = r_dcache_miss_set[num_cache].read(); - // need invalid rsp, don't select a victim -#if CC_XCACHE_WRAPPER_SELECT_VICTIM - way = r_dcache_miss_way[num_cache].read(); - set = r_dcache_miss_set[num_cache].read(); -#else - if (not r_dcache_inval_rsp[num_cache] ) - { - // First word : select an victim ! - if (word == 0) - { - vci_addr_t victim; - - // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT - r_dcache_cleanup_req [num_cache] = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set ); - r_dcache[num_cache]->victim_update_tag(addr, way, set); - r_dcache_cleanup_line[num_cache] = (addr_40) victim; - - r_dcache_miss_way [num_cache] = way; - r_dcache_miss_set [num_cache] = set; - } - else - { - way = r_dcache_miss_way[num_cache].read(); - set = r_dcache_miss_set[num_cache].read(); - } - } -#endif - - PRINTF(" * MISS_UPDT : Victim way %d, set %d\n",num_cache, way, set); + PRINTF(" * MISS_UPDT : Victim way %d, set %d\n",num_cache, (int)way, (int)set); if (CACHE_MISS_BUF_RSP_VAL(d,num_cache,word)) @@ -2598,9 +2539,7 @@ if (word >= m_dcache_words) { -#if CC_XCACHE_WRAPPER_SELECT_VICTIM // in all case (inval_rsp or not), update the victim tag // because victim is already cleanup r_dcache[num_cache]->victim_update_tag(addr, way, set); -#endif // Last word : if previous invalid_rsp, can cleanup, else update the TAG @@ -2736,4 +2675,5 @@ PRINTF(" * CC_CHECK\n",num_cache); + // if((r_dcache_fsm_save[num_cache] == DCACHE_MISS_WAIT) and ((r_dcache_addr_save[num_cache].read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { @@ -2886,11 +2826,4 @@ case DCACHE_CC_CLEANUP: { - // external cache invalidate request - if ( r_tgt_dcache_req[num_cache] ) - { - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; - break; - } // cleanup if(not r_dcache_cleanup_req[num_cache]){ @@ -2899,5 +2832,4 @@ r_dcache_fsm [num_cache] = DCACHE_IDLE; - // FIXME : too many access at the cache in this cycle m_cpt_dcache_dir_read += m_dcache_ways; r_dcache[num_cache]->inval((addr_40)r_dcache_addr_save[num_cache]); @@ -3108,5 +3040,5 @@ r_cleanup_num_cache = num_cache; - PRINTF(" * address : %llx\n",((cleanup_icache_req)?((uint64_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()< address : %llx\n",((cleanup_icache_req)?((blob_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()< dcache_miss_req (before) : %d\n",dcache_miss_req); -// #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) -// // 1) two access authorized -// dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; -// icache_miss_req = r_icache_miss_req[cache_miss_num_cache]; -// #el -#if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) - // 2) one access with static priority (dcache prior) +#if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) + // 1) one access with static priority (dcache prior) icache_miss_req &= not dcache_miss_req; +#elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) + // 2) one access with static priority (icache prior) + dcache_miss_req &= not icache_miss_req; #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3) - // 3) one access with static priority (icache prior) - dcache_miss_req &= not icache_miss_req; -#elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) - // 4) one access with round robin priority + // 3) one access with round robin priority dcache_miss_req = ((dcache_miss_req and not icache_miss_req) or // only dcache (dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior icache_miss_req &= not dcache_miss_req; +// #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) +// // 4) two access authorized +// dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; +// icache_miss_req = r_icache_miss_req[cache_miss_num_cache]; #else #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY" @@ -3278,5 +3209,5 @@ addr = (icache_miss_req)?r_icache_addr_save[icache_miss_num_cache].read():r_dcache_addr_save[dcache_miss_num_cache].read(); - PRINTF(" * addr : %llx\n",(uint64_t)addr); + PRINTF(" * addr : %llx\n",(blob_t)addr); if (icache_miss_req) @@ -3291,5 +3222,5 @@ set_num_dcache(addr,dcache_miss_num_cache); - PRINTF(" * addr : %llx\n",(uint64_t)addr); + PRINTF(" * addr : %llx\n",(blob_t)addr); } } @@ -3335,6 +3266,6 @@ << "(" << dcache_miss_num_cache << ") " << std::hex - << " @ " << std::setw(10) << (uint64_t)addr - << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" + << " @ " << std::setw(10) << (blob_t)addr + << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" << std::dec << std::endl; @@ -3362,6 +3293,6 @@ << "(" << dcache_unc_num_cache << ") " << std::hex - << " @ " << std::setw(10) << (uint64_t)addr - << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" + << " @ " << std::setw(10) << (blob_t)addr + << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" << std::dec << std::endl; @@ -3386,6 +3317,6 @@ << "(" << icache_miss_num_cache << ") " << std::hex - << " @ " << std::setw(10) << (uint64_t)addr - << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_icache_yzmask) << ")" + << " @ " << std::setw(10) << (blob_t)addr + << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")" << std::dec << std::endl; @@ -3412,6 +3343,6 @@ << "(" << icache_unc_num_cache << ") " << std::hex - << " @ " << std::setw(10) << (uint64_t)addr - << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_icache_yzmask) << ")" + << " @ " << std::setw(10) << (blob_t)addr + << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")" << std::dec << std::endl; @@ -3440,6 +3371,6 @@ << "(" << dcache_write_num_cache << ") " << std::hex - << " @ " << std::setw(10) << (uint64_t)addr - << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" + << " @ " << std::setw(10) << (blob_t)addr + << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" << " [" << wbuf_min << ":" << wbuf_max << "]" << " {" << wbuf_index << "}" @@ -3469,6 +3400,6 @@ << "(" << dcache_sc_num_cache << ") " << std::hex - << " @ " << std::setw(10) << (uint64_t)addr - << " (L " << std::setw(10) << ((uint64_t)addr&(uint64_t)m_dcache_yzmask) << ")" + << " @ " << std::setw(10) << (blob_t)addr + << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" << std::dec << std::endl; @@ -3737,5 +3668,6 @@ "A VCI response packet must contain one flit for a write transaction"); r_vci_rsp_fsm = RSP_IDLE; - bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1))); + uint32_t wbuf_index = p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)); + bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(wbuf_index); PRINTF(" * cached : %d\n",cached); @@ -3744,6 +3676,6 @@ r_dcache_previous_unc[r_vci_rsp_num_cache] = false; - // FIXME : r_vci_rsp_num_cache != num_cpu ! -> pktid - if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss[r_vci_rsp_num_cache]->setWriteBerr(); + if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) + m_iss[r_wbuf[r_vci_rsp_num_cache]->getCpuId(wbuf_index)]->setWriteBerr(); } break; @@ -3821,5 +3753,5 @@ set_num_icache(addr,r_cleanup_num_cache); - PRINTF(" * icache : %llx\n",(uint64_t)addr); + PRINTF(" * icache : %llx\n",(blob_t)addr); } else @@ -3828,5 +3760,5 @@ set_num_dcache(addr,r_cleanup_num_cache); - PRINTF(" * dcache : %llx\n",(uint64_t)addr); + PRINTF(" * dcache : %llx\n",(blob_t)addr); } @@ -3920,5 +3852,5 @@ set_num_dcache(addr,r_vci_cmd_num_cache); - PRINTF(" * DATA_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); + PRINTF(" * DATA_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); p_vci_ini_rw.address = addr; @@ -3957,5 +3889,5 @@ set_num_dcache(addr,r_vci_cmd_num_cache); - PRINTF(" * DATA_SC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); + PRINTF(" * DATA_SC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); p_vci_ini_rw.address = addr; @@ -3993,5 +3925,5 @@ addr_40 addr = (addr_40) r_wbuf[r_vci_cmd_num_cache]->getAddress(r_vci_cmd_cpt)&~0x3; - PRINTF(" * DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); + PRINTF(" * DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); p_vci_ini_rw.address = addr; @@ -4019,5 +3951,5 @@ set_num_dcache(addr,r_vci_cmd_num_cache); - PRINTF(" * DATA_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); + PRINTF(" * DATA_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); p_vci_ini_rw.address = addr; @@ -4044,5 +3976,5 @@ set_num_icache(addr,r_vci_cmd_num_cache); - PRINTF(" * INS_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); + PRINTF(" * INS_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); p_vci_ini_rw.address = addr; @@ -4069,5 +4001,5 @@ set_num_icache(addr,r_vci_cmd_num_cache); - PRINTF(" * INS_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(uint64_t)(addr)); + PRINTF(" * INS_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); p_vci_ini_rw.address = addr; @@ -4250,5 +4182,5 @@ ////////////////////////////////////////////////////////////////////////////////// - // fixme : mettre le type addr_40 + // FIXME : mettre le type addr_40 tmpl(sc_dt::sc_uint<40>)::set_num_cache_only(addr_40 addr, uint32_t num_cache) ////////////////////////////////////////////////////////////////////////////////// Index: /trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h =================================================================== --- /trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h (revision 142) +++ /trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h (revision 143) @@ -7,5 +7,5 @@ #include "arithmetics.h" -#define L1_MULTI_CACHE 1 +#define L1_MULTI_CACHE 1 //#define RANDOM_EVICTION Index: /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp =================================================================== --- /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 142) +++ /trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (revision 143) @@ -29,15 +29,18 @@ #include "../include/vci_mem_cache_v4.h" -// #define TDEBUG // Transaction tab debug -// #define IDEBUG // Update tab debug -// #define DDEBUG // Directory debug -// #define LOCK_DEBUG // Lock debug - #define DEBUG_VCI_MEM_CACHE 0 -#define DEBUG_START_CYCLE 949900 +#define DEBUG_START_CYCLE 1500 #define RANDOMIZE_SC #define ASSERT_VERBOSE #define ASSERT_NCYCLES m_cpt_cycles + +#if DEBUG_VCI_MEM_CACHE +#define TDEBUG // Transaction tab debug +#define IDEBUG // Update tab debug +#define DDEBUG // Directory debug +#define LOCK_DEBUG // Lock debug +#endif + #include "debug.h" @@ -2660,4 +2663,6 @@ bool match_heap = match_heap_srcid and match_heap_cache_id and match_heap_inst; + PRINTF(" * %s - srcid %d\n",name().c_str(),r_cleanup_srcid.read()); + #if L1_MULTI_CACHE PRINTF(" * match_dir %d (match_dir_srcid %d, match_dir_cache_id %d, match_dir_inst %d)\n", @@ -2683,9 +2688,9 @@ if(match_dir){ DirectoryEntry dir_entry; - dir_entry.valid = true; + dir_entry.valid = true; dir_entry.is_cnt = r_cleanup_is_cnt.read(); - dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.dirty = r_cleanup_dirty.read(); dir_entry.tag = r_cleanup_tag.read(); - dir_entry.lock = r_cleanup_lock.read(); + dir_entry.lock = r_cleanup_lock.read(); dir_entry.ptr = heap_entry.next; dir_entry.count = r_cleanup_count.read()-1; Index: /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg =================================================================== --- /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg (revision 142) +++ /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg (revision 143) @@ -1,4 +1,4 @@ -4 -1 1 +1 +4 4 4 64 16 4 64 16 Index: /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h =================================================================== --- /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h (revision 142) +++ /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h (revision 143) @@ -3,5 +3,5 @@ // List of benchmark -#define BENCHMARK_NB_THREAD 4 +#define BENCHMARK_NB_THREAD 1 #define BENCHMARK_DHRYSTONE 0 @@ -26,5 +26,5 @@ #define SORT_INSERTION_SIZE 2300 #define SORT_SELECTION_SIZE 1600 -#define SORT_SHELL_SIZE 4000 +#define SORT_SHELL_SIZE 5000 #define MATRIX_MULTIPLICATION_ST_SIZE 50 #define MATRIX_MULTIPLICATION_MT_SIZE 96 Index: /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp =================================================================== --- /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp (revision 142) +++ /trunk/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp (revision 143) @@ -207,5 +207,5 @@ maptabp.add(Segment("mc_r" , MC_R_BASE , MC_R_SIZE , IntTab(2), false, true, IntTab(0))); maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true)); - // maptabp.add(Segment("mc_u" , MC_U_BASE , MC_U_SIZE , IntTab(2), false)); + //maptabp.add(Segment("mc_u" , MC_U_BASE , MC_U_SIZE , IntTab(2), false)); //maptabp.add(Segment("ptba" , PTD_ADDR , TAB_SIZE , IntTab(2), true)); maptabp.add(Segment("xicu" , XICU_BASE , XICU_SIZE , IntTab(3), false));