Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h =================================================================== --- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (revision 146) +++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h (revision 147) @@ -31,5 +31,4 @@ #include -#include #include #include @@ -43,10 +42,12 @@ /* + * CC_XCACHE_WRAPPER_SELECT_VICTIM : + * The selection and the update of cache (after a read miss) + * are separated in two step + * Also, the cleanup can be send in parallel at the read miss. + * * CC_XCACHE_WRAPPER_FIFO_RSP * Two simple fifo (each 2x32 depth) receive the cache line from * RAM. Instead of two buffers (m_icache_words and m_dcache_words) - * 1 - nb_icache+nb_dcache simple fifo - * 2 - 2 simple fifo - * else - two buffers (m_icache_words and m_dcache_words) * * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE @@ -65,25 +66,9 @@ * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req - * 1 - one access with static priority (dcache prior) - * 2 - one access with static priority (icache prior) - * 3 - one access with round robin priority - * 4 - two access authorized - * - * CC_XCACHE_WRAPPER_MULTI_CACHE : - * 1 - icache static partitionnement - * 2 - icache dedicated - * - * CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS - * (In multi-cache) - * A dcache used by a cpu and in miss_wait state can be use by - * an another cpu to make a load cached access. - * - * CC_XCACHE_WRAPPER_STORE_AFTER_STORE - * Store access in dcache (and hit) is make in two cycle : - * - first read directory and read data - * - second make a mask with old data and write new data. - * If data part has a write enable per byte, read data access can be suppress - * and we can pipeline consecutive store access. - * + * 1 - two access authorized + * 2 - one access with static priority (dcache prior) + * 3 - one access with static priority (icache prior) + * 4 - one access with round robin priority + * * CC_XCACHE_WRAPPER_STOP_SIMULATION : * stop simulation if processor is stall after a long time @@ -96,63 +81,39 @@ * Number of cycle before to prinf debug message * - * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - * Print transaction between : - * - the cpu and the cache (icache and dcache) - * - vci - * - cleanup - * - coherency + * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION + * Print transaction between the cpu and the cache */ // implementation +#ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM +#define CC_XCACHE_WRAPPER_SELECT_VICTIM 0 +#endif #ifndef CC_XCACHE_WRAPPER_FIFO_RSP -#define CC_XCACHE_WRAPPER_FIFO_RSP 2 +#define CC_XCACHE_WRAPPER_FIFO_RSP 0 #endif #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE -#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 +#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 #endif #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT -#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 +#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 #endif #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME -#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 2 +#define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0 #endif #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY -#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 3 -#endif -#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE -#define CC_XCACHE_WRAPPER_MULTI_CACHE 2 -// if multi_cache : -// /modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 -// /soclib/lib/multi_write_buffer/include/multi_write_buffer.h : CC_XCACHE_MULTI_CACHE 1 -#endif -#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS -#define CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS 1 -#endif -#ifndef CC_XCACHE_WRAPPER_STORE_AFTER_STORE -#define CC_XCACHE_WRAPPER_STORE_AFTER_STORE 1 -#endif - +#define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 +#endif // debugging -#ifndef CC_XCACHE_WRAPPER_VERBOSE -#define CC_XCACHE_WRAPPER_VERBOSE 1 -#endif #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION -#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 +#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 #endif #ifndef CC_XCACHE_WRAPPER_DEBUG -#define CC_XCACHE_WRAPPER_DEBUG 0 +#define CC_XCACHE_WRAPPER_DEBUG 0 #endif #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN -#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 1500 -#endif -#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION -#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 -#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" -#endif - -// don't change -#if not CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE -#undef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT -#define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 0 +#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 +#endif +#ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION +#define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 #endif @@ -178,5 +139,7 @@ DCACHE_IDLE, DCACHE_WRITE_UPDT, +#if CC_XCACHE_WRAPPER_SELECT_VICTIM DCACHE_MISS_VICTIM, +#endif DCACHE_MISS_WAIT, DCACHE_MISS_UPDT, @@ -194,5 +157,7 @@ enum icache_fsm_state_e { ICACHE_IDLE, +#if CC_XCACHE_WRAPPER_SELECT_VICTIM ICACHE_MISS_VICTIM, +#endif ICACHE_MISS_WAIT, ICACHE_MISS_UPDT, @@ -239,7 +204,6 @@ enum cleanup_fsm_state_e { CLEANUP_IDLE, - CLEANUP_REQ, - CLEANUP_RSP_DCACHE, - CLEANUP_RSP_ICACHE, + CLEANUP_DCACHE, + CLEANUP_ICACHE, }; @@ -267,5 +231,5 @@ sc_in p_clk; sc_in p_resetn; - sc_in ** p_irq;//[m_nb_cpu][iss_t::n_irq]; + sc_in p_irq[iss_t::n_irq]; soclib::caba::VciInitiator p_vci_ini_rw; soclib::caba::VciInitiator p_vci_ini_c; @@ -277,12 +241,8 @@ const soclib::common::AddressDecodingTable m_cacheability_table; const soclib::common::Segment m_segment; - iss_t ** m_iss; //[m_nb_cpu] + iss_t m_iss; const uint32_t m_srcid_rw; const uint32_t m_srcid_c; - const size_t m_nb_cpu; - const size_t m_nb_icache; - const size_t m_nb_dcache; - const size_t m_nb_cache; const size_t m_dcache_ways; const size_t m_dcache_words; @@ -298,48 +258,41 @@ bool m_stop_simulation; uint32_t m_stop_simulation_nb_frz_cycles_max; - uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] + uint32_t m_stop_simulation_nb_frz_cycles; #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION // REGISTERS - sc_signal r_cpu_prior; - sc_signal * r_icache_lock;//[m_nb_icache] - sc_signal * r_dcache_lock;//[m_nb_dcache] - sc_signal * r_dcache_sync;//[m_nb_dcache] - - sc_signal * r_dcache_fsm; //[m_nb_dcache] - sc_signal * r_dcache_fsm_save; //[m_nb_dcache] - sc_signal * r_dcache_addr_save; //[m_nb_dcache] - sc_signal * r_dcache_wdata_save; //[m_nb_dcache] - sc_signal * r_dcache_rdata_save; //[m_nb_dcache] - sc_signal * r_dcache_type_save; //[m_nb_dcache] - sc_signal * r_dcache_be_save; //[m_nb_dcache] - sc_signal * r_dcache_cached_save; //[m_nb_dcache] - sc_signal * r_dcache_cleanup_req; //[m_nb_dcache] - sc_signal * r_dcache_cleanup_line; //[m_nb_dcache] - sc_signal * r_dcache_miss_req; //[m_nb_dcache] - sc_signal * r_dcache_miss_way; //[m_nb_dcache] - sc_signal * r_dcache_miss_set; //[m_nb_dcache] - sc_signal * r_dcache_unc_req; //[m_nb_dcache] - sc_signal * r_dcache_sc_req; //[m_nb_dcache] - sc_signal * r_dcache_inval_rsp; //[m_nb_dcache] - sc_signal * r_dcache_update_addr; //[m_nb_dcache] - sc_signal ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] - sc_signal ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] - sc_signal ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] - sc_signal * r_dcache_num_cpu_save; //[m_nb_dcache] - sc_signal * r_dcache_previous_unc; //[m_nb_dcache] - - sc_signal * r_icache_fsm; //[m_nb_icache] - sc_signal * r_icache_fsm_save; //[m_nb_icache] - sc_signal * r_icache_addr_save; //[m_nb_icache] - sc_signal * r_icache_miss_req; //[m_nb_icache] - sc_signal * r_icache_miss_way; //[m_nb_icache] - sc_signal * r_icache_miss_set; //[m_nb_icache] - sc_signal * r_icache_unc_req; //[m_nb_icache] - sc_signal * r_icache_cleanup_req; //[m_nb_icache] - sc_signal * r_icache_cleanup_line; //[m_nb_icache] - sc_signal * r_icache_inval_rsp; //[m_nb_icache] - sc_signal * r_icache_update_addr; //[m_nb_icache] - sc_signal * r_icache_buf_unc_valid;//[m_nb_icache] + sc_signal r_dcache_fsm; + sc_signal r_dcache_fsm_save; + sc_signal r_dcache_addr_save; + sc_signal r_dcache_wdata_save; + sc_signal r_dcache_rdata_save; + sc_signal r_dcache_type_save; + sc_signal r_dcache_be_save; + sc_signal r_dcache_cached_save; + sc_signal r_dcache_cleanup_req; + sc_signal r_dcache_cleanup_line; + sc_signal r_dcache_miss_req; + sc_signal r_dcache_miss_way; + sc_signal r_dcache_miss_set; + sc_signal r_dcache_unc_req; + sc_signal r_dcache_sc_req; + sc_signal r_dcache_inval_rsp; + sc_signal r_dcache_update_addr; + sc_signal r_dcache_ll_data; + sc_signal r_dcache_ll_addr; + sc_signal r_dcache_ll_valid; + sc_signal r_dcache_previous_unc; + + sc_signal r_icache_fsm; + sc_signal r_icache_fsm_save; + sc_signal r_icache_addr_save; + sc_signal r_icache_miss_req; + sc_signal r_icache_miss_way; + sc_signal r_icache_miss_set; + sc_signal r_icache_unc_req; + sc_signal r_icache_cleanup_req; + sc_signal r_icache_cleanup_line; + sc_signal r_icache_inval_rsp; + sc_signal r_icache_update_addr; sc_signal r_vci_cmd_fsm; @@ -348,33 +301,24 @@ sc_signal r_vci_cmd_cpt; sc_signal r_vci_cmd_dcache_prior; - sc_signal r_vci_cmd_num_cache; - + sc_signal r_vci_rsp_fsm; + sc_signal r_vci_rsp_ins_error; + sc_signal r_vci_rsp_data_error; sc_signal r_vci_rsp_cpt; - bool s_vci_rsp_ack; - sc_signal r_vci_rsp_num_cache; - sc_signal * r_vci_rsp_ins_error; //[m_nb_icache] - sc_signal * r_vci_rsp_data_error; //[m_nb_dcache] - -#if (CC_XCACHE_WRAPPER_FIFO_RSP==1) - std::queue * r_icache_miss_buf; //[m_nb_icache] - std::queue * r_dcache_miss_buf; //[m_nb_dcache] -#elif (CC_XCACHE_WRAPPER_FIFO_RSP==2) - typedef struct - { - data_t data; - uint32_t num_cache; - } miss_buf_t; - - std::queue r_icache_miss_buf; - std::queue r_dcache_miss_buf; + sc_signal r_vci_rsp_ack; + +#if CC_XCACHE_WRAPPER_FIFO_RSP + std::queue r_icache_miss_buf; + std::queue r_dcache_miss_buf; #else - bool ** r_icache_miss_val; //[m_nb_icache][m_icache_words] - data_t ** r_icache_miss_buf; //[m_nb_icache][m_icache_words] - bool ** r_dcache_miss_val; //[m_nb_dcache][m_dcache_words] - data_t ** r_dcache_miss_buf; //[m_nb_dcache][m_dcache_words] -#endif - data_t * r_tgt_buf; //[m_cache_words] - be_t * r_tgt_be; //[m_cache_words] + bool *r_icache_miss_val; //[m_icache_words] + data_t *r_icache_miss_buf; //[m_icache_words] + bool *r_dcache_miss_val; //[m_dcache_words] + data_t *r_dcache_miss_buf; //[m_dcache_words] +#endif + sc_signal r_icache_buf_unc_valid; + + data_t *r_tgt_buf; //[m_cache_words] + be_t *r_tgt_be; //[m_cache_words] #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE sc_signal r_cache_word; @@ -382,6 +326,5 @@ sc_signal r_vci_tgt_fsm; - sc_signal r_tgt_iaddr; - sc_signal r_tgt_daddr; + sc_signal r_tgt_addr; sc_signal r_tgt_word; sc_signal r_tgt_update; @@ -392,101 +335,64 @@ sc_signal r_tgt_trdid; //sc_signal r_tgt_plen; - sc_signal r_tgt_num_cache; - sc_signal * r_tgt_icache_req; //[m_nb_icache] - sc_signal * r_tgt_icache_rsp; //[m_nb_icache] - sc_signal * r_tgt_dcache_req; //[m_nb_dcache] - sc_signal * r_tgt_dcache_rsp; //[m_nb_dcache] + sc_signal r_tgt_icache_req; + sc_signal r_tgt_dcache_req; + sc_signal r_tgt_icache_rsp; + sc_signal r_tgt_dcache_rsp; sc_signal r_cleanup_fsm; // controls initiator port of the coherence network - sc_signal r_cleanup_num_cache; - sc_signal r_cleanup_icache; - - MultiWriteBuffer** r_wbuf; - GenericCache ** r_icache; - GenericCache ** r_dcache; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - std::ofstream * log_transaction_file_icache; //[m_nb_cpu] - std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] - std::ofstream log_transaction_file_cmd; - std::ofstream log_transaction_file_tgt; - std::ofstream log_transaction_file_cleanup; + + MultiWriteBuffer r_wbuf; + GenericCache r_icache; + GenericCache r_dcache; + +#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION + std::ofstream log_dcache_transaction_file; #endif // Activity counters - uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ - uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE - uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ - uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE - - uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ - uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE - uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ - uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE - - uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) - uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) - uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets - uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets - uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets - uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets - uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets - - uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen - uint32_t m_cpt_total_cycles; // total number of cycles - - uint32_t m_cpt_data_read; // number of data read - uint32_t m_cpt_data_read_miss; // number of data read miss - uint32_t m_cpt_data_read_uncached; // number of data read uncached - uint32_t m_cpt_data_write; // number of data write - uint32_t m_cpt_data_write_miss; // number of data write miss - uint32_t m_cpt_data_write_uncached; // number of data write uncached - uint32_t m_cpt_ins_miss; // * number of instruction miss - - uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer - uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss - uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read - uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss - - uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions - uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions - uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions - uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions - - uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions - uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions - uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions - uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions - uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions - - uint32_t * m_cpt_icache_access; //[m_nb_icache] - uint32_t * m_cpt_dcache_access; //[m_nb_dcache] - uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] - uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] - uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] - uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] - uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] - - uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] - uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] - uint32_t * m_cpt_fsm_cmd; - uint32_t * m_cpt_fsm_rsp; - uint32_t * m_cpt_fsm_tgt; - uint32_t * m_cpt_fsm_cleanup; - - // Non blocking multi-cache - typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] - typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] - bool * ireq_cached ; //[m_nb_icache] - uint32_t * ireq_num_cpu; //[m_nb_dcache] - typename iss_t::DataRequest * dreq ; //[m_nb_dcache] - typename iss_t::DataResponse * drsp ; //[m_nb_dcache] - bool * dreq_cached ; //[m_nb_dcache] - uint32_t * dreq_num_cpu; //[m_nb_dcache] - - const uint32_t m_num_cache_LSB; - const uint32_t m_num_cache_MSB; - addr_40 m_num_cache_LSB_mask; - addr_40 m_num_cache_mask; + uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ + uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE + uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ + uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE + + uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ + uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE + uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ + uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE + + uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) + uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) + uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets + uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets + uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets + uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets + uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets + + uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen + uint32_t m_cpt_total_cycles; // total number of cycles + + uint32_t m_cpt_data_read; // number of data read + uint32_t m_cpt_data_read_miss; // number of data read miss + uint32_t m_cpt_data_read_uncached; // number of data read uncached + uint32_t m_cpt_data_write; // number of data write + uint32_t m_cpt_data_write_miss; // number of data write miss + uint32_t m_cpt_data_write_uncached; // number of data write uncached + uint32_t m_cpt_ins_miss; // * number of instruction miss + + uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer + uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss + uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read + uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss + + uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions + uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions + uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions + uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions + + uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions + uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions + uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions + uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions + uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions protected: @@ -503,6 +409,4 @@ const soclib::common::IntTab &initiator_index_c, const soclib::common::IntTab &target_index, - size_t nb_cpu, - size_t nb_cache, size_t icache_ways, size_t icache_sets, @@ -518,7 +422,7 @@ ~VciCcXCacheWrapperV4(); - void print_trace(size_t mode = 0); - void print_cpi(); - void print_stats(bool print_wbuf=true, bool print_fsm=true); + void print_trace(size_t mode = 0); + void print_cpi(); + void print_stats(); // #if CC_XCACHE_WRAPPER_STOP_SIMULATION @@ -531,10 +435,5 @@ void genMoore(); - uint32_t get_num_cache (addr_40 & addr); - uint32_t get_num_cache_only(addr_40 addr); - void set_num_cache (addr_40 & addr, uint32_t num_cache); - addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); - - soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); + soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); }; Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp =================================================================== --- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (revision 146) +++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (revision 147) @@ -55,150 +55,49 @@ /////////////////////////////////////////////////////////////////////////////// +#include #include #include "arithmetics.h" -#include "size.h" #include "../include/vci_cc_xcache_wrapper_v4.h" -// =====[ DEBUG ]==================================== - -#define ASSERT_VERBOSE -#define ASSERT_NCYCLES m_cpt_total_cycles - -#include "debug.h" - #if CC_XCACHE_WRAPPER_DEBUG -# define PRINTF(msg...) PRINTF_COND(m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN,msg) +# define PRINTF(msg...) do { if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) printf(msg); } while (0); #else # define PRINTF(msg...) #endif -// =====[ FIFO_RSP ]================================= - -#if (CC_XCACHE_WRAPPER_FIFO_RSP==1) -# define CACHE_MISS_BUF_ALLOC do { \ - r_icache_miss_buf = new std::queue [m_nb_icache]; \ - r_dcache_miss_buf = new std::queue [m_nb_dcache]; \ - } while (0) -# define CACHE_MISS_BUF_DEALLOC do { \ - delete [] r_icache_miss_buf; \ - delete [] r_dcache_miss_buf; \ - } while (0) -# define CACHE_MISS_BUF_RESET(c) do { \ - for (uint32_t x=0; x0) { \ - r_##c##cache_miss_buf[x].pop(); \ - } \ - } \ - } while (0) -# define CACHE_MISS_BUF_REQ_INIT(c,x) -# define CACHE_MISS_BUF_RSP_VAL(c,x,n) (r_##c##cache_miss_buf[x].size()>0) -# define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf[x].size()<2) -# define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf[x].front() -# define CACHE_MISS_BUF_RSP_POP(c,x) do { \ - r_##c##cache_miss_buf[x].pop(); \ - } while (0) -# define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ - r_##c##cache_miss_buf[x].push(d); \ - } while (0) -# define CACHE_MISS_BUF_RSP_PRINT(c) do { \ - for (uint32_t x=0; x0) { \ - r_##c##cache_miss_buf.pop(); \ - } \ - } while (0) -# define CACHE_MISS_BUF_REQ_INIT(c,x) -# define CACHE_MISS_BUF_RSP_VAL(c,x,n) ((r_##c##cache_miss_buf.size()>0) and (r_##c##cache_miss_buf.front().num_cache==x)) -# define CACHE_MISS_BUF_RSP_ACK(c,x) (r_##c##cache_miss_buf.size()<2) -# define CACHE_MISS_BUF_RSP_DATA(c,x,n) r_##c##cache_miss_buf.front().data -# define CACHE_MISS_BUF_RSP_POP(c,x) do { \ - r_##c##cache_miss_buf.pop(); \ - } while (0) -# define CACHE_MISS_BUF_RSP_PUSH(c,x,n,d) do { \ - miss_buf_t miss_buf; \ - miss_buf.data = d; \ - miss_buf.num_cache = x; \ - r_##c##cache_miss_buf.push(miss_buf); \ - } while (0) -# define CACHE_MISS_BUF_RSP_PRINT(c) do { \ - PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size()); \ - } while (0) -#else -# define CACHE_MISS_BUF_ALLOC do { \ - r_icache_miss_val = new bool * [m_nb_icache]; \ - r_icache_miss_buf = new data_t * [m_nb_icache]; \ - for (uint32_t x=0; x0) {r_##c##cache_miss_buf.pop();} +# define CACHE_MISS_BUF_REQ_INIT(c) +# define CACHE_MISS_BUF_RSP_VAL(c,n) (r_##c##cache_miss_buf.size()>0) +# define CACHE_MISS_BUF_RSP_ACK(c) (r_##c##cache_miss_buf.size()<2) +# define CACHE_MISS_BUF_RSP_DATA(c,n) r_##c##cache_miss_buf.front() +# define CACHE_MISS_BUF_RSP_POP(c) do { r_##c##cache_miss_buf.pop();} while (0) +# define CACHE_MISS_BUF_RSP_PUSH(c,n,d) do { r_##c##cache_miss_buf.push(d);} while (0) +# define CACHE_MISS_BUF_RSP_PRINT(c) do { PRINTF(" * cache_miss_buf - size : %d\n",r_##c##cache_miss_buf.size());} while (0) #else -#error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE" +# define CACHE_MISS_BUF_ALLOC do { \ + r_icache_miss_val = new bool [m_icache_words]; \ + r_icache_miss_buf = new data_t[m_icache_words]; \ + r_dcache_miss_val = new bool [m_dcache_words]; \ + r_dcache_miss_buf = new data_t[m_dcache_words]; \ + } while (0) +# define CACHE_MISS_BUF_DEALLOC do { \ + delete [] r_icache_miss_val; \ + delete [] r_icache_miss_buf; \ + delete [] r_dcache_miss_val; \ + delete [] r_dcache_miss_buf; \ + } while (0) +# define CACHE_MISS_BUF_RESET(c) +# define CACHE_MISS_BUF_REQ_INIT(c) do {for (uint32_t i=0; i __VA_ARGS__ VciCcXCacheWrapperV4 @@ -289,6 +189,4 @@ const soclib::common::IntTab &initiator_index_c, const soclib::common::IntTab &target_index, - size_t nb_cpu, - size_t nb_dcache, size_t icache_ways, size_t icache_sets, @@ -312,26 +210,51 @@ m_cacheability_table(mtp.getCacheabilityTable()), m_segment(mtc.getSegment(target_index)), + m_iss(this->name(), proc_id), m_srcid_rw(mtp.indexForId(initiator_index_rw)), m_srcid_c(mtc.indexForId(initiator_index_c)), - m_nb_cpu(nb_cpu), -#if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) - m_nb_icache(nb_dcache), -#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) - m_nb_icache(m_nb_cpu), -#endif - m_nb_dcache(nb_dcache), - m_nb_cache((m_nb_dcache>m_nb_icache)?m_nb_dcache:m_nb_icache), m_dcache_ways(dcache_ways), m_dcache_words(dcache_words), - m_dcache_words_shift(uint32_log2(dcache_words)+uint32_log2(sizeof(data_t))), + m_dcache_words_shift(uint32_log2(dcache_words)+2), m_dcache_yzmask((~0)< 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines/m_nb_dcache)), - "Need more TRDID bits."); - - ASSERT(uint32_log2(nb_dcache) <= (1< 0), - "nb cpu must be a multiple of nb cache."); - - ASSERT(IS_POW_OF_2(m_icache_ways) and (m_nb_icache <= m_icache_ways), - "nb icache ways must be a multiple of nb cache."); - - ASSERT(IS_POW_OF_2(m_dcache_ways) and (m_nb_dcache <= m_dcache_ways), - "nb dcache ways must be a multiple of nb cache."); - - ASSERT(icache_words == dcache_words, - "icache_words must be equal at dcache_words."); - - ASSERT(IS_POW_OF_2(wbuf_nlines) and (m_nb_dcache <= wbuf_nlines), - "wbuf_nlines must be a multiple of nb cache."); - - // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE - ASSERT((m_nb_dcache == 1) or (dcache_words >= 16), - "When multi cache is activated, need 4 bits (16 word) to the cache set ."); - - if (m_nb_cpu > 1) - ASSERT(CC_XCACHE_MULTI_CPU!=0, - "Macro CC_XCACHE_MULTI_CPU in wbuf must be set at 1."); - - p_irq = new sc_in * [m_nb_cpu]; - for (uint32_t num_cpu=0; num_cpu [iss_t::n_irq]; - - m_iss = new iss_t * [m_nb_cpu]; - for (uint32_t num_cpu=0; num_cpuname() << "_" << num_cpu; - - m_iss[num_cpu] = new iss_t (iss_name.str().c_str(), proc_id+num_cpu); - } - + ASSERT( (icache_words*vci_param::B) < (1< 2) and ((1<<(vci_param::T-1)) >= wbuf_nlines), + "I need more TRDID bits"); + CACHE_MISS_BUF_ALLOC; - r_icache_lock = new sc_signal[m_nb_icache]; - r_dcache_lock = new sc_signal[m_nb_dcache]; - r_dcache_sync = new sc_signal [m_nb_dcache]; - - r_icache_fsm = new sc_signal [m_nb_icache]; - r_icache_fsm_save = new sc_signal [m_nb_icache]; - r_icache_addr_save = new sc_signal [m_nb_icache]; - r_icache_miss_req = new sc_signal [m_nb_icache]; - r_icache_miss_way = new sc_signal [m_nb_icache]; - r_icache_miss_set = new sc_signal [m_nb_icache]; - r_icache_unc_req = new sc_signal [m_nb_icache]; - r_icache_cleanup_req = new sc_signal [m_nb_icache]; - r_icache_cleanup_line = new sc_signal [m_nb_icache]; - r_icache_inval_rsp = new sc_signal [m_nb_icache]; - r_icache_update_addr = new sc_signal [m_nb_icache]; - r_icache_buf_unc_valid = new sc_signal [m_nb_icache]; - - r_dcache_fsm = new sc_signal [m_nb_dcache]; - r_dcache_fsm_save = new sc_signal [m_nb_dcache]; - r_dcache_addr_save = new sc_signal [m_nb_dcache]; - r_dcache_wdata_save = new sc_signal [m_nb_dcache]; - r_dcache_rdata_save = new sc_signal [m_nb_dcache]; - r_dcache_type_save = new sc_signal [m_nb_dcache]; - r_dcache_be_save = new sc_signal [m_nb_dcache]; - r_dcache_cached_save = new sc_signal [m_nb_dcache]; - r_dcache_cleanup_req = new sc_signal [m_nb_dcache]; - r_dcache_cleanup_line = new sc_signal [m_nb_dcache]; - r_dcache_miss_req = new sc_signal [m_nb_dcache]; - r_dcache_miss_way = new sc_signal [m_nb_dcache]; - r_dcache_miss_set = new sc_signal [m_nb_dcache]; - r_dcache_unc_req = new sc_signal [m_nb_dcache]; - r_dcache_sc_req = new sc_signal [m_nb_dcache]; - r_dcache_inval_rsp = new sc_signal [m_nb_dcache]; - r_dcache_update_addr = new sc_signal [m_nb_dcache]; - r_dcache_previous_unc = new sc_signal [m_nb_dcache]; - - r_dcache_num_cpu_save = new sc_signal [m_nb_dcache]; - r_dcache_ll_data = new sc_signal * [m_nb_dcache]; - r_dcache_ll_addr = new sc_signal * [m_nb_dcache]; - r_dcache_ll_valid = new sc_signal * [m_nb_dcache]; - for (uint32_t num_cache=0; num_cache [m_nb_cpu]; - r_dcache_ll_addr [num_cache] = new sc_signal [m_nb_cpu]; - r_dcache_ll_valid [num_cache] = new sc_signal [m_nb_cpu]; - } - - r_tgt_icache_req = new sc_signal [m_nb_icache]; - r_tgt_icache_rsp = new sc_signal [m_nb_icache]; - r_tgt_dcache_req = new sc_signal [m_nb_dcache]; - r_tgt_dcache_rsp = new sc_signal [m_nb_dcache]; - - r_tgt_buf = new data_t [m_cache_words]; - r_tgt_be = new be_t [m_cache_words]; - - r_vci_rsp_ins_error = new sc_signal [m_nb_icache]; - r_vci_rsp_data_error = new sc_signal [m_nb_dcache]; - - ireq = new typename iss_t::InstructionRequest [m_nb_icache]; - irsp = new typename iss_t::InstructionResponse [m_nb_icache]; - ireq_cached = new bool [m_nb_icache]; - ireq_num_cpu = new uint32_t [m_nb_dcache]; - - dreq = new typename iss_t::DataRequest [m_nb_dcache]; - drsp = new typename iss_t::DataResponse [m_nb_dcache]; - dreq_cached = new bool [m_nb_dcache]; - dreq_num_cpu = new uint32_t [m_nb_dcache]; - - m_cpt_icache_access = new uint32_t [m_nb_icache]; - m_cpt_dcache_access = new uint32_t [m_nb_dcache]; - m_cpt_icache_miss_victim_wait = new uint32_t [m_nb_icache]; - m_cpt_dcache_miss_victim_wait = new uint32_t [m_nb_dcache]; - -#if CC_XCACHE_WRAPPER_STORE_AFTER_STORE - m_cpt_dcache_store_after_store = new uint32_t [m_nb_dcache]; -#endif -#if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS - m_cpt_dcache_hit_after_miss_read = new uint32_t [m_nb_dcache]; - m_cpt_dcache_hit_after_miss_write = new uint32_t [m_nb_dcache]; -#endif - - m_cpt_fsm_dcache = new uint32_t * [m_nb_dcache]; - m_cpt_fsm_icache = new uint32_t * [m_nb_icache]; - for (uint32_t num_cache=0; num_cache Parameters :" << std::endl; - std::cout << " * nb_cpu : " << nb_cpu << std::endl; - std::cout << " * nb_cache : " << m_nb_icache << " icache(s), " << m_nb_dcache << " dcache(s)" << std::endl; - std::cout << " * icache (total) : " << icache_ways << " way(s), " << icache_sets << " set(s), " << icache_words << " word(s)" << std::endl; - std::cout << " * icache (per cache) : " << _icache_ways << " way(s), " << _icache_sets << " set(s), " << _icache_words << " word(s)" << std::endl; - std::cout << " * dcache (total) : " << dcache_ways << " way(s), " << dcache_sets << " set(s), " << dcache_words << " word(s)" << std::endl; - std::cout << " * dcache (per cache) : " << _dcache_ways << " way(s), " << _dcache_sets << " set(s), " << _dcache_words << " word(s)" << std::endl; - std::cout << " * wbuf (total) : " << wbuf_nlines << " line(s), " << wbuf_nwords << " word(s), timeout : " << wbuf_timeout << std::endl; - std::cout << " * wbuf (per cache) : " << _wbuf_nlines << " line(s), " << _wbuf_nwords << " word(s), timeout : " << _wbuf_timeout << std::endl; -#endif - - r_icache = new GenericCache * [m_nb_icache]; - r_dcache = new GenericCache * [m_nb_dcache]; - r_wbuf = new MultiWriteBuffer * [m_nb_dcache]; - - for (uint32_t num_cache=0; num_cache ("icache", _icache_ways, _icache_sets, _icache_words); - } - for (uint32_t num_cache=0; num_cache ("dcache", _dcache_ways, _dcache_sets, _dcache_words); - r_wbuf [num_cache] = new MultiWriteBuffer ("r_wbuf", _wbuf_nwords, _wbuf_nlines, _wbuf_timeout, _dcache_words); - } - - m_num_cache_LSB_mask = 0; - for (uint32_t i=0; isetCacheInfo(cache_info); - + m_iss.setCacheInfo(cache_info); + #if CC_XCACHE_WRAPPER_STOP_SIMULATION m_stop_simulation = false; - m_stop_simulation_nb_frz_cycles = new uint32_t [m_nb_cpu]; - for (uint32_t num_cpu=0; num_cpuprintStatistics(); + r_wbuf.printStatistics(); } @@ -954,18 +421,11 @@ typename iss_t::DataRequest dreq; + m_iss.getRequests( ireq, dreq ); std::cout << std::dec << "Proc \"" << name() << "\"" << std::endl; - - for (uint32_t num_cpu=0; num_cpugetRequests( ireq, dreq ); - std::cout << ireq << std::endl; - std::cout << dreq << std::endl; - } - for (uint32_t num_cache=0; num_cacheprintTrace((mode>>1)&1); + r_wbuf.printTrace((mode>>1)&1); } if(mode & 0x4) { std::cout << " Data cache" << std::endl; - for (uint32_t num_cache=0; num_cacheprintTrace(); + r_dcache.printTrace(); } if(mode & 0x8) { std::cout << " Instruction cache" << std::endl; - for (uint32_t num_cache=0; num_cacheprintTrace(); + r_icache.printTrace(); } + + // if(mode & 0x10) + // { + // std::cout << " Icache miss buffer : "; + // CACHE_MISS_BUF_RSP_PRINT(i); + // std::cout << std::endl; + + // std::cout << " Dcache miss buffer : "; + // CACHE_MISS_BUF_RSP_PRINT(d); + // std::cout << std::endl; + // } } @@ -997,24 +465,9 @@ if ( not p_resetn.read() ) { - r_cpu_prior = 0; - - for (uint32_t num_cpu=0; num_cpureset(); + m_iss.reset(); // FSM states - for (uint32_t num_cache=0; num_cachereset(); + r_wbuf.reset(); + r_icache.reset(); + r_dcache.reset(); // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs - r_icache_miss_req [num_cache] = false; - r_icache_unc_req [num_cache] = false; - r_icache_cleanup_req [num_cache] = false; - - // internal messages in DCACHE et ICACHE FSMs - r_icache_inval_rsp [num_cache] = false; - - // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs - r_icache_buf_unc_valid [num_cache] = false; + r_icache_miss_req = false; + r_icache_unc_req = false; + r_icache_cleanup_req = false; + r_dcache_miss_req = false; + r_dcache_unc_req = false; + r_dcache_sc_req = false; + r_dcache_cleanup_req = false; + r_dcache_previous_unc= false; // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs - r_tgt_icache_req [num_cache] = false; - r_tgt_icache_rsp [num_cache] = false; - - r_vci_rsp_ins_error [num_cache] = false; - }// end for num_cache - - for (uint32_t num_cache=0; num_cachereset(); - r_dcache[num_cache]->reset(); - - // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI FSMs - r_dcache_miss_req [num_cache] = false; - r_dcache_unc_req [num_cache] = false; - r_dcache_sc_req [num_cache] = false; - r_dcache_cleanup_req [num_cache] = false; - r_dcache_previous_unc[num_cache] = false; - - // internal messages in DCACHE et ICACHE FSMs - r_dcache_inval_rsp [num_cache] = false; - - // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs - for (uint32_t num_cpu=0; num_cpu=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) - r_wbuf[num_cache]->printTrace(1); -#endif - } + PRINTF(" * CC_XCACHE_WRAPPER \"%s\" - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); + PRINTF(" * fsm dcache = %s\n",dcache_fsm_state_str[r_dcache_fsm]); + PRINTF(" * fsm icache = %s\n",icache_fsm_state_str[r_icache_fsm]); + PRINTF(" * fsm cmd = %s\n",cmd_fsm_state_str[r_vci_cmd_fsm]); + PRINTF(" * fsm rsp = %s\n",rsp_fsm_state_str[r_vci_rsp_fsm]); + PRINTF(" * fsm tgt = %s\n",tgt_fsm_state_str[r_vci_tgt_fsm]); + PRINTF(" * fsm cleanup = %s\n",cleanup_fsm_state_str[r_cleanup_fsm]); + PRINTF(" * ll info : %d %llx %llx\n",r_dcache_ll_valid.read(), (uint64_t)r_dcache_ll_addr.read(), (uint64_t)r_dcache_ll_data.read()); + PRINTF(" * dcache_previous_unc : %d\n",r_dcache_previous_unc.read()); // CACHE_MISS_BUF_RSP_PRINT(i); // CACHE_MISS_BUF_RSP_PRINT(d); - for (uint32_t num_cache=0; num_cache=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + { + r_wbuf.printTrace(1); + } +#endif m_cpt_total_cycles++; @@ -1245,5 +626,5 @@ if ( p_vci_tgt.cmdval.read() ) { - PRINTF(" * Request\n"); + PRINTF(" * request\n"); addr_40 address = p_vci_tgt.address.read(); @@ -1253,5 +634,5 @@ std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; std::cout << "coherence request is not a write" << std::endl; - std::cout << "address = " << std::hex << address << std::dec << std::endl; + std::cout << "oddress = " << std::hex << address << std::dec << std::endl; std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; exit(0); @@ -1263,26 +644,20 @@ std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl; std::cout << "out of segment coherence request" << std::endl; - std::cout << "address = " << std::hex << address << std::dec << std::endl; + std::cout << "oddress = " << std::hex << address << std::dec << std::endl; std::cout << "srcid = " << p_vci_tgt.srcid.read() << std::endl; exit(0); } - addr_40 tgt_addr = ((((addr_40)p_vci_tgt.be.read() & 0x3) << 32) | ((addr_40) p_vci_tgt.wdata.read())) << (addr_40)m_dcache_words_shift; - // * m_dcache_words * 4; - - addr_40 tgt_iaddr = tgt_addr; - addr_40 tgt_daddr = tgt_addr; - - PRINTF(" * srcid : %d\n",(uint32_t)p_vci_tgt.srcid.read()); - PRINTF(" * trdid : %d\n",(uint32_t)p_vci_tgt.trdid.read()); - PRINTF(" * pktid : %d\n",(uint32_t)p_vci_tgt.pktid.read()); - PRINTF(" * address (before) : %llx\n",(blob_t)tgt_iaddr); - - r_tgt_srcid = p_vci_tgt.srcid.read(); - r_tgt_trdid = p_vci_tgt.trdid.read(); - r_tgt_pktid = p_vci_tgt.pktid.read(); - // r_tgt_plen = p_vci_tgt.plen.read(); + r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | + ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4; + r_tgt_srcid = p_vci_tgt.srcid.read(); + r_tgt_trdid = p_vci_tgt.trdid.read(); + r_tgt_pktid = p_vci_tgt.pktid.read(); + // r_tgt_plen = p_vci_tgt.plen.read(); - // BROADCAST + PRINTF(" * address : %llx\n",(uint64_t)address); + PRINTF(" * address : %llx\n",(uint64_t)((((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | + ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4)); + if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type { @@ -1296,27 +671,5 @@ // r_tgt_brdcast= true; r_vci_tgt_fsm = TGT_REQ_BROADCAST; - uint32_t tgt_num_cache; - tgt_num_cache = get_num_icache(tgt_iaddr,0); // none effect (else CC_XCACHE_WRAPPER_MULTI_CACHE==1) - tgt_num_cache = get_num_dcache(tgt_daddr); - r_tgt_num_cache = tgt_num_cache; - - PRINTF(" * REQ_BROADCAST\n"); - PRINTF(" * num_cache (data) : %d\n",tgt_num_cache); - m_cpt_cc_inval_broadcast++ ; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_tgt - << "[" << m_cpt_total_cycles << "] " - << "BROADCAST " - << std::hex - << " L " << std::setw(10) << (blob_t)tgt_addr - << std::dec - << " - " << tgt_num_cache - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - } else // multi-update or multi-invalidate for data type @@ -1324,5 +677,4 @@ uint32_t cell = address - m_segment.baseAddress(); // addr_40 // r_tgt_brdcast = false; - if (cell == 0) { // invalidate data @@ -1335,25 +687,5 @@ r_tgt_update = false; r_vci_tgt_fsm = TGT_REQ_DCACHE; - uint32_t tgt_num_cache = get_num_dcache(tgt_daddr); // static partionnement - r_tgt_num_cache = tgt_num_cache; - - PRINTF(" * REQ_DCACHE\n"); - PRINTF(" * num_cache : %d\n",tgt_num_cache); - m_cpt_cc_inval_dcache++ ; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_tgt - << "[" << m_cpt_total_cycles << "] " - << "INVAL DATA " - << std::hex - << " L " << std::setw(10) << (blob_t)tgt_addr - << std::dec - << " - " << tgt_num_cache - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - } else if (cell == 4) // invalidate instruction @@ -1367,26 +699,5 @@ r_tgt_update = false; r_vci_tgt_fsm = TGT_REQ_ICACHE; - uint32_t tgt_num_cpu = p_vci_tgt.pktid.read(); - uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu); - r_tgt_num_cache = tgt_num_cache; - - PRINTF(" * REQ_ICACHE\n"); - PRINTF(" * num_cache : %d\n",tgt_num_cache); - m_cpt_cc_inval_icache++ ; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_tgt - << "[" << m_cpt_total_cycles << "] " - << "INVAL INS " - << std::hex - << " L " << std::setw(10) << (blob_t)tgt_addr - << std::dec - << " - " << tgt_num_cache - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - } else if ( (cell == 8) or (cell==12) ) // update data or instruction @@ -1402,23 +713,4 @@ m_cpt_cc_update_dcache++; r_tgt_update_data = true; - - uint32_t tgt_num_cache = get_num_dcache(tgt_daddr); - r_tgt_num_cache = tgt_num_cache; - - PRINTF(" * UPDT_WORD DATA\n"); - PRINTF(" * num_cache : %d\n",tgt_num_cache); - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_tgt - << "[" << m_cpt_total_cycles << "] " - << "UPT DATA " - << std::hex - << " L " << std::setw(10) << (blob_t)tgt_addr - << std::dec - << " - " << tgt_num_cache - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION } else @@ -1426,24 +718,4 @@ m_cpt_cc_update_icache++; r_tgt_update_data = false; - - uint32_t tgt_num_cpu = p_vci_tgt.pktid.read(); - uint32_t tgt_num_cache = get_num_icache(tgt_iaddr,tgt_num_cpu); - r_tgt_num_cache = tgt_num_cache; - - PRINTF(" * UPDT_WORD INSTRUCTION\n"); - PRINTF(" * num_cache : %d\n",tgt_num_cache); - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_tgt - << "[" << m_cpt_total_cycles << "] " - << "UPT INS " - << std::hex - << " L " << std::setw(10) << (blob_t)tgt_addr - << std::dec - << " - " << tgt_num_cache - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION } r_tgt_update = true; @@ -1452,9 +724,4 @@ } // end if address - - r_tgt_iaddr = tgt_iaddr; - r_tgt_daddr = tgt_daddr; - PRINTF(" * address (after) : i %llx, d %llx\n",(blob_t)tgt_iaddr,(blob_t)tgt_daddr); - } // end if cmdval break; @@ -1472,5 +739,5 @@ r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index #ifdef COHERENCE_DEBUG - std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_daddr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl; + std::cout << "PROC " << m_srcid_rw << " update, line : " << std::hex << r_tgt_addr.read() << " word : " << p_vci_tgt.wdata.read() << std::dec << std::endl; #endif r_vci_tgt_fsm = TGT_UPDT_DATA; @@ -1522,27 +789,9 @@ case TGT_REQ_BROADCAST: - { - bool tgt_icache_req; - -#if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) - tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); -#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) - tgt_icache_req = false; - for (uint32_t num_cache=0; num_cache dcache[%d] : %d - %d\n",(uint32_t)r_tgt_num_cache, (uint32_t)r_tgt_dcache_req[r_tgt_num_cache].read(),(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); - for (uint32_t num_cache=0; num_cache icache[%d] : %d - %d\n",(uint32_t)num_cache, (uint32_t)r_tgt_icache_req[num_cache].read(),(uint32_t)r_tgt_icache_rsp[num_cache].read()); - - bool tgt_icache_req; - -#if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) - tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); -#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) - tgt_icache_req = false; - for (uint32_t num_cache=0; num_cache icache[%d] : %d\n",(uint32_t)tgt_icache_rsp_num_cache, (uint32_t)r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read()); - - if (r_tgt_icache_rsp[tgt_icache_rsp_num_cache].read()) - break; + r_tgt_icache_rsp = false; // only reset one for respond the second time } - - tgt_icache_rsp = (tgt_icache_rsp_num_cache icache_rsp [%d] : %d\n",tgt_icache_rsp_num_cache,(uint32_t) tgt_icache_rsp); - PRINTF(" * dcache_rsp [%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t) r_tgt_dcache_rsp[r_tgt_num_cache]); - - if (tgt_icache_rsp or r_tgt_dcache_rsp[r_tgt_num_cache]) - { - // Have send one response - if ( p_vci_tgt.rspack.read()) - { - // reset dcache if activated - if (r_tgt_dcache_rsp[r_tgt_num_cache]) - r_tgt_dcache_rsp[r_tgt_num_cache] = false; - else - // reset one icache - r_tgt_icache_rsp[tgt_icache_rsp_num_cache] = false; - } - } - - // // one response - // if ( not r_tgt_icache_rsp[r_tgt_num_cache] or not r_tgt_dcache_rsp[r_tgt_num_cache] ) - // { - // if ( p_vci_tgt.rspack.read() ) - // { - // r_vci_tgt_fsm = TGT_IDLE; - // r_tgt_icache_rsp[r_tgt_num_cache] = false; - // r_tgt_dcache_rsp[r_tgt_num_cache] = false; - // } - // } - - // // if data and instruction have the inval line, need two responses - // if ( r_tgt_icache_rsp[r_tgt_num_cache] and r_tgt_dcache_rsp[r_tgt_num_cache] ) - // { - // if ( p_vci_tgt.rspack.read() ) - // { - // r_tgt_icache_rsp[r_tgt_num_cache] = false; // only reset one for respond the second time - // } - // } - - PRINTF(" * icache_rsp : %d\n",(uint32_t) r_tgt_icache_rsp[r_tgt_num_cache]); - PRINTF(" * dcache_rsp[%d] : %d\n",(uint32_t)r_tgt_num_cache,(uint32_t)r_tgt_dcache_rsp[r_tgt_num_cache].read()); - // if there is no need for a response - if (not tgt_icache_rsp and not r_tgt_dcache_rsp[r_tgt_num_cache] ) - { - r_vci_tgt_fsm = TGT_IDLE; - } - - } - break; - } + } + + // if there is no need for a response + if ( not r_tgt_icache_rsp and not r_tgt_dcache_rsp ) + { + r_vci_tgt_fsm = TGT_IDLE; + } + + } + break; //////////////////// case TGT_RSP_ICACHE: { - bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp[r_tgt_num_cache].read()) and not r_tgt_icache_req[r_tgt_num_cache].read(); - - PRINTF(" * RSP_ICACHE : transaction : %d ((%d or not %d) and not %d)\n",transaction_rsp - ,(int)p_vci_tgt.rspack.read() - ,(int)r_tgt_icache_rsp[r_tgt_num_cache].read() - ,(int)r_tgt_icache_req[r_tgt_num_cache].read() - ); - - if (transaction_rsp) + if ( (p_vci_tgt.rspack.read() or not r_tgt_icache_rsp.read()) and not r_tgt_icache_req.read() ) { r_vci_tgt_fsm = TGT_IDLE; - r_tgt_icache_rsp[r_tgt_num_cache] = false; + r_tgt_icache_rsp = false; } break; @@ -1675,163 +859,12 @@ case TGT_RSP_DCACHE: { - bool transaction_rsp = (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp[r_tgt_num_cache].read()) and not r_tgt_dcache_req[r_tgt_num_cache].read(); - - PRINTF(" * RSP_DCACHE : transaction : %d\n",transaction_rsp); - - if (transaction_rsp) + if ( (p_vci_tgt.rspack.read() or not r_tgt_dcache_rsp.read()) and not r_tgt_dcache_req.read() ) { r_vci_tgt_fsm = TGT_IDLE; - r_tgt_dcache_rsp[r_tgt_num_cache] = false; + r_tgt_dcache_rsp = false; } break; } } // end switch TGT_FSM - - ///////////////////////////////////////////////////////////////////// - // Interface between CPU and CACHE FSM - /////////////////////////////////////////////////////////////////////// - - uint32_t ireq_num_cache [m_nb_cpu]; - uint32_t dreq_num_cache [m_nb_cpu]; - bool have_sync = false; - - { - typename iss_t::InstructionRequest _ireq = ISS_IREQ_INITIALIZER; - typename iss_t::DataRequest _dreq = ISS_DREQ_INITIALIZER; - - for (uint32_t num_cache=0; num_cachegetRequests(_ireq, _dreq); - - addr_40 addr; - uint32_t num_cache; - - addr = (addr_40)_ireq.addr; - num_cache = get_num_icache(addr,num_cpu); - - bool icache_req_valid = ((not ireq[num_cache].valid and // no previous request in this cycle - (r_icache_lock [num_cache] == m_nb_cpu)) or // no previous request in previous cycle - (r_icache_lock [num_cache] == num_cpu)); // previous request in previous cycle by this cpu - - if (icache_req_valid) - { - bool valid = _ireq.valid; - - if (valid) - { - PRINTF(" * ICACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache); - ireq_num_cache [num_cpu ] = num_cache; - r_icache_lock [num_cache] = num_cpu; - } - else - { - PRINTF(" * ICACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache); - ireq_num_cache [num_cpu] = m_nb_icache; - } - - ireq_cached [num_cache] = m_cacheability_table[(vci_addr_t)_ireq.addr]; - ireq_num_cpu [num_cache] = num_cpu; - ireq [num_cache] = _ireq; - ireq [num_cache].addr = addr; - } - else - { - PRINTF(" * ICACHE : No transaction (cpu %d)\n",num_cpu); - - ireq_num_cache [num_cpu] = m_nb_icache; - } - - addr = (addr_40)_dreq.addr; - num_cache = get_num_dcache(addr); - - - bool dcache_no_lock = (r_dcache_lock [num_cache] == m_nb_cpu); - bool dcache_lock_owner = (r_dcache_lock [num_cache] == num_cpu); -#if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS - bool dcache_lock_no_owner= not dcache_no_lock and not dcache_lock_owner; - bool dcache_wait = ((r_dcache_fsm[num_cache] == DCACHE_MISS_WAIT)// or - // (r_dcache_fsm[num_cache] == DCACHE_UNC_WAIT) or - // (r_dcache_fsm[num_cache] == DCACHE_SC_WAIT) - ); - - bool dcache_req_valid = ((not dreq[num_cache].valid and // no previous request in this cycle - not have_sync and // no sync instruction - (dcache_no_lock or - (dcache_lock_no_owner and dcache_wait))) or // no previous request in previous cycle - (dcache_lock_owner and not dcache_wait)); // previous request in previous cycle by this cpu -#else - bool dcache_req_valid = ((not dreq[num_cache].valid and // no previous request in this cycle - not have_sync and // no sync instruction - dcache_no_lock) or // no previous request in previous cycle - dcache_lock_owner); // previous request in previous cycle by this cpu -#endif - // @@@@ - - - // test if already used - if (dcache_req_valid) - { - bool valid = _dreq.valid; - - if (valid) - { - PRINTF(" * DCACHE : Transaction between cpu %d and cache %d (lock)\n",num_cpu,num_cache); - dreq_num_cache [num_cpu ] = num_cache; - -#if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS - if (not dcache_lock_no_owner) -#endif - r_dcache_lock [num_cache] = num_cpu; - } - else - { - PRINTF(" * DCACHE : No Transaction between cpu %d and cache %d : invalid\n",num_cpu,num_cache); - dreq_num_cache [num_cpu] = m_nb_dcache; - } - - dreq_cached [num_cache] = m_cacheability_table[(vci_addr_t)_dreq.addr]; - dreq_num_cpu [num_cache] = num_cpu; - dreq [num_cache] = _dreq; - dreq [num_cache].addr = addr; - } - else - { - PRINTF(" * DCACHE : No transaction (cpu %d)\n",num_cpu); - - dreq_num_cache [num_cpu] = m_nb_dcache; - } - - -#if CC_XCACHE_WRAPPER_DEBUG - if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) - { - std::cout << " * Instruction Request : " << ireq_num_cache[num_cpu] << " - " << _ireq << std::endl - << " * Data Request : " << dreq_num_cache[num_cpu] << " - " << _dreq << std::endl; - } -#endif - } - - // round robin priority - r_cpu_prior = (r_cpu_prior+1)%m_nb_cpu; ///////////////////////////////////////////////////////////////////// @@ -1866,218 +899,251 @@ // flip-flop. It is reset by the ICACHE FSM. /////////////////////////////////////////////////////////////////////// - - for (uint32_t num_cache=0; num_cache=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + std::cout << " * Instruction Request : " << ireq << std::endl; +#endif + + switch(r_icache_fsm) { ///////////////// case ICACHE_IDLE: { - if ( r_tgt_icache_req[num_cache] ) { // external request - // if ( _ireq.valid ) m_cost_ins_miss_frz++; - r_icache_fsm [num_cache] = ICACHE_CC_CHECK; - r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache]; + if ( r_tgt_icache_req ) { // external request + if ( ireq.valid ) m_cost_ins_miss_frz++; + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); break; } - if ( _ireq.valid ) { - data_t icache_ins = 0; - bool icache_hit = false; - bool icache_cached = ireq_cached [num_cache]; - // uint32_t icache_num_cpu = ireq_num_cpu [num_cache]; - bool icache_cleanup_hit = r_icache_cleanup_req[num_cache] and (((addr_40)_ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line[num_cache].read()); + if ( ireq.valid ) { + data_t icache_ins = 0; + bool icache_hit = false; + bool icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr]; + bool icache_cleanup_hit = r_icache_cleanup_req and (((addr_40)ireq.addr >> (addr_40)m_icache_words_shift) == r_icache_cleanup_line.read()); // icache_hit & icache_ins evaluation if ( icache_cached ) { - icache_hit = r_icache[num_cache]->read((vci_addr_t) _ireq.addr, &icache_ins); + icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins); } else { // if uncache, again in the icache_miss_buf - icache_hit = (r_icache_buf_unc_valid[num_cache] and ((addr_40) _ireq.addr == (addr_40)r_icache_addr_save[num_cache])); - icache_ins = CACHE_MISS_BUF_RSP_DATA(i,num_cache,0); - - if (icache_hit) - CACHE_MISS_BUF_RSP_POP(i,num_cache); + icache_hit = ( r_icache_buf_unc_valid and ((addr_40) ireq.addr == (addr_40)r_icache_addr_save)); + icache_ins = CACHE_MISS_BUF_RSP_DATA(i,0); + CACHE_MISS_BUF_RSP_POP(i); } - PRINTF(" * hit %d - cached %d - cleanup_hit %d\n",num_cache, icache_hit, icache_cached, icache_cleanup_hit); - - if (icache_hit and icache_cleanup_hit) + PRINTF(" * hit %d - cached %d - cleanup_hit %d\n",icache_hit, icache_cached, icache_cleanup_hit); + + ASSERT( not (icache_hit and icache_cleanup_hit), + "Icache hit and icache_cleanup_hit"); + + if ( not icache_hit and not icache_cleanup_hit) { + m_cpt_ins_miss++; + m_cost_ins_miss_frz++; + r_icache_addr_save = (addr_40) ireq.addr; + + CACHE_MISS_BUF_REQ_INIT(i); + + if ( icache_cached ) { +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + r_icache_fsm = ICACHE_MISS_VICTIM; +#else + r_icache_fsm = ICACHE_MISS_WAIT; +#endif + r_icache_miss_req = true; + + } else { + r_icache_fsm = ICACHE_UNC_WAIT; + r_icache_unc_req = true; + } + } else { + r_icache_buf_unc_valid = false; + } + m_cpt_icache_dir_read += m_icache_ways; + m_cpt_icache_data_read += m_icache_ways; + irsp.valid = icache_hit; + irsp.instruction = icache_ins; + } + break; + } + ////////////////////// +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + case ICACHE_MISS_VICTIM: + { + if (not r_icache_cleanup_req) + { + size_t way; + size_t set; + vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read(); + vci_addr_t victim; + + r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set ); + r_icache_cleanup_line = (addr_40) victim; + r_icache_miss_way = way; + r_icache_miss_set = set; + + r_icache_fsm = ICACHE_MISS_WAIT; + } + break; + } +#endif + ////////////////////// + case ICACHE_MISS_WAIT: + { + m_cost_ins_miss_frz++; + if ( r_tgt_icache_req ) { // external request + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + bool val = CACHE_MISS_BUF_RSP_VAL(i,0); + + PRINTF(" * val : %d\n",val); + + if (val) + { + PRINTF(" * r_icache_inval_rsp : %d\n",(int) r_icache_inval_rsp ); + PRINTF(" * r_vci_rsp_ins_error : %d\n",(int) r_vci_rsp_ins_error ); + PRINTF(" * r_icache_cleanup_req : %d\n",(int) r_icache_cleanup_req); + + // if (not r_icache_inval_rsp ) + // { + // Miss read response and no invalidation + if ( r_vci_rsp_ins_error ) { + r_icache_fsm = ICACHE_ERROR; + } else { +#if not CC_XCACHE_WRAPPER_SELECT_VICTIM + if (not r_icache_cleanup_req.read()) +#endif + { + r_icache_update_addr = 0; + r_icache_fsm = ICACHE_MISS_UPDT; + } + } + // } + // else + // { + // r_icache_inval_rsp = false; + + // // Miss read response and invalidation + // if ( r_vci_rsp_ins_error ) + // r_icache_fsm = ICACHE_ERROR; + // else + // r_icache_fsm = ICACHE_CC_CLEANUP; + // } + } + break; + } + ///////////////////// + case ICACHE_UNC_WAIT: + { + m_cost_ins_miss_frz++; + if ( r_tgt_icache_req ) { // external request + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + bool ok = CACHE_MISS_BUF_RSP_VAL(i,0); + + if (ok) + { + if ( r_vci_rsp_ins_error ) { + r_icache_fsm = ICACHE_ERROR; + } else { + r_icache_fsm = ICACHE_IDLE; + r_icache_buf_unc_valid = true; + } + } + break; + } + ////////////////// + case ICACHE_ERROR: + { + if ( (addr_40)ireq.addr == (addr_40)r_icache_addr_save ) { + irsp.error = true; + irsp.valid = true; + } + r_icache_fsm = ICACHE_IDLE; + r_vci_rsp_ins_error = false; + break; + } + ////////////////////// + case ICACHE_MISS_UPDT: + { + size_t word = r_icache_update_addr.read(); + vci_addr_t addr = (vci_addr_t) r_icache_addr_save.read(); + size_t way = 0; + size_t set = 0; + + // need invalid rsp, don't select a victim + if (not r_icache_inval_rsp ) + { +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + way = r_icache_miss_way.read(); + set = r_icache_miss_set.read(); +#else + + // First word : select an victim ! + if (word == 0) { - PRINTF(" * Warning : icache hit and icache_cleanup_hit\n",num_cache); - icache_hit = false; + vci_addr_t victim; + + // r_icache_cleanup_req is false because is the transition condition to go in ICACHE_MISS_UPDT state + r_icache_cleanup_req = r_icache.victim_select(addr, &victim, &way, &set ); + r_icache.victim_update_tag(addr, way, set); + + r_icache_cleanup_line = (addr_40) victim; + r_icache_miss_way = way; + r_icache_miss_set = set; } else { - if ( not icache_hit and not icache_cleanup_hit) - { - m_cpt_ins_miss++; - m_cost_ins_miss_frz++; - - r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; - - if ( icache_cached ) - { - // to prevent deadlock, miss victim don't be block - if (not r_icache_cleanup_req[num_cache]) - { - CACHE_MISS_BUF_REQ_INIT(i,num_cache); - r_icache_fsm [num_cache] = ICACHE_MISS_VICTIM; - r_icache_miss_req[num_cache] = true; - } - else - m_cpt_icache_miss_victim_wait [num_cache] ++; - } - else - { - CACHE_MISS_BUF_REQ_INIT(i,num_cache); - r_icache_addr_save[num_cache] = (addr_40) _ireq.addr; - - r_icache_fsm [num_cache] = ICACHE_UNC_WAIT; - r_icache_unc_req[num_cache] = true; - } - } - else - { - r_icache_buf_unc_valid[num_cache] = false; - } - m_cpt_icache_dir_read += m_icache_ways; - m_cpt_icache_data_read += m_icache_ways; + way = r_icache_miss_way.read(); + set = r_icache_miss_set.read(); } - - _irsp.valid = icache_hit; - _irsp.instruction = icache_ins; - } - break; - } - ////////////////////// - case ICACHE_MISS_VICTIM: - { - // if (not r_icache_cleanup_req[num_cache]) - { - size_t way; - size_t set; - vci_addr_t addr = (vci_addr_t) r_icache_addr_save[num_cache].read(); - vci_addr_t victim; - - r_icache_cleanup_req [num_cache] = r_icache[num_cache]->victim_select(addr, &victim, &way, &set ); - r_icache_cleanup_line[num_cache] = (addr_40) victim; - r_icache_miss_way [num_cache] = way; - r_icache_miss_set [num_cache] = set; - - r_icache_fsm [num_cache] = ICACHE_MISS_WAIT; - } - break; - } - ////////////////////// - case ICACHE_MISS_WAIT: - { - m_cost_ins_miss_frz++; - if ( r_tgt_icache_req[num_cache] ) { // external request - r_icache_fsm [num_cache] = ICACHE_CC_CHECK; - r_icache_fsm_save [num_cache] = r_icache_fsm[num_cache].read(); - break; - } - - bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0); - - PRINTF(" * val : %d\n",num_cache,val); +#endif + } + bool val = CACHE_MISS_BUF_RSP_VAL(i,word); if (val) { - PRINTF(" * r_icache_inval_rsp : %d\n",num_cache,(int) r_icache_inval_rsp [num_cache]); - PRINTF(" * r_vci_rsp_ins_error : %d\n",num_cache,(int) r_vci_rsp_ins_error [num_cache]); - PRINTF(" * r_icache_cleanup_req : %d\n",num_cache,(int) r_icache_cleanup_req[num_cache]); - - // Miss read response and no invalidation - if ( r_vci_rsp_ins_error [num_cache]) { - r_icache_fsm[num_cache] = ICACHE_ERROR; - } else { - r_icache_update_addr[num_cache] = 0; - r_icache_fsm [num_cache] = ICACHE_MISS_UPDT; - } - } - break; - } - ///////////////////// - case ICACHE_UNC_WAIT: - { - m_cost_ins_miss_frz++; - if ( r_tgt_icache_req[num_cache] ) { // external request - r_icache_fsm [num_cache] = ICACHE_CC_CHECK; - r_icache_fsm_save[num_cache] = r_icache_fsm[num_cache].read(); - break; - } - - bool ok = CACHE_MISS_BUF_RSP_VAL(i,num_cache,0); - - PRINTF(" * ok : %d\n",num_cache,ok); - PRINTF(" * error : %d\n",num_cache,(uint32_t)r_vci_rsp_ins_error [num_cache]); - - if (ok) - { - if ( r_vci_rsp_ins_error [num_cache]) { - r_icache_fsm[num_cache] = ICACHE_ERROR; - } else { - r_icache_fsm [num_cache] = ICACHE_IDLE; - r_icache_buf_unc_valid[num_cache] = true; - } - } - break; - } - ////////////////// - case ICACHE_ERROR: - { - if ( (addr_40)_ireq.addr == (addr_40)r_icache_addr_save[num_cache] ) { - _irsp.error = true; - _irsp.valid = true; - } - r_icache_fsm [num_cache] = ICACHE_IDLE; - r_vci_rsp_ins_error [num_cache] = false; - break; - } - ////////////////////// - case ICACHE_MISS_UPDT: - { - size_t word = r_icache_update_addr[num_cache].read(); - vci_addr_t addr = (vci_addr_t) r_icache_addr_save [num_cache].read(); - size_t way = r_icache_miss_way[num_cache].read(); - size_t set = r_icache_miss_set[num_cache].read(); - - bool val = CACHE_MISS_BUF_RSP_VAL(i,num_cache,word); - - if (val) - { - PRINTF(" * rsp_val : %d/%d\n",num_cache,(int)r_icache_update_addr[num_cache],(int)m_icache_words); - PRINTF(" * r_icache_inval_rsp : %d\n" ,num_cache,(int)r_icache_inval_rsp[num_cache]); - PRINTF(" * ins : %x\n" ,num_cache,(int)CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); + PRINTF(" * rsp_val : %d/%d\n",(int)r_icache_update_addr,m_icache_words); + PRINTF(" * r_icache_inval_rsp : %d\n",(int)r_icache_inval_rsp); + PRINTF(" * ins : %x\n",(int)CACHE_MISS_BUF_RSP_DATA(i,word)); // m_cpt_icache_dir_write++; // m_cpt_icache_data_write++; - // if ( _ireq.valid ) m_cost_ins_miss_frz++; + // if ( ireq.valid ) m_cost_ins_miss_frz++; // if need invalid rsp, don't modify the cache, but pop the buf_rsp - if (not r_icache_inval_rsp[num_cache]) - r_icache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,num_cache,word)); - - CACHE_MISS_BUF_RSP_POP(i,num_cache); - - r_icache_update_addr[num_cache] = ++word; + if (not r_icache_inval_rsp ) + r_icache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(i,word)); + CACHE_MISS_BUF_RSP_POP(i); + + r_icache_update_addr = ++word; // if last word, finish the update if (word >= m_icache_words) { - // in all case (inval_rsp or not), update the victim tag - r_icache[num_cache]->victim_update_tag(addr, way, set); - // Last word : if previous invalid_rsp, can cleanup, else update the TAG - if (r_icache_inval_rsp[num_cache]) + if (r_icache_inval_rsp) { - r_icache_inval_rsp[num_cache] = false; - r_icache_fsm [num_cache] = ICACHE_CC_CLEANUP; + r_icache_inval_rsp = false; + r_icache_fsm = ICACHE_CC_CLEANUP; } else { - r_icache_fsm [num_cache] = ICACHE_IDLE; +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + r_icache.victim_update_tag(addr, way, set); +#endif + r_icache_fsm = ICACHE_IDLE; } } @@ -2089,12 +1155,16 @@ case ICACHE_CC_CLEANUP: { + // external cache invalidate request + if ( r_tgt_icache_req ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } // cleanup - if(not r_icache_cleanup_req[num_cache]){ - r_icache_cleanup_req [num_cache] = true; - r_icache_cleanup_line[num_cache] = r_icache_addr_save[num_cache].read() >> m_icache_words_shift; - r_icache_fsm [num_cache] = ICACHE_IDLE; - - m_cpt_icache_dir_read += m_icache_ways; - r_icache[num_cache]->inval((addr_40)r_icache_addr_save[num_cache]); + if(not r_icache_cleanup_req){ + r_icache_cleanup_req = true; + r_icache_cleanup_line = r_icache_addr_save.read() >> m_icache_words_shift; + r_icache_fsm = ICACHE_IDLE; } break; @@ -2106,29 +1176,20 @@ m_cpt_icache_dir_read += m_icache_ways; m_cpt_icache_data_read += m_icache_ways; - addr_40 ad = r_tgt_iaddr; + addr_40 ad = r_tgt_addr; data_t icache_rdata = 0; - PRINTF(" * CC_CHECK\n",num_cache); - - if((r_icache_fsm_save[num_cache] == ICACHE_MISS_WAIT) and - ((r_icache_addr_save[num_cache].read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { - PRINTF(" * have request, need inval rsp\n",num_cache); - - r_icache_inval_rsp[num_cache] = true; - r_tgt_icache_req [num_cache] = false; + if((r_icache_fsm_save == ICACHE_MISS_WAIT) and + ( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) { + r_icache_inval_rsp = true; + r_tgt_icache_req = false; if(r_tgt_update){ // Also send a cleanup and answer - PRINTF(" * send a cleanup and answer\n",num_cache); - r_tgt_icache_rsp[num_cache] = true; + r_tgt_icache_rsp = true; } else { // Also send a cleanup but don't answer - PRINTF(" * send a cleanup and but don't answer\n",num_cache); - r_tgt_icache_rsp[num_cache] = false; + r_tgt_icache_rsp = false; } - r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache]; + r_icache_fsm = r_icache_fsm_save; } else { - bool icache_hit = r_icache[num_cache]->read(ad, &icache_rdata); - - PRINTF(" * have no request, hit cache : %d\n",num_cache,icache_hit); - - if ( icache_hit and r_tgt_update) + bool icache_hit = r_icache.read(ad, &icache_rdata); + if ( icache_hit and r_tgt_update ) { #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE @@ -2137,5 +1198,5 @@ data_t rdata = 0; - r_icache[num_cache]->read(ad+word*4,&rdata); + r_icache.read(ad+word*4,&rdata); r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); @@ -2149,5 +1210,5 @@ if (word==m_icache_words) { - r_icache_fsm[num_cache] = ICACHE_CC_UPDT; + r_icache_fsm = ICACHE_CC_UPDT; #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT @@ -2161,23 +1222,23 @@ r_cache_word = word; #else //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE - r_icache_fsm[num_cache] = ICACHE_CC_UPDT; + r_icache_fsm = ICACHE_CC_UPDT; // complete the line buffer in case of update for(size_t i=0; iread(ad + i*4,&rdata); + r_icache.read(ad + i*4,&rdata); data_t mask = vci_param::be2mask(r_tgt_be[i]); r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); } #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE - } else if ( icache_hit and not r_tgt_update) { - r_icache_fsm[num_cache] = ICACHE_CC_INVAL; + } else if ( icache_hit and not r_tgt_update ) { + r_icache_fsm = ICACHE_CC_INVAL; } else { // instruction not found (can happen) - r_tgt_icache_req[num_cache] = false; + r_tgt_icache_req = false; if(r_tgt_update){ - r_tgt_icache_rsp[num_cache] = true; + r_tgt_icache_rsp = true; } else { - r_tgt_icache_rsp[num_cache] = false; + r_tgt_icache_rsp = false; } - r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache]; + r_icache_fsm = r_icache_fsm_save; } } @@ -2187,11 +1248,11 @@ case ICACHE_CC_INVAL: { - addr_40 ad = r_tgt_iaddr; - // if ( _ireq.valid ) m_cost_ins_miss_frz++; + addr_40 ad = r_tgt_addr; + if ( ireq.valid ) m_cost_ins_miss_frz++; m_cpt_icache_dir_read += m_icache_ways; - r_tgt_icache_rsp[num_cache] = true; - r_icache[num_cache]->inval(ad); - r_tgt_icache_req[num_cache] = false; - r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache]; + r_tgt_icache_rsp = true; + r_icache.inval(ad); + r_tgt_icache_req = false; + r_icache_fsm = r_icache_fsm_save; break; } @@ -2199,5 +1260,5 @@ case ICACHE_CC_UPDT: { - addr_40 ad = r_tgt_iaddr.read(); + addr_40 ad = r_tgt_addr.read(); m_cpt_icache_dir_write++; m_cpt_icache_data_write++; @@ -2207,5 +1268,5 @@ if(r_tgt_be[word]) - r_icache[num_cache]->write(ad+word*4, r_tgt_buf[word]); + r_icache.write(ad+word*4, r_tgt_buf[word]); word ++; @@ -2218,7 +1279,7 @@ if (word==m_icache_words) { - r_tgt_icache_req[num_cache] = false; - r_tgt_icache_rsp[num_cache] = true; - r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read(); + r_tgt_icache_req = false; + r_tgt_icache_rsp = true; + r_icache_fsm = r_icache_fsm_save.read(); word = 0; } @@ -2227,9 +1288,9 @@ data_t* buf = r_tgt_buf; for(size_t i=0; iwrite( ad + i*4, buf[i]); - } - r_tgt_icache_req [num_cache] = false; - r_tgt_icache_rsp [num_cache] = true; - r_icache_fsm [num_cache] = r_icache_fsm_save[num_cache].read(); + if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]); + } + r_tgt_icache_req = false; + r_tgt_icache_rsp = true; + r_icache_fsm = r_icache_fsm_save.read(); #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE @@ -2237,16 +1298,10 @@ } - }// end switch r_icache_fsm - - irsp [num_cache] = _irsp; - if (_ireq.valid and _irsp.valid) - { - PRINTF(" * Transaction between cpu %d and Icache %d (unlock)\n",r_icache_lock [num_cache].read(),num_cache); - - r_icache_lock [num_cache] = m_nb_cpu; - m_cpt_icache_access [num_cache] ++; - } - - }// end for num_cache + } // end switch r_icache_fsm + +#if CC_XCACHE_WRAPPER_DEBUG + if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + std::cout << " * Instruction Response : " << irsp << std::endl; +#endif //////////////////////////////////////////////////////////////////////:///////////// @@ -2306,36 +1361,35 @@ /////////////////////////////////////////////////////////////////////////////////// - for (uint32_t num_cache=0; num_cache=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + std::cout << " * Data Request : " << dreq << std::endl; +#endif + + switch ( r_dcache_fsm ) { ///////////////// case DCACHE_IDLE: { - if ( r_tgt_dcache_req[num_cache]) { // external request - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; + if ( r_tgt_dcache_req ) { // external request + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; break; } - if ( _dreq.valid ) { - PRINTF(" * Have dreq\n",num_cache); + if ( dreq.valid ) { + PRINTF(" * Have dreq\n"); data_t dcache_rdata = 0; - // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} - bool dcache_cached = dreq_cached [num_cache]; - uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; - bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); - bool dcache_cleanup_hit = r_dcache_cleanup_req[num_cache] and (((addr_40)_dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line[num_cache].read()); - - PRINTF(" * hit %d - cached %d - cleanup_hit %d\n",num_cache,dcache_hit, dcache_cached, dcache_cleanup_hit); + // dcache_cached and dcache_hit don't used with dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} + bool dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr]; + bool dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); + bool dcache_cleanup_hit = r_dcache_cleanup_req and (((addr_40)dreq.addr >> (addr_40)m_dcache_words_shift) == r_dcache_cleanup_line.read()); + + PRINTF(" * hit %d - cached %d - cleanup_hit %d\n",dcache_hit, dcache_cached, dcache_cleanup_hit); m_cpt_dcache_data_read += m_dcache_ways; m_cpt_dcache_dir_read += m_dcache_ways; - switch( _dreq.type ) { + switch( dreq.type ) { case iss_t::DATA_READ: case iss_t::DATA_LL: @@ -2346,21 +1400,20 @@ { // address is in the cache : return the word - r_dcache_fsm [num_cache] = DCACHE_IDLE; - - _drsp.valid = true; - _drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) + r_dcache_fsm = DCACHE_IDLE; + drsp.valid = true; + drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) // if the request is a Load Linked instruction, save request information - if(_dreq.type == iss_t::DATA_LL) + if(dreq.type == iss_t::DATA_LL) { - PRINTF(" * ll_valid = true\n",num_cache); - - r_dcache_ll_valid [num_cache][dcache_num_cpu] = true; - r_dcache_ll_data [num_cache][dcache_num_cpu] = dcache_rdata; - r_dcache_ll_addr [num_cache][dcache_num_cpu] = (vci_addr_t) _dreq.addr; + PRINTF(" * ll_valid = true\n"); + + r_dcache_ll_valid = true; + r_dcache_ll_data = dcache_rdata; + r_dcache_ll_addr = (vci_addr_t) dreq.addr; #ifdef COHERENCE_DEBUG - std::cout << "Value returned for LL at address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; - r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); - std::cout << "Value stored at this address : " << std::hex << _dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; + std::cout << "Value returned for LL at address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; + r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata); + std::cout << "Value stored at this address : " << std::hex << dreq.addr << " data : " << std::dec << dcache_rdata<< std::endl; #endif } @@ -2370,30 +1423,26 @@ if (not dcache_cleanup_hit) { + CACHE_MISS_BUF_REQ_INIT(d); // Miss : send signal at the CMD_FSM (via r_dcache_miss_req or r_dcache_unc_req) if ( dcache_cached ) { - // to prevent deadlock, miss victim don't be block - if (not r_dcache_cleanup_req[num_cache].read()) + m_cpt_data_read_miss++; + m_cost_data_miss_frz++; + r_dcache_miss_req = true; +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + r_dcache_fsm = DCACHE_MISS_VICTIM; +#else + r_dcache_fsm = DCACHE_MISS_WAIT; +#endif + + } else { + if (not r_dcache_previous_unc.read()) // strongly order to the uncached access { - CACHE_MISS_BUF_REQ_INIT(d,num_cache); - - m_cpt_data_read_miss++; - m_cost_data_miss_frz++; - r_dcache_miss_req [num_cache] = true; - r_dcache_fsm [num_cache] = DCACHE_MISS_VICTIM; - } - else - m_cpt_icache_miss_victim_wait [num_cache] ++; - } else { - if (not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access - { - CACHE_MISS_BUF_REQ_INIT(d,num_cache); - - r_dcache_previous_unc[num_cache] = true; + r_dcache_previous_unc = true; m_cpt_data_read_uncached++; m_cost_unc_read_frz++; - r_dcache_unc_req[num_cache] = true; - r_dcache_fsm [num_cache] = DCACHE_UNC_WAIT; + r_dcache_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; } } @@ -2404,7 +1453,7 @@ case iss_t::DATA_SC: { - PRINTF(" * DATA_SC - ll_valid = %d, num_cpu = %d\n",num_cache,r_dcache_ll_valid[num_cache][dcache_num_cpu].read(),dcache_num_cpu); - - if (not r_dcache_previous_unc[num_cache].read() and not dcache_cleanup_hit) // strongly order to the uncached access + PRINTF(" * DATA_SC - ll_valid = %d\n",r_dcache_ll_valid.read()); + + if (not r_dcache_previous_unc.read() and not dcache_cleanup_hit) // strongly order to the uncached access { //m_cpt_data_read_unc++; // instruction must read the memory in uncached mode @@ -2413,20 +1462,20 @@ // if previous load linked (with the same address), make a transaction // else, keep in IDLE state and return 1 (no OK) - if( r_dcache_ll_valid[num_cache][dcache_num_cpu].read() and - (r_dcache_ll_addr [num_cache][dcache_num_cpu].read() == (vci_addr_t)_dreq.addr)){ - PRINTF(" * have previous load linked\n",num_cache); + if(r_dcache_ll_valid.read() and (r_dcache_ll_addr.read() == (vci_addr_t)dreq.addr)){ + PRINTF(" * have previous load linked\n"); - r_dcache_previous_unc[num_cache] = true; - r_dcache_sc_req [num_cache] = true; - - CACHE_MISS_BUF_REQ_INIT(d,num_cache); - - r_dcache_fsm [num_cache] = DCACHE_SC_WAIT; + r_dcache_previous_unc = true; + + r_dcache_sc_req = true; + + CACHE_MISS_BUF_REQ_INIT(d); + + r_dcache_fsm = DCACHE_SC_WAIT; } else { - PRINTF(" * don't have previous load linked\n",num_cache); + PRINTF(" * don't have previous load linked\n"); - _drsp.valid = true; - _drsp.rdata = 1; // SC rsp NOK - r_dcache_ll_valid[num_cache][dcache_num_cpu] = false; + drsp.valid = true; + drsp.rdata = 1; // SC rsp NOK + r_dcache_ll_valid = false; } } @@ -2437,12 +1486,12 @@ case iss_t::XTN_WRITE: { - bool valid = false; + bool drsp_valid = false; // only DCACHE INVALIDATE and SYNC request are supported - switch (_dreq.addr>>2) + switch (dreq.addr>>2) { case iss_t::XTN_DCACHE_INVAL : { - valid = true; - r_dcache_fsm[num_cache] = DCACHE_INVAL; + drsp_valid = true; + r_dcache_fsm = DCACHE_INVAL; break; } @@ -2452,19 +1501,13 @@ // * gain : 1 cycle // * cost : can be on the critical path - - bool empty=true; - for (uint32_t i=0; iempty(); - - if (empty) + if (r_wbuf.empty()) { - valid = true; - r_dcache_fsm [num_cache] = DCACHE_IDLE; + drsp_valid = true; + r_dcache_fsm = DCACHE_IDLE; } else { - valid = false; - r_dcache_fsm [num_cache] = DCACHE_SYNC; - r_dcache_sync[num_cache] = true; + drsp_valid = false; + r_dcache_fsm = DCACHE_SYNC; } break; @@ -2473,31 +1516,23 @@ { // std::cout << "Warning in VCI_CC_XCACHE_WRAPPER " << name() << std::endl; - // std::cout << "Unsupported external access : " << (_dreq.addr>>2) << std::endl; - - r_dcache_fsm [num_cache] = DCACHE_IDLE; + // std::cout << "Unsupported external access : " << (dreq.addr>>2) << std::endl; + + r_dcache_fsm = DCACHE_IDLE; } - }//end switch (_dreq.addr>>2) - - _drsp.valid = valid; - _drsp.rdata = 0; + }//end switch (dreq.addr>>2) + + drsp.valid = drsp_valid; + drsp.rdata = 0; break; } case iss_t::DATA_WRITE: - PRINTF(" * r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); - - if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access + if (dcache_cached or not r_dcache_previous_unc.read()) // strongly order to the uncached access { - bool valid; - addr_40 addr = _dreq.addr; - set_num_dcache(addr,num_cache); - - // FIXME : - // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) - // * pour cela, virer le set_num_dcache ! - valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); - PRINTF(" * r_wbuf valid : %d\n",num_cache,valid); - - if (valid) + bool drsp_valid; + + drsp_valid = r_wbuf.write((addr_40) dreq.addr, dreq.be, dreq.wdata, dcache_cached); + + if (drsp_valid) { m_cpt_data_write++; @@ -2505,5 +1540,5 @@ if (not dcache_cached) { - r_dcache_previous_unc[num_cache] = true; + r_dcache_previous_unc = true; m_cpt_data_write_uncached++; } @@ -2511,29 +1546,26 @@ m_cpt_data_write_miss++; - if (dcache_hit) { - // update data cache - r_dcache_fsm[num_cache] = DCACHE_WRITE_UPDT; + if ( dcache_hit) { + r_dcache_fsm = DCACHE_WRITE_UPDT; } else { - // write accepted - r_dcache_fsm [num_cache] = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; } } - _drsp.valid = valid; - _drsp.rdata = 0; + drsp.valid = drsp_valid; + drsp.rdata = 0; } break; - } // end switch _dreq.type - - r_dcache_addr_save [num_cache] = (addr_40) _dreq.addr; - r_dcache_type_save [num_cache] = _dreq.type; - r_dcache_wdata_save [num_cache] = _dreq.wdata; - r_dcache_be_save [num_cache] = _dreq.be; - r_dcache_rdata_save [num_cache] = dcache_rdata; - r_dcache_cached_save [num_cache] = dcache_cached; - r_dcache_num_cpu_save[num_cache] = dcache_num_cpu; - - } else { // end if _dreq.valid - r_dcache_fsm [num_cache] = DCACHE_IDLE; + } // end switch dreq.type + + r_dcache_addr_save = (addr_40) dreq.addr; + r_dcache_type_save = dreq.type; + r_dcache_wdata_save = dreq.wdata; + r_dcache_be_save = dreq.be; + r_dcache_rdata_save = dcache_rdata; + r_dcache_cached_save = dcache_cached; + + } else { // end if dreq.valid + r_dcache_fsm = DCACHE_IDLE; } @@ -2544,188 +1576,79 @@ { m_cpt_dcache_data_write++; - data_t mask = vci_param::be2mask(r_dcache_be_save[num_cache]); - data_t wdata = (mask & r_dcache_wdata_save[num_cache]) | (~mask & r_dcache_rdata_save[num_cache]); - vci_addr_t ad = r_dcache_addr_save[num_cache].read(); - r_dcache[num_cache]->write(ad, wdata); - - int dcache_fsm_next = DCACHE_IDLE; // default - -#if CC_XCACHE_WRAPPER_STORE_AFTER_STORE - // Test if write after write - - if (_dreq.valid and (_dreq.type == iss_t::DATA_WRITE)) - { - PRINTF(" * Have dreq (Write after Write)\n",num_cache); - - data_t dcache_rdata = 0; - // dcache_cached and dcache_hit don't used with _dreq.type == {DATA_SC, XTN_READ, XTN_WRITE} - bool dcache_cached = dreq_cached [num_cache]; - uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; - bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); - - m_cpt_dcache_data_read += m_dcache_ways; - m_cpt_dcache_dir_read += m_dcache_ways; - - PRINTF(" * r_dcache_previous_unc : %d\n",num_cache,r_dcache_previous_unc[num_cache].read()); - - if (dcache_cached or not r_dcache_previous_unc[num_cache].read()) // strongly order to the uncached access - { - bool valid; - addr_40 addr = _dreq.addr; - set_num_dcache(addr,num_cache); - - // FIXME : - // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) - // * pour cela, virer le set_num_dcache ! - valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); - PRINTF(" * r_wbuf valid : %d\n",num_cache,valid); - - if (valid) - { - m_cpt_dcache_store_after_store [num_cache] ++; - - m_cpt_data_write++; - - if (not dcache_cached) - { - r_dcache_previous_unc[num_cache] = true; - m_cpt_data_write_uncached++; - } - else if (not dcache_hit) - m_cpt_data_write_miss++; - - if (dcache_hit) { - // update data cache - dcache_fsm_next = DCACHE_WRITE_UPDT; - } else { - // write accepted - dcache_fsm_next = DCACHE_IDLE; - } - } - - _drsp.valid = valid; - _drsp.rdata = 0; - } - - r_dcache_addr_save [num_cache] = (addr_40) _dreq.addr; - // r_dcache_type_save [num_cache] = _dreq.type; - r_dcache_wdata_save [num_cache] = _dreq.wdata; - r_dcache_be_save [num_cache] = _dreq.be; - r_dcache_rdata_save [num_cache] = dcache_rdata; - // r_dcache_cached_save [num_cache] = dcache_cached; - // r_dcache_num_cpu_save[num_cache] = dcache_num_cpu; - } -#endif - - r_dcache_fsm [num_cache] = dcache_fsm_next; // default + data_t mask = vci_param::be2mask(r_dcache_be_save); + data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save); + vci_addr_t ad = r_dcache_addr_save.read(); + r_dcache.write(ad, wdata); + + r_dcache_fsm = DCACHE_IDLE; break; } ////////////////////// +#if CC_XCACHE_WRAPPER_SELECT_VICTIM case DCACHE_MISS_VICTIM: { - // if (not r_dcache_cleanup_req[num_cache].read()) + if (not r_dcache_cleanup_req.read()) { size_t way; size_t set; - vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read(); + vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read(); vci_addr_t victim; - bool victim_val = r_dcache[num_cache]->victim_select(addr, &victim, &way, &set ); - r_dcache_cleanup_req [num_cache] = victim_val; - r_dcache_cleanup_line [num_cache] = (addr_40) victim; - r_dcache_miss_way [num_cache] = way; - r_dcache_miss_set [num_cache] = set; - - PRINTF(" * MISS_VICTIM : Victim %d - %llx (way %d, set %d)\n",num_cache,victim_val, (blob_t)victim, (int)way, (int)set); - - r_dcache_fsm [num_cache] = DCACHE_MISS_WAIT; + r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); + r_dcache_cleanup_line = (addr_40) victim; + r_dcache_miss_way = way; + r_dcache_miss_set = set; + + r_dcache_fsm = DCACHE_MISS_WAIT; } break; } +#endif ////////////////////// case DCACHE_MISS_WAIT: { -#if CC_XCACHE_WRAPPER_MULTI_CACHE_HIT_AFTER_MISS - data_t dcache_rdata = 0; - bool dcache_hit = r_dcache[num_cache]->read((vci_addr_t) _dreq.addr, &dcache_rdata); - // bool dcache_cached = dreq_cached [num_cache]; - // uint32_t dcache_num_cpu = dreq_num_cpu [num_cache]; - - m_cpt_dcache_data_read += m_dcache_ways; - m_cpt_dcache_dir_read += m_dcache_ways; - - if (_dreq.valid) - switch (_dreq.type) - { - case iss_t::DATA_READ : // accept only hit dcache load - { - m_cpt_data_read++; // new dcache read - - if (dcache_hit) // no special test for uncached read, because it's always miss - { - m_cpt_dcache_hit_after_miss_read [num_cache] ++; - - // address is in the cache : return the word - _drsp.valid = true; - _drsp.rdata = dcache_rdata; // return read data (cf dcache_hit) - } - break; - } - // case iss_t::DATA_WRITE : // accept only cached write and miss in dcache (else need update dcache) - // { - // if (dcache_cached and not dcache_hit) - // { - // bool valid; - // addr_40 addr = _dreq.addr; - // set_num_dcache(addr,num_cache); - - // // FIXME : - // // * dans le wbuf, ne pas mettre l'adresse au complet (economie de surface) - // // * pour cela, virer le set_num_dcache ! - // valid = r_wbuf[num_cache]->write(addr, _dreq.be, _dreq.wdata, dcache_cached, dcache_num_cpu); - // PRINTF(" * r_wbuf valid : %d\n",num_cache,valid); - - // if (valid) - // { - // m_cpt_dcache_hit_after_miss_write [num_cache] ++; - - // m_cpt_data_write++; - // m_cpt_data_write_miss++; - // } - - // _drsp.valid = valid; - // _drsp.rdata = 0; - // } - // break; - // } - default : - { - break; - } - } -#endif - - // if ( _dreq.valid ) m_cost_data_miss_frz++; - if ( r_tgt_dcache_req[num_cache].read() ) { // external request - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save [num_cache] = r_dcache_fsm[num_cache]; + + if ( dreq.valid ) m_cost_data_miss_frz++; + if ( r_tgt_dcache_req.read() ) { // external request + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; break; } - bool val = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0); + bool val = CACHE_MISS_BUF_RSP_VAL(d,0); if (val) { + // if (not r_dcache_inval_rsp ) + // { + // Miss read response and no invalidation - if (r_vci_rsp_data_error[num_cache]) + if ( r_vci_rsp_data_error ) { - r_dcache_fsm [num_cache] = DCACHE_ERROR; + r_dcache_fsm = DCACHE_ERROR; } else { - r_dcache_update_addr[num_cache] = 0; - r_dcache_fsm [num_cache] = DCACHE_MISS_UPDT; +#if not CC_XCACHE_WRAPPER_SELECT_VICTIM + if (not r_dcache_cleanup_req.read()) +#endif + { + r_dcache_update_addr = 0; + r_dcache_fsm = DCACHE_MISS_UPDT; + } } + // } + // else + // { + // r_dcache_inval_rsp = false; + + // // Miss read response and invalidation + // if ( r_vci_rsp_data_error ) { + // r_dcache_fsm = DCACHE_ERROR; + // } else { + // r_dcache_fsm = DCACHE_CC_CLEANUP; + // } + // } } break; @@ -2734,43 +1657,68 @@ case DCACHE_MISS_UPDT: { - size_t word = r_dcache_update_addr[num_cache].read(); - vci_addr_t addr = (vci_addr_t) r_dcache_addr_save[num_cache].read(); - size_t way = r_dcache_miss_way[num_cache].read(); - size_t set = r_dcache_miss_set[num_cache].read(); + size_t word = r_dcache_update_addr.read(); + vci_addr_t addr = (vci_addr_t) r_dcache_addr_save.read(); + size_t way = 0; + size_t set = 0; - PRINTF(" * MISS_UPDT : Victim way %d, set %d\n",num_cache, (int)way, (int)set); - - if (CACHE_MISS_BUF_RSP_VAL(d,num_cache,word)) + // need invalid rsp, don't select a victim + if (not r_dcache_inval_rsp ) + { +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + way = r_dcache_miss_way.read(); + set = r_dcache_miss_set.read(); +#else + // First word : select an victim ! + if (word == 0) + { + vci_addr_t victim; + + // r_dcache_cleanup_req is false (condition to enter in DCACHE_MISS_UPDT + r_dcache_cleanup_req = r_dcache.victim_select(addr, &victim, &way, &set ); + r_dcache.victim_update_tag(addr, way, set); + r_dcache_cleanup_line = (addr_40) victim; + + r_dcache_miss_way = way; + r_dcache_miss_set = set; + } + else + { + way = r_dcache_miss_way.read(); + set = r_dcache_miss_set.read(); + } +#endif + } + + bool val = CACHE_MISS_BUF_RSP_VAL(d,word); + if (val) { // m_cpt_dcache_dir_write++; - // if ( _dreq.valid ) m_cost_data_miss_frz++; + // if ( ireq.valid ) m_cost_data_miss_frz++; // if need invalid rsp, don't modify the cache, but pop the buf_rsp - // (power save) - if (not r_dcache_inval_rsp[num_cache]) + if (not r_dcache_inval_rsp ) { - r_dcache[num_cache]->write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,num_cache,word)); + r_dcache.write(way, set, word, CACHE_MISS_BUF_RSP_DATA(d,word)); m_cpt_dcache_data_write++; } - CACHE_MISS_BUF_RSP_POP(d,num_cache); - r_dcache_update_addr[num_cache] = ++word; + CACHE_MISS_BUF_RSP_POP(d); + r_dcache_update_addr = ++word; // if last word, finish the update if (word >= m_dcache_words) { - // in all case (inval_rsp or not), update the victim tag - // because victim is already cleanup - r_dcache[num_cache]->victim_update_tag(addr, way, set); - // Last word : if previous invalid_rsp, can cleanup, else update the TAG - if (r_dcache_inval_rsp[num_cache]) + if (r_dcache_inval_rsp) { - r_dcache_inval_rsp[num_cache] = false; - r_dcache_fsm [num_cache] = DCACHE_CC_CLEANUP; + r_dcache_inval_rsp = false; + r_dcache_fsm = DCACHE_CC_CLEANUP; } else { - r_dcache_fsm [num_cache] = DCACHE_IDLE; +#if CC_XCACHE_WRAPPER_SELECT_VICTIM + r_dcache.victim_update_tag(addr, way, set); +#endif + r_dcache_fsm = DCACHE_IDLE; } } @@ -2782,31 +1730,30 @@ case DCACHE_UNC_WAIT: { - // if ( _dreq.valid ) m_cost_unc_read_frz++; - if ( r_tgt_dcache_req[num_cache] ) { // external request - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; + if ( dreq.valid ) m_cost_unc_read_frz++; + if ( r_tgt_dcache_req ) { // external request + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; break; } - bool ok = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0); + bool ok = CACHE_MISS_BUF_RSP_VAL(d,0); if (ok) { - if (r_vci_rsp_data_error[num_cache]) { - r_dcache_fsm[num_cache] = DCACHE_ERROR; + if ( r_vci_rsp_data_error ) { + r_dcache_fsm = DCACHE_ERROR; } else { - data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0); - CACHE_MISS_BUF_RSP_POP(d,num_cache); - - if(_dreq.type == iss_t::DATA_LL){ - PRINTF(" * ll_valid = true\n",num_cache); - - r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]] = true; - r_dcache_ll_data [num_cache][r_dcache_num_cpu_save[num_cache]] = rdata; - r_dcache_ll_addr [num_cache][r_dcache_num_cpu_save[num_cache]] = (vci_addr_t) _dreq.addr; + data_t rdata = CACHE_MISS_BUF_RSP_DATA(d,0); + CACHE_MISS_BUF_RSP_POP(d); + + if(dreq.type == iss_t::DATA_LL){ + PRINTF(" * ll_valid = true\n"); + + r_dcache_ll_valid = true; + r_dcache_ll_data = rdata; + r_dcache_ll_addr = (vci_addr_t) dreq.addr; } - r_dcache_fsm [num_cache] = DCACHE_IDLE; - - _drsp.valid = true; - _drsp.rdata = rdata; + r_dcache_fsm = DCACHE_IDLE; + drsp.valid = true; + drsp.rdata = rdata; } } @@ -2816,23 +1763,22 @@ case DCACHE_SC_WAIT: { - // if ( _dreq.valid ) m_cost_unc_read_frz++; - if ( r_tgt_dcache_req[num_cache] ) { // external request - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache]; + if ( dreq.valid ) m_cost_unc_read_frz++; + if ( r_tgt_dcache_req ) { // external request + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; break; } - bool ok = CACHE_MISS_BUF_RSP_VAL(d,num_cache,0); + bool ok = CACHE_MISS_BUF_RSP_VAL(d,0); if (ok) { - if (r_vci_rsp_data_error[num_cache]) { - r_dcache_fsm [num_cache] = DCACHE_ERROR; + if ( r_vci_rsp_data_error ) { + r_dcache_fsm = DCACHE_ERROR; } else { - r_dcache_fsm [num_cache] = DCACHE_IDLE; - - _drsp.valid = true; - _drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,num_cache,0); - CACHE_MISS_BUF_RSP_POP(d,num_cache); - r_dcache_ll_valid [num_cache][r_dcache_num_cpu_save[num_cache]] = false; + r_dcache_fsm = DCACHE_IDLE; + drsp.valid = true; + drsp.rdata = CACHE_MISS_BUF_RSP_DATA(d,0); + CACHE_MISS_BUF_RSP_POP(d); + r_dcache_ll_valid = false; } } @@ -2843,9 +1789,8 @@ case DCACHE_ERROR: { - r_dcache_fsm [num_cache] = DCACHE_IDLE; - - r_vci_rsp_data_error[num_cache] = false; - _drsp.error = true; - _drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + r_vci_rsp_data_error = false; + drsp.error = true; + drsp.valid = true; break; } @@ -2853,16 +1798,16 @@ case DCACHE_INVAL: { - if ( r_tgt_dcache_req[num_cache].read() ) { // external request - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save [num_cache] = r_dcache_fsm [num_cache]; + if ( r_tgt_dcache_req.read() ) { // external request + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; break; } - if( not r_dcache_cleanup_req [num_cache].read() ){ + if( not r_dcache_cleanup_req.read() ){ m_cpt_dcache_dir_read += m_dcache_ways; - vci_addr_t ad = r_dcache_addr_save [num_cache].read(); - r_dcache_cleanup_req [num_cache] = r_dcache[num_cache]->inval(ad); - r_dcache_cleanup_line [num_cache] = r_dcache_addr_save [num_cache].read() >> m_dcache_words_shift; - - r_dcache_fsm [num_cache] = DCACHE_IDLE; + vci_addr_t ad = r_dcache_addr_save.read(); + r_dcache_cleanup_req = r_dcache.inval(ad); + r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; + + r_dcache_fsm = DCACHE_IDLE; } break; @@ -2870,20 +1815,15 @@ case DCACHE_SYNC : { - if ( r_tgt_dcache_req[num_cache] ) { // external request - r_dcache_fsm [num_cache] = DCACHE_CC_CHECK; - r_dcache_fsm_save[num_cache] = r_dcache_fsm[num_cache]; + if ( r_tgt_dcache_req ) { // external request + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; break; } - bool empty=true; - for (uint32_t i=0; iempty(); - - if (empty) - { - _drsp.valid = true; // end, can accept the sync request - r_dcache_fsm [num_cache] = DCACHE_IDLE; - r_dcache_sync[num_cache] = false; - } + if (r_wbuf.empty()) + { + drsp.valid = true; // end, can accept the sync request + r_dcache_fsm = DCACHE_IDLE; + } break; } @@ -2891,28 +1831,19 @@ case DCACHE_CC_CHECK: // read directory in case of invalidate or update request { - addr_40 ad = r_tgt_daddr; + addr_40 ad = r_tgt_addr; data_t dcache_rdata = 0; - PRINTF(" * CC_CHECK\n",num_cache); - - // - if((r_dcache_fsm_save[num_cache] == DCACHE_MISS_WAIT) and - ((r_dcache_addr_save[num_cache].read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { - PRINTF(" * have request, need inval rsp\n",num_cache); - - r_dcache_inval_rsp[num_cache] = true; - r_tgt_dcache_req [num_cache] = false; + if((r_dcache_fsm_save == DCACHE_MISS_WAIT) and + ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) { + r_dcache_inval_rsp = true; + r_tgt_dcache_req = false; if(r_tgt_update){ // Also send a cleanup and answer - PRINTF(" * send a cleanup and answer\n",num_cache); - r_tgt_dcache_rsp[num_cache] = true; + r_tgt_dcache_rsp = true; } else { // Also send a cleanup but don't answer - PRINTF(" * send a cleanup and but don't answer\n",num_cache); - r_tgt_dcache_rsp[num_cache] = false; + r_tgt_dcache_rsp = false; } - r_dcache_fsm[num_cache] = r_dcache_fsm_save[num_cache]; + r_dcache_fsm = r_dcache_fsm_save; } else { - bool dcache_hit = r_dcache[num_cache]->read(ad, &dcache_rdata); - - PRINTF(" * have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update); + bool dcache_hit = r_dcache.read(ad, &dcache_rdata); m_cpt_dcache_data_read += m_dcache_ways; @@ -2929,5 +1860,5 @@ data_t rdata = 0; - r_dcache[num_cache]->read(ad+word*4,&rdata); + r_dcache.read(ad+word*4,&rdata); r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata); @@ -2942,5 +1873,5 @@ if (word==m_dcache_words) { - r_dcache_fsm[num_cache] = DCACHE_CC_UPDT; + r_dcache_fsm = DCACHE_CC_UPDT; #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT for (word=0; wordread(ad + i*4,&rdata); + r_dcache.read(ad + i*4,&rdata); data_t mask = vci_param::be2mask(r_tgt_be[i]); r_tgt_buf[i] = (mask & r_tgt_buf[i]) | (~mask & rdata); } - r_dcache_fsm[num_cache] = DCACHE_CC_UPDT; + r_dcache_fsm = DCACHE_CC_UPDT; #endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE } else if ( dcache_hit and not r_tgt_update ) { - r_dcache_fsm[num_cache] = DCACHE_CC_INVAL; + r_dcache_fsm = DCACHE_CC_INVAL; } else { if(r_tgt_update){ - r_tgt_dcache_rsp[num_cache] = true; + r_tgt_dcache_rsp = true; } else { - r_tgt_dcache_rsp[num_cache] = false; + r_tgt_dcache_rsp = false; } - r_tgt_dcache_req[num_cache] = false; - r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; + r_tgt_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_save; } } @@ -2979,5 +1910,5 @@ case DCACHE_CC_UPDT: // update directory and data cache { - addr_40 ad = r_tgt_daddr; + addr_40 ad = r_tgt_addr; m_cpt_dcache_dir_write++; @@ -2992,9 +1923,9 @@ if(r_tgt_be[word]) - r_dcache[num_cache]->write(ad+word*4, r_tgt_buf[word]); + r_dcache.write(ad+word*4, r_tgt_buf[word]); # ifdef COHERENCE_DEBUG std::cout << " address " << std::hex << ad+word*4 << " data " << std::dec << r_tgt_buf[word] << std::endl; data_t rdata = 0xAAAAAAAA; - r_dcache[num_cache]->read(ad+word*4,&rdata); + r_dcache.read(ad+word*4,&rdata); std::cout << "data written " << rdata << std::endl; # endif @@ -3009,7 +1940,7 @@ if (word==m_dcache_words) { - r_tgt_dcache_req[num_cache] = false; - r_tgt_dcache_rsp[num_cache] = true; - r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; + r_tgt_dcache_req = false; + r_tgt_dcache_rsp = true; + r_dcache_fsm = r_dcache_fsm_save; word = 0; } @@ -3019,16 +1950,16 @@ for(size_t i=0; iwrite( ad + i*4, buf[i]); + r_dcache.write( ad + i*4, buf[i]); # ifdef COHERENCE_DEBUG std::cout << " address " << std::hex << ad+i*4 << " data " << std::dec << buf[i] << std::endl; data_t rdata = 0xAAAAAAAA; - r_dcache[num_cache]->read(ad + i*4,&rdata); + r_dcache.read(ad + i*4,&rdata); std::cout << "data written " << rdata << std::endl; # endif //CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE } } - r_tgt_dcache_req[num_cache] = false; - r_tgt_dcache_rsp[num_cache] = true; - r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; + r_tgt_dcache_req = false; + r_tgt_dcache_rsp = true; + r_dcache_fsm = r_dcache_fsm_save; #endif break; @@ -3037,9 +1968,9 @@ case DCACHE_CC_INVAL: // invalidate a cache line { - addr_40 ad = r_tgt_daddr; - r_tgt_dcache_rsp[num_cache] = true; - r_dcache [num_cache]->inval(ad); - r_tgt_dcache_req[num_cache] = false; - r_dcache_fsm [num_cache] = r_dcache_fsm_save[num_cache]; + addr_40 ad = r_tgt_addr; + r_tgt_dcache_rsp = true; + r_dcache.inval(ad); + r_tgt_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_save; break; } @@ -3047,12 +1978,16 @@ case DCACHE_CC_CLEANUP: { + // external cache invalidate request + if ( r_tgt_dcache_req ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_save = r_dcache_fsm; + break; + } // cleanup - if(not r_dcache_cleanup_req[num_cache]){ - r_dcache_cleanup_req [num_cache] = true; - r_dcache_cleanup_line [num_cache] = r_dcache_addr_save[num_cache].read() >> m_dcache_words_shift; - r_dcache_fsm [num_cache] = DCACHE_IDLE; - - m_cpt_dcache_dir_read += m_dcache_ways; - r_dcache[num_cache]->inval((addr_40)r_dcache_addr_save[num_cache]); + if(not r_dcache_cleanup_req){ + r_dcache_cleanup_req = true; + r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_dcache_words_shift; + r_dcache_fsm = DCACHE_IDLE; } break; @@ -3064,135 +1999,94 @@ // The update() method must be called at each cycle to update the internal state. // All pending write requests must be locked in case of SYNC - - // bool have_sync=(r_dcache_fsm[num_cache] == DCACHE_SYNC); + bool wbuf_flush=(r_dcache_fsm == DCACHE_SYNC); #if (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==1) - r_wbuf[num_cache]->update_multi_scan (have_sync); + r_wbuf.update_multi_scan (wbuf_flush); #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==2) - r_wbuf[num_cache]->update_round_robin_scan(have_sync); + r_wbuf.update_round_robin_scan(wbuf_flush); #elif (CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME==3) - r_wbuf[num_cache]->update_one_scan (have_sync); + r_wbuf.update_one_scan (wbuf_flush); #else - r_wbuf[num_cache]->update (have_sync); -#endif - - drsp [num_cache] = _drsp; - if (_dreq.valid and _drsp.valid) + r_wbuf.update (wbuf_flush); +#endif + +#if CC_XCACHE_WRAPPER_DEBUG + if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + std::cout << " * Data Response : " << drsp << std::endl; +#endif + + /////////// execute one iss cycle ///////////////////////////////////////////// { - PRINTF(" * Transaction between cpu %d and Dcache %d (unlock)\n",r_dcache_lock [num_cache].read(),num_cache); - - r_dcache_lock [num_cache] = m_nb_cpu; - m_cpt_dcache_access [num_cache] ++; + uint32_t it = 0; + for (size_t i=0; i<(size_t)iss_t::n_irq; i++) + if(p_irq[i].read()) it |= (1<=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN) + m_cpt_frz_cycles++; +#if CC_XCACHE_WRAPPER_STOP_SIMULATION + m_stop_simulation_nb_frz_cycles ++; + + if (m_stop_simulation and (m_stop_simulation_nb_frz_cycles >= m_stop_simulation_nb_frz_cycles_max)) { - - std::cout << " * CPU : " << num_cpu << std::endl - << " * Instruction Cache : " << ireq_num_cache[num_cpu] << ", valid : " << (ireq_num_cache[num_cpu]= m_stop_simulation_nb_frz_cycles_max)) - { - std::cout << std::dec << "CC_XCACHE_WRAPPER \"" << name() << "\" (" << num_cpu << ") : cycle " << m_cpt_total_cycles << ", the cpu is frozen since " << m_stop_simulation_nb_frz_cycles [num_cpu]<< " cycles." << std::endl; - ASSERT(false,"CPU : anormal activity"); // exit - } - } - else - { - m_stop_simulation_nb_frz_cycles [num_cpu] = 0; // reinit counter + } + else + { + m_stop_simulation_nb_frz_cycles = 0; // reinit counter #endif //CC_XCACHE_WRAPPER_STOP_SIMULATION - } - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - if (_ireq.valid and _irsp.valid) - { - log_transaction_file_icache [num_cpu] - << "[" << m_cpt_total_cycles << "]" - << std::hex - << " @ " << std::setw(8) << (uint32_t)_ireq.addr - << " (" << std::setw(8) << (uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu]) - << " - L " << std::setw(8) <<((uint32_t)set_num_icache_only(_ireq.addr,ireq_num_cache[num_cpu])&m_icache_yzmask) << ")" - << " I " << std::setw(8) << (uint32_t)_irsp.instruction - << " error " << (uint32_t)_irsp.error - << std::dec - << std::endl; - } - - if (_dreq.valid and _drsp.valid) - { - log_transaction_file_dcache [num_cpu] - << "[" << m_cpt_total_cycles << "]" - << std::hex - << " @ " << std::setw(8) << (uint32_t)_dreq.addr - << " (" << std::setw(8) << (uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu]) - << " - L " << std::setw(8) <<((uint32_t)set_num_dcache_only(_dreq.addr,dreq_num_cache[num_cpu])&m_dcache_yzmask) << ")" - << " be " << std::setw(1) << (uint32_t)_dreq.be - << " W " << std::setw(8) << (uint32_t)_dreq.wdata - << " R " << std::setw(8) << (uint32_t)_drsp.rdata - << " error " << (uint32_t)_drsp.error - << std::dec - << " " << type_str(_dreq.type); - - if ((_dreq.type == iss_t::XTN_READ) or - (_dreq.type == iss_t::XTN_WRITE)) - //log_transaction_file_dcache [num_cpu] << xtn_str(_dreq.addr>>2); - switch (_dreq.addr>>2) - { - case iss_t::XTN_DCACHE_INVAL : log_transaction_file_dcache [num_cpu]<< " INVAL"; break; - case iss_t::XTN_SYNC : log_transaction_file_dcache [num_cpu]<< " SYNC"; break; - default : log_transaction_file_dcache [num_cpu]<< " invalid"; break; - } - - log_transaction_file_dcache [num_cpu]<< std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - - { - uint32_t it = 0; - for (size_t i=0; i<(size_t)iss_t::n_irq; i++) - if(p_irq[num_cpu][i].read()) it |= (1<executeNCycles(1, _irsp, _drsp, it); - } - }//end num_cpu + } + + +#if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION + if (dreq.valid and drsp.valid) + { + log_dcache_transaction_file + << "[" << m_cpt_total_cycles << "]" + << std::hex + << " @ " << std::setw(8) << (uint32_t)dreq.addr + << " be " << std::setw(1) << (uint32_t)dreq.be + << " W " << std::setw(8) << (uint32_t)dreq.wdata + << " R " << std::setw(8) << (uint32_t)drsp.rdata + << " error " << (uint32_t)drsp.error + << std::dec + << " " << type_str(dreq.type); + + if ((dreq.type == iss_t::XTN_READ) or + (dreq.type == iss_t::XTN_WRITE)) + //log_dcache_transaction_file << xtn_str(dreq.addr>>2); + switch (dreq.addr>>2) + { + case iss_t::XTN_DCACHE_INVAL : log_dcache_transaction_file << " INVAL"; break; + case iss_t::XTN_SYNC : log_dcache_transaction_file << " SYNC"; break; + default : log_dcache_transaction_file << " invalid"; break; + } + + log_dcache_transaction_file << std::endl; + + // printf("[%d] @ %.8x be %.1x W %.8x R %.8x error %d - %s" + // ,(uint32_t)m_cpt_total_cycles + // ,(uint32_t)dreq.addr + // ,(uint32_t)dreq.be + // ,(uint32_t)dreq.wdata + // ,(uint32_t)drsp.rdata + // ,(uint32_t)drsp.error + // ,type_str(dreq.type)); + // if ((dreq.type == iss_t::XTN_READ) or + // (dreq.type == iss_t::XTN_WRITE)) + // // printf(" %s",xtn_str(dreq.addr>>2)); + // switch (dreq.addr>>2) + // { + // case iss_t::XTN_DCACHE_INVAL : printf(" INVAL"); break; + // case iss_t::XTN_SYNC : printf(" SYNC"); break; + // default : printf(" invalid"); break; + // } + // printf("\n"); + } +#endif //CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION //////////////////////////////////////////////////////////////////////////// @@ -3219,95 +2113,30 @@ case CLEANUP_IDLE: - { - uint32_t num_cache = 0; - bool cleanup_dcache_req = false; - bool cleanup_icache_req = false; - - // dcache is prior - for (uint32_t i=0; i dcache_cleanup_req : [%d] %d\n",i,(int)r_dcache_cleanup_req[i]); - cleanup_dcache_req |= r_dcache_cleanup_req[i]; - if (cleanup_dcache_req) - { - PRINTF(" * ... find\n"); - num_cache=i; - break; - } - } - - if (not cleanup_dcache_req) - for (uint32_t i=0; i icache_cleanup_req : [%d] %d\n",i,(int)r_icache_cleanup_req[i]); - - cleanup_icache_req |= r_icache_cleanup_req[i]; - if (cleanup_icache_req) - { - PRINTF(" * ... find\n"); - num_cache=i; - break; - } - } - - PRINTF(" * cleanup_icache_req : %d\n",cleanup_icache_req); - PRINTF(" * cleanup_dcache_req : %d\n",cleanup_dcache_req); - PRINTF(" * num_cache : %d\n",num_cache); - - if (cleanup_icache_req or cleanup_dcache_req) - { - r_cleanup_fsm = CLEANUP_REQ; - r_cleanup_icache = cleanup_icache_req; - r_cleanup_num_cache = num_cache; - - PRINTF(" * address : %llx\n",((cleanup_icache_req)?((blob_t)set_num_icache_only(r_icache_cleanup_line[num_cache].read()< rerror : %d (%d)\n",(uint32_t)p_vci_ini_c.rerror.read(),0x2 & ( (1 << vci_param::E) - 1)); - PRINTF(" * rpktid : %d, r_cleanup_num_cache : %d\n",(uint32_t)p_vci_ini_c.rpktid.read(), (uint32_t)r_cleanup_num_cache); ASSERT(p_vci_ini_c.reop and (p_vci_ini_c.rtrdid.read() == TYPE_DATA_CLEANUP), - "illegal response packet received for a cleanup transaction"); + "illegal response packet received for a cleanup transaction"); ASSERT(p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL, "error signaled in a cleanup response" ); - ASSERT(p_vci_ini_c.rpktid.read() == (sc_dt::sc_uint)r_cleanup_num_cache, - "invalid pktid in a cleanup response"); - + r_cleanup_fsm = CLEANUP_IDLE; - r_dcache_cleanup_req[r_cleanup_num_cache] = false; - // m_cpt_cc_cleanup_data++; + r_dcache_cleanup_req = false; + // m_cpt_cc_cleanup_data++; TODO } break; } - case CLEANUP_RSP_ICACHE: + case CLEANUP_ICACHE: { if ( p_vci_ini_c.rspval ) @@ -3321,6 +2150,6 @@ r_cleanup_fsm = CLEANUP_IDLE; - r_icache_cleanup_req[r_cleanup_num_cache] = false; - // m_cpt_cc_cleanup_ins++; + r_icache_cleanup_req = false; + // m_cpt_cc_cleanup_ins++; TODO } break; @@ -3366,10 +2195,7 @@ // if (r_vci_rsp_fsm != RSP_IDLE) break; - size_t wbuf_min = 0; - size_t wbuf_max = 0; -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - addr_40 wbuf_addr = 0; - size_t wbuf_index = 0; -#endif + size_t min; + size_t max; + r_vci_cmd_cpt = 0; @@ -3378,253 +2204,74 @@ // multi_write_buffer access is conditionnal with dcache_miss_req and icache_miss_req - bool dcache_miss_req = false; - bool icache_miss_req = false; - uint32_t dcache_miss_num_cache = 0; - uint32_t icache_miss_num_cache = 0; - addr_40 addr = 0; - - { - for (; dcache_miss_num_cache icache_miss_req (before) : %d\n",icache_miss_req); - PRINTF(" * dcache_miss_req (before) : %d\n",dcache_miss_req); - #if (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==1) - // 1) one access with static priority (dcache prior) - icache_miss_req &= not dcache_miss_req; + // 1) two access authorized + bool dcache_miss_req = r_dcache_miss_req; + bool icache_miss_req = r_icache_miss_req; #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==2) - // 2) one access with static priority (icache prior) - dcache_miss_req &= not icache_miss_req; + // 2) one access with static priority (dcache prior) + bool dcache_miss_req = r_dcache_miss_req; // dcache prior + bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==3) - // 3) one access with round robin priority - dcache_miss_req = ((dcache_miss_req and not icache_miss_req) or // only dcache - (dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior - icache_miss_req &= not dcache_miss_req; -// #elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) -// // 4) two access authorized -// dcache_miss_req = r_dcache_miss_req[cache_miss_num_cache]; -// icache_miss_req = r_icache_miss_req[cache_miss_num_cache]; + // 3) one access with static priority (icache prior) + bool icache_miss_req = r_icache_miss_req; + bool dcache_miss_req = not icache_miss_req and r_dcache_miss_req; // dcache prior +#elif (CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY==4) + // 4) one access with round robin priority + bool dcache_miss_req = ((r_dcache_miss_req and not r_icache_miss_req) or // only dcache + (r_dcache_miss_req and r_vci_cmd_dcache_prior)); // dcache prior + bool icache_miss_req = not dcache_miss_req and r_icache_miss_req; #else #error "Invalid value to CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY" #endif - - PRINTF(" * icache_miss_req (after ) : %d\n",icache_miss_req); - PRINTF(" * dcache_miss_req (after ) : %d\n",dcache_miss_req); - - PRINTF(" * icache_miss_num_cache : %d\n",icache_miss_num_cache); - PRINTF(" * dcache_miss_num_cache : %d\n",dcache_miss_num_cache); - - if (icache_miss_req or dcache_miss_req) - { - addr = (icache_miss_req)?r_icache_addr_save[icache_miss_num_cache].read():r_dcache_addr_save[dcache_miss_num_cache].read(); - - PRINTF(" * addr : %llx\n",(blob_t)addr); - - if (icache_miss_req) - { - // FIXME : - // si wbuf contient des addresses partionné, set_num_icache puis get_num_dcache - // dcache_miss_num_cache = icache_miss_num_cache; - set_num_icache(addr,icache_miss_num_cache); - // get_num_dcache(addr,dcache_miss_num_cache); - } - else - set_num_dcache(addr,dcache_miss_num_cache); - - PRINTF(" * addr : %llx\n",(blob_t)addr); - } - } - - uint32_t dcache_unc_num_cache = 0; - for (; dcache_unc_num_cachedebug_rok(&wbuf_min, &wbuf_max, &wbuf_addr, &wbuf_index)) - break; -#else - if ( r_wbuf[dcache_write_num_cache]->rok(&wbuf_min, &wbuf_max)) - break; -#endif - } - // 1 - Data Read - if (dcache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr)) + if (dcache_miss_req and r_wbuf.miss(r_dcache_addr_save)) { - r_vci_cmd_fsm = CMD_DATA_MISS; - r_vci_cmd_num_cache = dcache_miss_num_cache; - r_dcache_miss_req[dcache_miss_num_cache] = false; + r_vci_cmd_fsm = CMD_DATA_MISS; + r_dcache_miss_req = false; m_cpt_dmiss_transaction++; - - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "CMD DATA MISS " - << "(" << dcache_miss_num_cache << ") " - << std::hex - << " @ " << std::setw(10) << (blob_t)addr - << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" - << std::dec - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - } // 2 - Data Read Uncachable - else if (dcache_unc_num_cache < m_nb_dcache) // have r_dcache_unc_req + else if ( r_dcache_unc_req ) { - r_vci_cmd_fsm = CMD_DATA_UNC; - r_vci_cmd_num_cache = dcache_unc_num_cache; - r_dcache_unc_req[dcache_unc_num_cache] = false; - // m_cpt_data_unc_transaction++; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - addr_40 addr = (addr_40) r_dcache_addr_save[dcache_unc_num_cache].read() & ~0x3; - set_num_dcache(addr,dcache_unc_num_cache); - - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "CMD DATA UNC " - << "(" << dcache_unc_num_cache << ") " - << std::hex - << " @ " << std::setw(10) << (blob_t)addr - << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" - << std::dec - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION + r_vci_cmd_fsm = CMD_DATA_UNC; + r_dcache_unc_req = false; + // m_cpt_data_unc_transaction++; } // 3 - Instruction Miss - else if (icache_miss_req and r_wbuf[icache_miss_num_cache]->miss(addr)) - //else if (icache_miss_req and r_wbuf[dcache_miss_num_cache]->miss(addr)) + else if (icache_miss_req and r_wbuf.miss(r_icache_addr_save)) { - r_vci_cmd_fsm = CMD_INS_MISS; - r_vci_cmd_num_cache = icache_miss_num_cache; - r_icache_miss_req[icache_miss_num_cache] = false; + r_vci_cmd_fsm = CMD_INS_MISS; + r_icache_miss_req = false; m_cpt_imiss_transaction++; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "CMD INS MISS " - << "(" << icache_miss_num_cache << ") " - << std::hex - << " @ " << std::setw(10) << (blob_t)addr - << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")" - << std::dec - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION } // 4 - Instruction Uncachable - else if (icache_unc_num_cache < m_nb_icache) // have r_icache_unc_req + else if ( r_icache_unc_req ) { - r_vci_cmd_fsm = CMD_INS_UNC; - r_vci_cmd_num_cache = icache_unc_num_cache; - r_icache_unc_req[icache_unc_num_cache] = false; + r_vci_cmd_fsm = CMD_INS_UNC; + r_icache_unc_req = false; // m_cpt_ins_unc_transaction++; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - addr_40 addr = (addr_40) r_icache_addr_save[icache_unc_num_cache].read() & ~0x3; - set_num_dcache(addr,icache_unc_num_cache); - - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "CMD INS UNC " - << "(" << icache_unc_num_cache << ") " - << std::hex - << " @ " << std::setw(10) << (blob_t)addr - << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_icache_yzmask) << ")" - << std::dec - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION } // 5 - Data Write - else if (dcache_write_num_cache < m_nb_dcache) // have r_wbuf.rok(&wbuf_min, &wbuf_max) + else if ( r_wbuf.rok(&min, &max) ) { - r_vci_cmd_num_cache = dcache_write_num_cache; - r_vci_cmd_fsm = CMD_DATA_WRITE; - r_vci_cmd_cpt = wbuf_min; - r_vci_cmd_min = wbuf_min; - r_vci_cmd_max = wbuf_max; + r_vci_cmd_fsm = CMD_DATA_WRITE; + r_vci_cmd_cpt = min; + r_vci_cmd_min = min; + r_vci_cmd_max = max; m_cpt_data_write_transaction++; - m_length_write_transaction += (wbuf_max-wbuf_min+1); - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - addr_40 addr = (addr_40) wbuf_addr&~0x3; - - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "CMD DATA WRITE " - << "(" << dcache_write_num_cache << ") " - << std::hex - << " @ " << std::setw(10) << (blob_t)addr - << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" - << " [" << wbuf_min << ":" << wbuf_max << "]" - << " {" << wbuf_index << "}" - << std::dec - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION + m_length_write_transaction += (max-min+1); } // 6 - Data Store Conditionnal - else if (dcache_sc_num_cache < m_nb_dcache) // have r_dcache_sc_req + else if ( r_dcache_sc_req ) { - r_vci_cmd_fsm = CMD_DATA_SC; - r_vci_cmd_num_cache = dcache_sc_num_cache; - r_vci_cmd_max = 1; + r_vci_cmd_fsm = CMD_DATA_SC; + r_vci_cmd_max = 1; m_cpt_unc_transaction++; - r_dcache_sc_req[dcache_sc_num_cache] = false; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - addr_40 addr = (addr_40) r_dcache_addr_save[dcache_sc_num_cache].read() & ~0x3; - set_num_dcache(addr,dcache_sc_num_cache); - - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "CMD DATA SC " - << "(" << dcache_sc_num_cache << ") " - << std::hex - << " @ " << std::setw(10) << (blob_t)addr - << " (L " << std::setw(10) << ((blob_t)addr&(blob_t)m_dcache_yzmask) << ")" - << std::dec - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION + r_dcache_sc_req = false; } @@ -3636,5 +2283,5 @@ if (r_vci_cmd_cpt == r_vci_cmd_max) { r_vci_cmd_fsm = CMD_IDLE ; - r_wbuf[r_vci_cmd_num_cache]->sent() ; + r_wbuf.sent() ; } } @@ -3692,110 +2339,19 @@ if( p_vci_ini_rw.rspval.read() ) { - PRINTF(" * have rsp - trdid : %x - num_cache : %d\n",(uint32_t)p_vci_ini_rw.rtrdid.read(),(uint32_t)p_vci_ini_rw.rpktid.read()); - - ASSERT(p_vci_ini_rw.rpktid.read() <= (1< have rsp - trdid : %x\n",(uint32_t)p_vci_ini_rw.rtrdid.read()); r_vci_rsp_cpt = 0; if ((p_vci_ini_rw.rtrdid.read()>>(vci_param::T-1)) != 0 ) - { r_vci_rsp_fsm = RSP_DATA_WRITE; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "RSP DATA WRITE " - << "(" << p_vci_ini_rw.rpktid.read() << ") " - << "{" << (p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1))) << "}" - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - } else { switch (p_vci_ini_rw.rtrdid.read()) { - case TYPE_INS_MISS : - { - r_vci_rsp_fsm = RSP_INS_MISS; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "RSP INS MISS " - << "(" << p_vci_ini_rw.rpktid.read() << ") " - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - - break; - } - case TYPE_INS_UNC : - { - r_vci_rsp_fsm = RSP_INS_UNC; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "RSP INS UNC " - << "(" << p_vci_ini_rw.rpktid.read() << ") " - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - - break; - } - case TYPE_DATA_MISS : - { - r_vci_rsp_fsm = RSP_DATA_MISS; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "RSP DATA MISS " - << "(" << p_vci_ini_rw.rpktid.read() << ") " - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - - break; - } - case TYPE_DATA_UNC : - { - r_vci_rsp_fsm = RSP_DATA_UNC; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "RSP DATA UNC " - << "(" << p_vci_ini_rw.rpktid.read() << ") " - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - - break; - } - case TYPE_DATA_SC : - { - r_vci_rsp_fsm = RSP_DATA_SC; - -#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - { - log_transaction_file_cmd - << "[" << m_cpt_total_cycles << "] " - << "RSP DATA SC " - << "(" << p_vci_ini_rw.rpktid.read() << ") " - << std::endl; - } -#endif //CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION - - break; - } + case TYPE_INS_MISS : r_vci_rsp_fsm = RSP_INS_MISS; break; + case TYPE_INS_UNC : r_vci_rsp_fsm = RSP_INS_UNC; break; + case TYPE_DATA_MISS : r_vci_rsp_fsm = RSP_DATA_MISS; break; + case TYPE_DATA_UNC : r_vci_rsp_fsm = RSP_DATA_UNC; break; + case TYPE_DATA_SC : r_vci_rsp_fsm = RSP_DATA_SC; break; default : { @@ -3804,6 +2360,4 @@ } } - - r_vci_rsp_num_cache = p_vci_ini_rw.rpktid.read(); } break; @@ -3812,7 +2366,7 @@ m_cost_imiss_transaction++; - PRINTF(" * rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t)s_vci_rsp_ack); - - if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) + PRINTF(" * rspval/ack : %d - %d\n",(uint32_t)p_vci_ini_rw.rspval.read(), (uint32_t)r_vci_rsp_ack); + + if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) { PRINTF(" * have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words); @@ -3822,5 +2376,5 @@ "The VCI response packet for instruction miss is too long" ); r_vci_rsp_cpt = r_vci_rsp_cpt + 1; - CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_num_cache,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); + CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); if ( p_vci_ini_rw.reop.read() ) { @@ -3829,5 +2383,5 @@ ASSERT( ((r_vci_rsp_cpt == m_icache_words - 1) or p_vci_ini_rw.rerror.read() or - (r_vci_rsp_ins_error[r_vci_rsp_num_cache].read()&0x1)), + (r_vci_rsp_ins_error.read()&0x1)), "The VCI response packet for instruction miss is too short"); r_vci_rsp_cpt = 0; @@ -3835,5 +2389,5 @@ } - if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error[r_vci_rsp_num_cache] = true; + if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true; } break; @@ -3842,14 +2396,14 @@ m_cost_imiss_transaction++; - if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) + if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) { ASSERT(p_vci_ini_rw.reop.read(), "illegal VCI response packet for uncached instruction"); - CACHE_MISS_BUF_RSP_PUSH(i,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read()); + CACHE_MISS_BUF_RSP_PUSH(i,0,(data_t)p_vci_ini_rw.rdata.read()); r_vci_rsp_fsm = RSP_IDLE; - if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error[r_vci_rsp_num_cache] = true; + if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true; } break; @@ -3858,5 +2412,5 @@ m_cost_dmiss_transaction++; - if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) + if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) { PRINTF(" * have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read()); @@ -3866,19 +2420,20 @@ r_vci_rsp_cpt = r_vci_rsp_cpt + 1; - CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); + CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_cpt,(data_t)p_vci_ini_rw.rdata.read()); if ( p_vci_ini_rw.reop.read() ) { ASSERT( ((r_vci_rsp_cpt == m_dcache_words - 1) or (p_vci_ini_rw.rerror.read()&0x1) - or r_vci_rsp_data_error[r_vci_rsp_num_cache].read()), + or r_vci_rsp_data_error.read()), "illegal VCI response packet for data read miss"); r_vci_rsp_cpt = 0; r_vci_rsp_fsm = RSP_IDLE; } - if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true; + if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; } break; case RSP_DATA_WRITE: + m_cost_write_transaction++; if (p_vci_ini_rw.rspval.read()) @@ -3889,14 +2444,12 @@ "A VCI response packet must contain one flit for a write transaction"); r_vci_rsp_fsm = RSP_IDLE; - uint32_t wbuf_index = p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)); - bool cached = r_wbuf[r_vci_rsp_num_cache]->completed(wbuf_index); + bool cached = r_wbuf.completed(p_vci_ini_rw.rtrdid.read() - (1<<(vci_param::T-1)) ); PRINTF(" * cached : %d\n",cached); if (not cached) - r_dcache_previous_unc[r_vci_rsp_num_cache] = false; - - if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) - m_iss[r_wbuf[r_vci_rsp_num_cache]->getCpuId(wbuf_index)]->setWriteBerr(); + r_dcache_previous_unc = false; + + if ((p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL) m_iss.setWriteBerr(); } break; @@ -3904,15 +2457,15 @@ case RSP_DATA_UNC: m_cost_unc_transaction++; - if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) + if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) { ASSERT(p_vci_ini_rw.reop.read(), "illegal VCI response packet for data read uncached"); - CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read()); + CACHE_MISS_BUF_RSP_PUSH(d,0,(data_t)p_vci_ini_rw.rdata.read()); r_vci_rsp_fsm = RSP_IDLE; - r_dcache_previous_unc[r_vci_rsp_num_cache] = false; - - if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true; + r_dcache_previous_unc = false; + + if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; } break; @@ -3920,15 +2473,15 @@ case RSP_DATA_SC: m_cost_unc_transaction++; - if (p_vci_ini_rw.rspval.read() and s_vci_rsp_ack) + if (p_vci_ini_rw.rspval.read() and r_vci_rsp_ack) { ASSERT(p_vci_ini_rw.reop.read(), "illegal VCI response packet for data SC"); - CACHE_MISS_BUF_RSP_PUSH(d,r_vci_rsp_num_cache,0,(data_t)p_vci_ini_rw.rdata.read()); + CACHE_MISS_BUF_RSP_PUSH(d,0,(data_t)p_vci_ini_rw.rdata.read()); r_vci_rsp_fsm = RSP_IDLE; - r_dcache_previous_unc[r_vci_rsp_num_cache] = false; - - if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error[r_vci_rsp_num_cache] = true; + r_dcache_previous_unc = false; + + if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true; } break; @@ -3936,5 +2489,5 @@ } // end switch r_vci_rsp_fsm - } // end transition() + } // end transition() ////////////////////////////////////////////////////////////////////////////////// @@ -3942,67 +2495,36 @@ ////////////////////////////////////////////////////////////////////////////////// { - PRINTF("--------------------------------------------\n"); - PRINTF(" * CC_XCACHE_WRAPPER \"%s\" genMoore - Time = %d\n",name().c_str(),(uint32_t)m_cpt_total_cycles); // VCI initiator response switch ( r_cleanup_fsm.read() ) { + case CLEANUP_IDLE: p_vci_ini_c.rspack = false; - p_vci_ini_c.cmdval = false; - p_vci_ini_c.address = 0; - p_vci_ini_c.wdata = 0; - p_vci_ini_c.be = 0; - p_vci_ini_c.plen = 0; - p_vci_ini_c.cmd = vci_param::CMD_WRITE; - p_vci_ini_c.trdid = 0; - p_vci_ini_c.pktid = 0; - p_vci_ini_c.srcid = 0; - p_vci_ini_c.cons = false; - p_vci_ini_c.wrap = false; - p_vci_ini_c.contig = false; - p_vci_ini_c.clen = 0; - p_vci_ini_c.cfixed = false; - p_vci_ini_c.eop = false; - break; - - case CLEANUP_REQ: - { - addr_40 addr; - if (r_cleanup_icache) - { - addr = r_icache_cleanup_line[r_cleanup_num_cache].read()< icache : %llx\n",(blob_t)addr); + p_vci_ini_c.cmdval = r_icache_cleanup_req || r_dcache_cleanup_req; + if ( r_dcache_cleanup_req ) + { + p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words << 2); + p_vci_ini_c.trdid = TYPE_DATA_CLEANUP; } else { - addr = r_dcache_cleanup_line[r_cleanup_num_cache].read()< dcache : %llx\n",(blob_t)addr); - } - - p_vci_ini_c.rspack = false; - p_vci_ini_c.cmdval = true; - p_vci_ini_c.address = addr; - p_vci_ini_c.wdata = 0; - p_vci_ini_c.be = 0xF; - p_vci_ini_c.plen = 4; - p_vci_ini_c.cmd = vci_param::CMD_WRITE; - p_vci_ini_c.trdid = (r_cleanup_icache)?TYPE_INS_CLEANUP:TYPE_DATA_CLEANUP; - p_vci_ini_c.pktid = (sc_dt::sc_uint)r_cleanup_num_cache; - p_vci_ini_c.srcid = m_srcid_c; - p_vci_ini_c.cons = false; - p_vci_ini_c.wrap = false; - p_vci_ini_c.contig = false; - p_vci_ini_c.clen = 0; - p_vci_ini_c.cfixed = false; - p_vci_ini_c.eop = true; - - break; - } - - case CLEANUP_RSP_DCACHE: + p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words << 2); + p_vci_ini_c.trdid = TYPE_INS_CLEANUP; + } + p_vci_ini_c.wdata = 0; + p_vci_ini_c.be = 0xF; + p_vci_ini_c.plen = 4; + p_vci_ini_c.cmd = vci_param::CMD_WRITE; + p_vci_ini_c.pktid = 0; + p_vci_ini_c.srcid = m_srcid_c; + p_vci_ini_c.cons = false; + p_vci_ini_c.wrap = false; + p_vci_ini_c.contig = false; + p_vci_ini_c.clen = 0; + p_vci_ini_c.cfixed = false; + p_vci_ini_c.eop = true; + break; + + case CLEANUP_DCACHE: p_vci_ini_c.rspack = true; p_vci_ini_c.cmdval = false; @@ -4023,5 +2545,5 @@ break; - case CLEANUP_RSP_ICACHE: + case CLEANUP_ICACHE: p_vci_ini_c.rspack = true; p_vci_ini_c.cmdval = false; @@ -4046,6 +2568,6 @@ switch (r_vci_cmd_fsm.read() ) { + case CMD_IDLE: - { p_vci_ini_rw.cmdval = false; p_vci_ini_rw.address = 0; @@ -4065,19 +2587,12 @@ break; - } + case CMD_DATA_UNC: - { p_vci_ini_rw.cmdval = true; - - addr_40 addr = (addr_40) r_dcache_addr_save[r_vci_cmd_num_cache].read() & ~0x3; - set_num_dcache(addr,r_vci_cmd_num_cache); - - PRINTF(" * DATA_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); - - p_vci_ini_rw.address = addr; - switch( r_dcache_type_save[r_vci_cmd_num_cache] ) { + p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3; + switch( r_dcache_type_save ) { case iss_t::DATA_READ: p_vci_ini_rw.wdata = 0; - p_vci_ini_rw.be = r_dcache_be_save[r_vci_cmd_num_cache].read(); + p_vci_ini_rw.be = r_dcache_be_save.read(); p_vci_ini_rw.cmd = vci_param::CMD_READ; break; @@ -4092,5 +2607,5 @@ p_vci_ini_rw.plen = 4; p_vci_ini_rw.trdid = TYPE_DATA_UNC; // data cache uncached read - p_vci_ini_rw.pktid = (sc_dt::sc_uint)r_vci_cmd_num_cache; + p_vci_ini_rw.pktid = 0; p_vci_ini_rw.srcid = m_srcid_rw; p_vci_ini_rw.cons = false; @@ -4102,15 +2617,8 @@ break; - } + case CMD_DATA_SC: - { p_vci_ini_rw.cmdval = true; - - addr_40 addr = (addr_40) r_dcache_addr_save[r_vci_cmd_num_cache].read() & ~0x3; - set_num_dcache(addr,r_vci_cmd_num_cache); - - PRINTF(" * DATA_SC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); - - p_vci_ini_rw.address = addr; + p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3; if(r_vci_cmd_max.read() == 3){ ASSERT(false, "Not handled yet"); @@ -4118,8 +2626,8 @@ switch(r_vci_cmd_cpt.read()){ case 0: - p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data[r_vci_cmd_num_cache][r_dcache_num_cpu_save[r_vci_cmd_num_cache]].read() & 0xFFFFFFFF); + p_vci_ini_rw.wdata = (uint32_t)(r_dcache_ll_data.read() & 0xFFFFFFFF); break; case 1: - p_vci_ini_rw.wdata = r_dcache_wdata_save[r_vci_cmd_num_cache].read(); + p_vci_ini_rw.wdata = r_dcache_wdata_save.read(); break; } @@ -4129,5 +2637,5 @@ p_vci_ini_rw.plen = 4*(r_vci_cmd_max.read()+1); p_vci_ini_rw.trdid = TYPE_DATA_SC; // data cache uncached read - p_vci_ini_rw.pktid = (sc_dt::sc_uint)r_vci_cmd_num_cache; + p_vci_ini_rw.pktid = 0; p_vci_ini_rw.srcid = m_srcid_rw; p_vci_ini_rw.cons = true; @@ -4139,20 +2647,14 @@ break; - } + case CMD_DATA_WRITE: - { p_vci_ini_rw.cmdval = true; - - addr_40 addr = (addr_40) r_wbuf[r_vci_cmd_num_cache]->getAddress(r_vci_cmd_cpt)&~0x3; - - PRINTF(" * DATA_WRITE : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); - - p_vci_ini_rw.address = addr; - p_vci_ini_rw.wdata = r_wbuf[r_vci_cmd_num_cache]->getData(r_vci_cmd_cpt); - p_vci_ini_rw.be = r_wbuf[r_vci_cmd_num_cache]->getBe(r_vci_cmd_cpt); + p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3; + p_vci_ini_rw.wdata = r_wbuf.getData(r_vci_cmd_cpt); + p_vci_ini_rw.be = r_wbuf.getBe(r_vci_cmd_cpt); p_vci_ini_rw.plen = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2; p_vci_ini_rw.cmd = vci_param::CMD_WRITE; - p_vci_ini_rw.trdid = r_wbuf[r_vci_cmd_num_cache]->getIndex() + (1<<(vci_param::T-1)); - p_vci_ini_rw.pktid = (sc_dt::sc_uint)r_vci_cmd_num_cache; + p_vci_ini_rw.trdid = r_wbuf.getIndex() + (1<<(vci_param::T-1)); + p_vci_ini_rw.pktid = 0; p_vci_ini_rw.srcid = m_srcid_rw; p_vci_ini_rw.cons = false; @@ -4164,20 +2666,13 @@ break; - } + case CMD_DATA_MISS: - { p_vci_ini_rw.cmdval = true; - - addr_40 addr = r_dcache_addr_save[r_vci_cmd_num_cache].read() & (addr_40) m_dcache_yzmask; - set_num_dcache(addr,r_vci_cmd_num_cache); - - PRINTF(" * DATA_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); - - p_vci_ini_rw.address = addr; + p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask; p_vci_ini_rw.be = 0xF; p_vci_ini_rw.plen = m_dcache_words << 2; p_vci_ini_rw.cmd = vci_param::CMD_READ; p_vci_ini_rw.trdid = TYPE_DATA_MISS; // data cache cached read - p_vci_ini_rw.pktid = (sc_dt::sc_uint)r_vci_cmd_num_cache; + p_vci_ini_rw.pktid = 0; p_vci_ini_rw.srcid = m_srcid_rw; p_vci_ini_rw.cons = false; @@ -4189,20 +2684,13 @@ break; - } + case CMD_INS_MISS: - { p_vci_ini_rw.cmdval = true; - - addr_40 addr = r_icache_addr_save[r_vci_cmd_num_cache].read() & (addr_40) m_icache_yzmask; - set_num_icache(addr,r_vci_cmd_num_cache); - - PRINTF(" * INS_MISS : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); - - p_vci_ini_rw.address = addr; + p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask; p_vci_ini_rw.be = 0xF; p_vci_ini_rw.plen = m_icache_words << 2; p_vci_ini_rw.cmd = vci_param::CMD_READ; p_vci_ini_rw.trdid = TYPE_INS_MISS; // ins cache cached read - p_vci_ini_rw.pktid = (sc_dt::sc_uint)r_vci_cmd_num_cache; + p_vci_ini_rw.pktid = 0; p_vci_ini_rw.srcid = m_srcid_rw; p_vci_ini_rw.cons = false; @@ -4214,20 +2702,13 @@ break; - } + case CMD_INS_UNC: - { p_vci_ini_rw.cmdval = true; - - addr_40 addr = r_icache_addr_save[r_vci_cmd_num_cache].read() & ~0x3; - set_num_icache(addr,r_vci_cmd_num_cache); - - PRINTF(" * INS_UNC : %d - %llx\n",(uint32_t)r_vci_cmd_num_cache,(blob_t)(addr)); - - p_vci_ini_rw.address = addr; + p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3; p_vci_ini_rw.be = 0xF; p_vci_ini_rw.plen = 4; p_vci_ini_rw.cmd = vci_param::CMD_READ; p_vci_ini_rw.trdid = TYPE_INS_UNC; // ins cache uncached read - p_vci_ini_rw.pktid = (sc_dt::sc_uint)r_vci_cmd_num_cache; + p_vci_ini_rw.pktid = 0; p_vci_ini_rw.srcid = m_srcid_rw; p_vci_ini_rw.cons = false; @@ -4239,32 +2720,23 @@ break; - } + } // end switch r_vci_cmd_fsm - { - bool ack; - - switch (r_vci_rsp_fsm.read() ) { - case RSP_DATA_WRITE : ack = true; break; - case RSP_INS_MISS : - case RSP_INS_UNC : ack = CACHE_MISS_BUF_RSP_ACK(i,r_vci_rsp_num_cache); break; - case RSP_DATA_MISS : - case RSP_DATA_UNC : - case RSP_DATA_SC : ack = CACHE_MISS_BUF_RSP_ACK(d,r_vci_rsp_num_cache); break; - - case RSP_IDLE : - default : ack = false; break; - - } // end switch r_vci_cmd_fsm - - s_vci_rsp_ack = ack; - p_vci_ini_rw.rspack = ack; - - PRINTF(" * rspack : %d\n", ack); - } - + bool ack; + + switch (r_vci_rsp_fsm.read() ) { + case RSP_IDLE : ack = false; break; + case RSP_DATA_WRITE : ack = true; break; + case RSP_INS_MISS : + case RSP_INS_UNC : ack = CACHE_MISS_BUF_RSP_ACK(i); break; + case RSP_DATA_MISS : + case RSP_DATA_UNC : + case RSP_DATA_SC : ack = CACHE_MISS_BUF_RSP_ACK(d); break; + } // end switch r_vci_cmd_fsm + + r_vci_rsp_ack = ack; + p_vci_ini_rw.rspack = ack; + // VCI_TGT - - // PRINTF(" * srcid : %d\n", r_tgt_srcid.read()); switch ( r_vci_tgt_fsm.read() ) { @@ -4278,68 +2750,36 @@ case TGT_RSP_BROADCAST: - { - bool tgt_icache_req; - bool tgt_icache_rsp; - -#if (CC_XCACHE_WRAPPER_MULTI_CACHE==1) - tgt_icache_req = r_tgt_icache_req[r_tgt_num_cache].read(); - tgt_icache_rsp = r_tgt_icache_rsp[r_tgt_num_cache].read(); -#elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2) - tgt_icache_req = false; - tgt_icache_rsp = false; - for (uint32_t num_cache=0; num_cache RSP_BROADCAST : rspval : %d (i %d %d, d %d %d)\n",rspval,tgt_icache_req,tgt_icache_rsp, r_tgt_dcache_req[r_tgt_num_cache].read(), r_tgt_dcache_rsp[r_tgt_num_cache].read()); - - p_vci_tgt.cmdack = false; - p_vci_tgt.rspval = rspval; - p_vci_tgt.rsrcid = r_tgt_srcid.read(); - p_vci_tgt.rpktid = r_tgt_pktid.read(); - p_vci_tgt.rtrdid = r_tgt_trdid.read(); - p_vci_tgt.rdata = 0; - p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK - p_vci_tgt.reop = true; - break; - } + p_vci_tgt.cmdack = false; + p_vci_tgt.rspval = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() and ( r_tgt_icache_rsp | r_tgt_dcache_rsp ); + p_vci_tgt.rsrcid = r_tgt_srcid.read(); + p_vci_tgt.rpktid = r_tgt_pktid.read(); + p_vci_tgt.rtrdid = r_tgt_trdid.read(); + p_vci_tgt.rdata = 0; + p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK + p_vci_tgt.reop = true; + break; + case TGT_RSP_ICACHE: - { - bool rspval = not r_tgt_icache_req[r_tgt_num_cache].read() and r_tgt_icache_rsp[r_tgt_num_cache].read(); - - PRINTF(" * RSP_ICACHE : rspval : %d\n",rspval); - - p_vci_tgt.cmdack = false; - p_vci_tgt.rspval = rspval; - p_vci_tgt.rsrcid = r_tgt_srcid.read(); - p_vci_tgt.rpktid = r_tgt_pktid.read(); - p_vci_tgt.rtrdid = r_tgt_trdid.read(); - p_vci_tgt.rdata = 0; - p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK - p_vci_tgt.reop = true; - break; - } + p_vci_tgt.cmdack = false; + p_vci_tgt.rspval = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read(); + p_vci_tgt.rsrcid = r_tgt_srcid.read(); + p_vci_tgt.rpktid = r_tgt_pktid.read(); + p_vci_tgt.rtrdid = r_tgt_trdid.read(); + p_vci_tgt.rdata = 0; + p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK + p_vci_tgt.reop = true; + break; + case TGT_RSP_DCACHE: - { - bool rspval = not r_tgt_dcache_req[r_tgt_num_cache].read() and r_tgt_dcache_rsp[r_tgt_num_cache].read(); - - PRINTF(" * RSP_DCACHE : rspval : %d\n",rspval); - - p_vci_tgt.cmdack = false; - p_vci_tgt.rspval = rspval; - p_vci_tgt.rsrcid = r_tgt_srcid.read(); - p_vci_tgt.rpktid = r_tgt_pktid.read(); - p_vci_tgt.rtrdid = r_tgt_trdid.read(); - p_vci_tgt.rdata = 0; - p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK - p_vci_tgt.reop = true; - break; - } + p_vci_tgt.cmdack = false; + p_vci_tgt.rspval = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read(); + p_vci_tgt.rsrcid = r_tgt_srcid.read(); + p_vci_tgt.rpktid = r_tgt_pktid.read(); + p_vci_tgt.rtrdid = r_tgt_trdid.read(); + p_vci_tgt.rdata = 0; + p_vci_tgt.rerror = 0x2 & ( (1 << vci_param::E) - 1); // Write OK + p_vci_tgt.reop = true; + break; + case TGT_REQ_BROADCAST: case TGT_REQ_ICACHE: @@ -4374,43 +2814,4 @@ } - ////////////////////////////////////////////////////////////////////////////////// - tmpl(uint32_t)::get_num_cache(addr_40 & addr) - ////////////////////////////////////////////////////////////////////////////////// - { - uint32_t num_cache = get_num_cache_only(addr); - - addr = ((addr&m_num_cache_LSB_mask) | // keep LSB - ((addr>>m_num_cache_MSB)<>m_num_cache_LSB)&m_num_cache_mask; - } - - ////////////////////////////////////////////////////////////////////////////////// - tmpl(void)::set_num_cache(addr_40 & addr, uint32_t num_cache) - ////////////////////////////////////////////////////////////////////////////////// - { - addr = ((addr&m_num_cache_LSB_mask) | // keep LSB - ((addr_40)num_cache << m_num_cache_LSB) | - ((addr>>m_num_cache_LSB)<)::set_num_cache_only(addr_40 addr, uint32_t num_cache) - ////////////////////////////////////////////////////////////////////////////////// - { - return ((addr&m_num_cache_LSB_mask) | // keep LSB - ((addr_40)num_cache << m_num_cache_LSB) | - ((addr>>m_num_cache_LSB)<